DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Inventorship
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/22/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-6 and 8-14 is/are rejected under 35 U.S.C. 102a1/a2 as being anticipated by Wilcox et al. (US 5481178).
Claims 1, 2 and 8; Wilcox et al disclose a controller (470), and method, for a switching regulator receiving an input voltage (VIN), the controller controlling a high-side switch (16) and a low-side switch (17) connected in series between the input voltage and a ground potential and configured to drive a switching node for generating a switching voltage, the switching node being coupled to an LC filter circuit (32, 34) including an inductor (32) and a capacitor (34) to generate a regulated output voltage (Vout) having a substantially constant magnitude on an output node, the regulated output voltage being fed back to the controller as a feedback voltage (36A, 36B), the controller (470) comprising: a control circuit (e.g. R1/R2, 37, 38, 39, 25, 20) configured to receive a first error signal (from 38) indicative of a difference between a feedback voltage (VFB) indicative of the regulated output voltage and a reference voltage (37), the control circuit configured to generate first and second pulse width modulation signals (e.g. 20) for driving the high-side switch (16) and the low-side switch (17), the first and second PWM signals being coupled to turn the high-side switch and the low-side switch on and off alternately to generate the switching voltage at the switching node; and a protection circuit (471, I4, 472, 25, 39) configured to monitor a current sense signal (IFB2) indicative of an inductor current flowing through the inductor (32) and responsive to the current sense signal indicating a negative current (471A) flowing through the inductor (32) has reached a negative current threshold (471B: e.g. falling below I4), the protection circuit generates control signals to turn off the low-side switch (17) and to turn on the high-side switch (one-shot will turn 16 ON); and the protection circuit continues to monitor the current sense signal and responsive to the current sense signal indicating the negative current has recovered to a negative current recovery level (exceeding I4: col. 14 lines 46-54; after N-MOSFET 17 is turned OFF, it will again be allowed to turn ON as soon as feedback current IFB2 exceeds current I4 to cause comparator output 471c to go HIGH. Comparator output 471c will again go HIGH after one-shot circuit 25 turns P-MOSFET 16 ON, which, in turn, causes the inductor current IL to again ramp up. Ramping up will allow current feedback signal IFB2 to exceed I4 and, cause comparator output 471c to go HIGH) before a predetermined maximum on time (ONE-SHOT) of the high-side switch, the protection circuit generates the control signals to turn off the high-side switch and to turn on the low-side switch.
Claims 3 and 9; FET 17 is held OFF until IFB2 exceeds current source I4; thus, if FET 16 is turned ON by one-shot 25, FET 16 will turn OFF while FET 17 is still OFF.
Claims 4 and 10; FET 17 will again be allowed to turn ON as soon as feedback current IFB2 exceeds current I4.
Claims 5 and 11; col. 13 line 50 discloses the FETs have body diodes. Thus, even when FET 16 turns OFF, the body diode can still conduct current.
Claim 6; col. 16 line 23.
Claim 12; responsive to the high-side switch being turned on, the high-side switch could conduct negative current.
Claim 13; receiving a first error signal (38) indicative of a difference between a feedback voltage (VFB) indicative of the regulated output voltage and a reference voltage (37); and generating first and second pulse width modulation signals (Wilcox et al. disclose the pulses can be fixed or variable) for driving the high-side switch (16) and the low-side switch (17), the first and second PWM signals being coupled to turn the high-side switch and the low-side switch on and off alternately (e.g. complementary) to generate the switching voltage at the switching node, wherein the control signals generated in response to the current sense signal or the predetermined maximum on time override the PWM signals.
Claim 14; col. 16 line 23.
Allowable Subject Matter
Claim 7 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Prior art fails to disclose or fairly suggest, inter alia, the protection circuit comprises: a first comparator configured to receive the current sense signal and the negative current threshold and to generate a first output signal; a second comparator configured to receive the current sense signal and the negative current recovery level and to generate a second output signal; a set-reset latch having a set input terminal configured to receive the first output signal, a reset input terminal configured to receive the second output signal, the set-reset latch generating a third output signal and a fourth output signal being an inverse of the third output signal, the third output signal having a first logical state in response to the first output signal being asserted and having a second logical state in response to the second output signal being asserted; and a one-shot timer circuit configured to receive the third output signal and to generate a fifth output signal, wherein in response to the third output signal transitioning to the first logical state, the one-shot timer circuit generates the fifth output signal having the first logical state for the predetermined maximum on time, wherein the fifth output signal is the control signal for driving the high-side switch and the fourth output signal is the control signal for driving the low-side switch.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GARY L LAXTON whose telephone number is (571)272-2079. The examiner can normally be reached Monday-Friday, 8 am-4 pm.
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/GARY L LAXTON/ Primary Examiner, Art Unit 2838 7/24/2026
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