DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 7 and 14 are objected to because of the following informalities:
For claim 7, Examiner believes this claim should be amended in the following manner:
The device of claim 6, wherein each of the plurality of 3D basis LUTs corresponds to one of a plurality of different predetermined lighting conditions.
For claim 14, Examiner believes this claim should be amended in the following manner:
The device of claim 13, wherein each of the plurality of 3D basis LUTs corresponds to one of a plurality of different predetermined lighting conditions.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 5, 6, 9, 18 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al., AdaInt: Learning Adaptive Intervals for 3D Lookup Tables on Real-time Image Enhancement, Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2022 (hereinafter “Yang”) (made of record of the IDS submitted 12/22/2024) in view of Cha et al. (U.S. Patent Application Publication 2021/0383498 A1, hereinafter “Cha”).
For claim 1, Yang discloses a device (disclosing an Nvidia Tesla V100 graphics processing unit (GPU) as a device (page 17527)), comprising: a memory capable of storing a non-uniform 3-dimensional lookup table (3D LUT) specifying color correction data (disclosing GPU memory for storing non-uniform 3D LUT for specifying data to perform color correction (pages 17524, 17527 and 17529)); wherein, for one or more of a red dimension, a green dimension, or a blue dimension, the non-uniform 3D LUT includes a number of color correction values within one or more first light ranges of the non-uniform 3D LUT that exceeds a number of color correction values included within one or more second light ranges of the non-uniform 3D LUT (disclosing, for the red, green and blue dimensions, the non-uniform 3-D LUT includes a higher number of sampling points and corresponding output color values as color correction values for color (light) ranges requiring highly non-linear transforms and a lower number of sampling points and corresponding output color values as color correction values for color (light) ranges that are strongly linear (pages 17523-17524/Fig. 2)); and capable of transforming a source frame into a color corrected frame using the non-uniform 3D LUT (disclosing transformation of an input image (source frame) into an enhanced image as a color corrected frame using the non-uniform 3-D LUT (page 17524/Fig. 2 and page 17529)).
Yang does not specifically disclose a memory circuit and a color correcting circuit.
However, these limitations are well-known in the art as disclosed in Cha.
Cha similarly discloses a device of a processor to perform image frame processing (par. 4-5 and 117-118). Cha explains it is known for a processor to be implemented in processing circuitry of a combination of logic circuits including a memory circuit and a circuit to perform color correction as a color correcting circuit (par. 118, 124, 147 and 158). It follows Yang may be accordingly modified with the teachings of Cha to implement its memory as a memory circuit for storing its non-uniform 3D LUT and a color correcting circuit to perform its color correction with its non-uniform 3D LUT.
A person having ordinary skill in the art (PHOSITA) before the effective filing date of the claimed invention would find it obvious to modify Yang with the teachings of Cha. Cha is analogous art in dealing with device of a processor to perform image frame processing (par. 4-5 and 117-118). Cha discloses its use of a combination of logic circuits is advantageous in appropriately implementing and carrying out various functions of a processor (par. 118 and 158). Consequently, a PHOSITA would incorporate the teachings of Cha into Yang for appropriately implementing and carrying out various functions of a processor. Therefore, claim 1 is rendered obvious to a PHOSITA before the effective filing date of the claimed invention.
For claim 5, depending on claim 1, Yang as modified by Cha discloses wherein the non-uniform 3D LUT is adapted to the source frame (Yang discloses the non-uniform 3D LUT is adapted to the input image (source frame) (pages 17523-17524/Fig. 2)).
For claim 6, depending on claim 1, Yang as modified by Cha discloses further comprising: a weight generation circuit capable of generating a plurality of weights based on the source frame (Yang discloses generating a plurality of weights based on the input image (source frame) (page 17524/Fig. 2); Cha similarly discloses a device of a processor to perform image frame processing (par. 4-5 and 117-118); Cha explains it is known for a processor to be implemented in processing circuitry of a combination of logic circuits (par. 118 and 158); and it follows Yang may be accordingly modified with the teachings of Cha to implement a weight generation circuit to perform its weight generation to appropriately carry out its color correction); and a fuse circuit capable of combining a plurality of 3D basis LUTs using the plurality of weights to generate the non-uniform 3D LUT (Yang discloses combining a plurality of basis 3D LUTs using the plurality of weights to generate the non-uniform 3D LUT; Cha similarly discloses a device of a processor to perform image frame processing (par. 4-5 and 117-118); Cha explains it is known for a processor to be implemented in processing circuitry of a combination of logic circuits (par. 118 and 158); and it follows Yang may be accordingly modified with the teachings of Cha to implement a fuse circuit to perform its combination of its basis 3D LUTs to appropriately carry out its color correction).
For claim 9, depending on claim 1, Yang as modified by Cha discloses wherein a number of color correction values in each of the red dimension, the green dimension, and the blue dimension of the non-uniform 3D LUT is equal (Yang discloses a same (equal) number of sampling points or coordinates with corresponding output color values as color correction values are allocated in each of the red dimension, the green dimension and the blue dimension of the non-uniform 3D LUT).
For claim 18, Yang as modified by Cha discloses a method of color correction for image data (Yang discloses a method of color correction for image data (pages 17524, 17527 and 17529)), comprising: storing a non-uniform 3-dimensional lookup table (3D LUT) specifying color correction data in a memory circuit (Yang discloses GPU memory for storing a non-uniform 3D LUT for specifying data to perform color correction (pages 17524, 17527 and 17529); Cha similarly discloses a device of a processor to perform image frame processing (par. 4-5 and 117-118); Cha explains it is known for a processor to be implemented in processing circuitry of a combination of logic circuits including a memory circuit and a circuit to perform color correction as a color correcting circuit (par. 118, 124, 147 and 158); and it follows Yang may be accordingly modified with the teachings of Cha to implement its memory as a memory circuit for storing its non-uniform 3D LUT and a color correcting circuit to perform its color correction with its non-uniform 3D LUT); wherein, for one or more of a red dimension, a green dimension, or a blue dimension, the non-uniform 3D LUT includes a number of color correction values within one or more first light ranges of the non-uniform 3D LUT that exceeds a number of color correction values included within one or more second light ranges of the non-uniform 3D LUT (Yang discloses, for the red, green and blue dimensions, the non-uniform 3-D LUT includes a higher number of sampling points and corresponding output color values as color correction values for color (light) ranges requiring highly non-linear transforms and a lower number of sampling points and corresponding output color values as color correction values for color (light) ranges that are strongly linear (pages 17523-17524/Fig. 2)); and receiving, from a camera, a source frame (Yang discloses receiving an input image as a source frame (page 17524/Fig. 2); Cha similarly discloses a device of a processor to perform image frame processing (par. 4-5 and 117-118); Cha explains images frames may be received from a camera (par. 121); and it follows Yang may be accordingly modified with the teachings of Cha to receive its source frame from a camera); and transforming the source frame into a color corrected frame using the non-uniform 3D LUT (Yang discloses transformation of an input image (source frame) into an enhanced image as a color corrected frame using the non-uniform 3-D LUT page 17524/Fig. 2 and page 17529)).
For claim 19, depending on claim 18, this claim is a combination of the limitations of claim 18 and claim 6. It follows claim 19 is rejected for the same reasons as to claim 18 and claim 6.
Claim(s) 2 and 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Cha further in view of Elizov et al. (U.S. Patent 11,496,700 B1, hereinafter “Elizov”).
For claim 2, depending on claim 1, Yang as modified by Cha does not disclose at least one of a low light range or a high light range and a medium light range.
However, these limitations are well-known in the art as disclosed in Elizov.
Elizov similarly discloses a system and method for processing image frames (col. 1/lines 49-63). Elizov explains it is known to arrange light ranges with a low luminance range, a high luminance range and a medium luminance range (col. 4/lines 57-67 and col. 5/lines 1-23). It follows Yang and Cha may be accordingly modified with the teachings of Elizov to implement its one or more first light ranges to include at least one of a low light range or a high light range and its one or more second light ranges to include a medium light range.
A PHOSITA before the effective filing date of the claimed invention would find it obvious to modify Yang and Cha with the teachings of Elizov. Elizov is analogous art in dealing with a system and method for processing image frames (col. 1/lines 49-63). Elizov discloses its use of multiple light ranges is advantageous in increasing dynamic range of a processed image to improve resolution (col. 1/lines 13-25; and col. 4/lines 57-67 and col. 5/lines 1-23). Consequently, a PHOSITA would incorporate the teachings of Elizov into Yang and Cha for increasing dynamic range of a processed image to improve resolution. Therefore, claim 2 is rendered obvious to a PHOSITA before the effective filing date of the claimed invention.
For claim 3, depending on claim 2, Yang as modified by Cha discloses wherein the number of color correction values within the one or more first light ranges of the non-uniform 3D LUT that exceeds the number of color correction values included within the one or more second light ranges of the non-uniform 3D LUT occurs within the non-uniform 3D LUT for the red dimension, the green dimension, and the blue dimension (Yang discloses, for the red, green and blue dimensions, the non-uniform 3-D LUT includes a higher number of sampling points and corresponding output color values as color correction values for color (light) ranges requiring highly non-linear transforms and a lower number of sampling points and corresponding output color values as color correction values for color (light) ranges that are strongly linear (pages 17523-17524/Fig. 2)).
Claim(s) 4, 11-13, 16 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Cha further in view of Gvsl et al. (U.S. Patent Application Publication 2019/0362190 A1, hereinafter “Gvsl”).
For claim 4, depending on claim 1, Yang as modified by Cha discloses wherein the source frame is one of a plurality of source frames, the device further comprising: a Visual See-Through (VST) pipeline circuit including the memory circuit and the color correcting circuit (Cha similarly discloses a device of a processor to perform image frame processing where an image frame is one of a plurality of frames (par. 4-5 and 117-118); Cha explains it is known for a processor to be implemented in processing circuitry of a combination of logic circuits including a memory circuit and a circuit to perform color correction as a color correcting circuit (par. 118, 124, 147 and 158); Cha further explains the processing circuitry may be implemented as a pipeline circuit including a plurality of circuits where the pipeline circuit implements augmented reality as a visual see-through pipeline circuit (par. 34, 158 and 160); and it follows Yang may be accordingly modified with the teachings of Cha to implement its memory as a memory circuit for storing its non-uniform 3D LUT and a color correcting circuit to perform its color correction with its non-uniform 3D LUT for inclusion in a visual see-through pipeline circuit for processing its source frame as a plurality of source frames).
Yang as modified by Cha does not specifically disclose frames of a video and transforming the video into a color corrected video in real time.
However, these limitations are well-known in the art as disclosed in Gvsl.
Gvsl similarly discloses a system and method for processing image frames with color correction (par. 11, 16, 111 and 113). Gvsl explains its system may process image frames of a video to transform the video to color corrected video in real time (par. 109 and 113). It follows Yang and Cha may be accordingly modified with the teachings of Gvsl to implement its plurality of source frames in a video where its visual see-through pipeline circuit transforms the video into color corrected video in real time.
A PHOSITA before the effective filing date of the claimed invention would find it obvious to modify Yang and Cha with the teachings of Gvsl. Gvsl is analogous art in dealing with a system and method for processing image frames by color correction (par. 11, 16, 111 and 113). Gvsl discloses its use of real time color correction is advantageous in facilitating real time mobile vision applications to present real time video for display (par. 109). Consequently, a PHOSITA would incorporate the teachings of Gvsl into Yang and Cha for facilitating real time mobile vision applications to present real time video for display. Therefore, claim 4 is rendered obvious to a PHOSITA before the effective filing date of the claimed invention.
For claim 11, Yang as modified by Cha and Gvsl discloses a device (Yang discloses an Nvidia Tesla V100 graphics processing unit (GPU) as a device (page 17527)), comprising: a Visual See-Through (VST) pipeline circuit capable of processing frames in real time (Cha similarly discloses a device of a processor to perform image frame processing where an image frame is one of a plurality of frames (par. 4-5 and 117-118); Cha explains it is known for a processor to be implemented in processing circuitry of a combination of logic circuits including a memory circuit and a circuit to perform color correction as a color correcting circuit (par. 118, 124, 147 and 158); Cha further explains the processing circuitry may be implemented as a pipeline circuit including a plurality of circuits where the pipeline circuit implements augmented reality as a visual see-through pipeline circuit (par. 34, 158 and 160); and it follows Yang may be accordingly modified with the teachings of Cha to implement its memory as a memory circuit for storing its non-uniform 3D LUT and a color correcting circuit to perform its color correction with its non-uniform 3D LUT for inclusion in a visual see-through pipeline circuit for processing its source frame as a plurality of source frames; Gvsl similarly discloses a system and method for processing image frames with color correction (par. 11, 16, 111 and 113); Gvsl explains its system may process image frames of a video to transform the video to color corrected video in real time (par. 109 and 113); and it follows Yang and Cha may be accordingly modified with the teachings of Gvsl to implement its plurality of source frames in a video where its visual see-through pipeline circuit transforms the video into color corrected video in real time), wherein the VST pipeline circuit includes: a memory circuit capable of storing a non-uniform 3-dimensional lookup table (3D LUT) specifying red, green, and blue color correction values for image processing (Yang discloses GPU memory for storing non-uniform 3D LUT for specifying red, green and blue color correction values for image processing (pages 17523-17524/Fig. 2, 17527 and 17529); Cha similarly discloses a device of a processor to perform image frame processing where an image frame is one of a plurality of frames (par. 4-5 and 117-118); Cha explains it is known for a processor to be implemented in processing circuitry of a combination of logic circuits including a memory circuit and a circuit to perform color correction as a color correcting circuit (par. 118, 124, 147 and 158); Cha further explains the processing circuitry may be implemented as a pipeline circuit including a plurality of circuits where the pipeline circuit implements augmented reality as a visual see-through pipeline circuit (par. 34, 158 and 160); and it follows Yang may be accordingly modified with the teachings of Cha to implement its memory as a memory circuit for storing its non-uniform 3D LUT and a color correcting circuit to perform its color correction with its non-uniform 3D LUT for inclusion in a visual see-through pipeline circuit for processing its source frame as a plurality of source frames); and a color correcting circuit capable of transforming a source frame into a color corrected frame using the non-uniform 3D LUT (Yang discloses transformation of an input image (source frame) into an enhanced image as a color corrected frame using the non-uniform 3-D LUT page 17524/Fig. 2 and page 17529); Cha similarly discloses a device of a processor to perform image frame processing where an image frame is one of a plurality of frames (par. 4-5 and 117-118); Cha explains it is known for a processor to be implemented in processing circuitry of a combination of logic circuits including a memory circuit and a circuit to perform color correction as a color correcting circuit (par. 118, 124, 147 and 158); Cha further explains the processing circuitry may be implemented as a pipeline circuit including a plurality of circuits where the pipeline circuit implements augmented reality as a visual see-through pipeline circuit (par. 34, 158 and 160); and it follows Yang may be accordingly modified with the teachings of Cha to implement its memory as a memory circuit for storing its non-uniform 3D LUT and a color correcting circuit to perform its color correction with its non-uniform 3D LUT for inclusion in a visual see-through pipeline circuit for processing its source frame as a plurality of source frames).
For claim 12, depending on claim 11, this claim is a combination of the limitations of claim 11 and claim 5. It follows claim 12 is rejected for the same reasons as to claim 11 and claim 5.
For claim 13, depending on claim 11, this claim is a combination of the limitations of claim 11 and claim 6. It follows claim 13 is rejected for the same reasons as to claim 11 and claim 6.
For claim 16, depending on claim 11, this claim is a combination of the limitations of claim 11 and claim 9. It follows claim 16 is rejected for the same reasons as to claim 11 and claim 9.
For claim 20, depending on claim 18, Yang as modified by Cha and Gvsl discloses wherein the source frame is one of a plurality of source frames of a video, wherein the transforming is capable of color correcting the video into a color corrected video in real time (Cha similarly discloses a device of a processor to perform image frame processing where an image frame is one of a plurality of frames (par. 4-5 and 117-118); Cha explains it is known for a processor to be implemented in processing circuitry of a combination of logic circuits including a memory circuit and a circuit to perform color correction as a color correcting circuit (par. 118, 124, 147 and 158); Cha further explains the processing circuitry may be implemented as a pipeline circuit including a plurality of circuits where the pipeline circuit implements augmented reality as a visual see-through pipeline circuit (par. 34, 158 and 160); and it follows Yang may be accordingly modified with the teachings of Cha to implement its memory as a memory circuit for storing its non-uniform 3D LUT and a color correcting circuit to perform its color correction with its non-uniform 3D LUT for inclusion in a visual see-through pipeline circuit for processing its source frame as a plurality of source frames; Gvsl similarly discloses a system and method for processing image frames with color correction (par. 11, 16, 111 and 113); Gvsl explains its system may process image frames of a video to transform the video to color corrected video in real time (par. 109 and 113); and it follows Yang and Cha may be accordingly modified with the teachings of Gvsl to implement its plurality of source frames in a video where its visual see-through pipeline circuit transforms the video into color corrected video in real time).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Cha further in view of Jones et al. (U.S. Patent Application Publication 2022/0174245 A1, hereinafter “Jones”).
For claim 7, depending on claim 6, Yang as modified by Cha does not disclose a plurality of LUTs each corresponding to one of a plurality of different predetermined lighting conditions.
However, these limitations are well-known int the art as disclosed in Jones.
Jones similarly discloses a system and method for processing images with color correction (par. 24-27 and 103). Jones likewise discloses the use of multiple lookup tables to perform the color correction where each lookup table is associated with a corresponding different reference (predetermined) lighting condition (par. 132). It follows Yang and Cha may be accordingly modified with the teachings of Jones to implement each of its 3D basis LUTs to correspond to one of a plurality of different predetermined lighting conditions.
A PHOSITA before the effective filing date of the claimed invention would find it obvious to modify Yang and Cha with the teachings of Jones. Jones is analogous art in dealing with a system and method for processing images with color correction (par. 24-27 and 103). Jones discloses its use of reference lighting conditions is advantageous in facilitating appropriate color correction of images for various lighting conditions (par. 132). Consequently, a PHOSITA would incorporate the teachings of Jones into Yang and Cha for facilitating appropriate color correction of images for various lighting conditions. Therefore, claim 7 is rendered obvious to a PHOSITA before the effective filing date of the claimed invention.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Cha further in view of Belur Sowmya Keshava et al. (U.S. Patent Application Publication 2024/0371131 A1, hereinafter “Keshava”).
For claim 8, depending on claim 6, Yang as modified by Cha does not disclose weights are generated based on a detected lighting condition.
However, these limitations are well-known in the art as disclosed in Keshava.
Keshava similarly discloses a system and method for processing images with color correction (par. 4 and 94). Keshava explains its system performs color correction by determining weights where the weights are generated based on detected lighting conditions of source images (par. 144-146). It follows Yang and Cha may be accordingly modified with the teachings of Keshava to generate its plurality of weights based on a detected lighting condition of its source frame.
A PHOSITA before the effective filing date of the claimed invention would find it obvious to modify Yang and Cha with the teachings of Keshava. Keshava is analogous art in dealing with a system and method for processing images with color correction (par. 24-27 and 103). Keshava discloses its use of lighting conditions is advantageous in facilitating appropriate color correction of images to improve color accuracy (par. 144-146). Consequently, a PHOSITA would incorporate the teachings of Keshava into Yang and Cha for facilitating appropriate color correction of images to improve color accuracy. Therefore, claim 8 is rendered obvious to a PHOSITA before the effective filing date of the claimed invention.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Cha further in view of Hayaishi et al. (U.S. Patent Application Publication 2007/0127074 A1, hereinafter “Hayaishi”).
For claim 10, depending on claim 1, Yang as modified by Cha does not disclose a number of color values in at least two of a red dimension, a green dimension, and a blue dimension of a LUT are not equal.
However, these limitations are well-known in the art as disclosed in Hayaishi.
Hayaishi similarly discloses a system and method for processing images with color adjustment (par. 9-10 and 53). Hayaishi explains the color adjustment is performed with a 3D LUT where a different number of color tone values of each of a red, green and blue dimension are selected in generating the 3D LUT (par. 148). It follows Yang and Cha may be accordingly modified with the teachings of Hayaishi to implement an unequal number of color correction values in at least two of the red dimension, the green dimension, and the blue dimension of its non-uniform 3D LUT.
A PHOSITA before the effective filing date of the claimed invention would find it obvious to modify Yang and Cha with the teachings of Hayaishi. Hayaishi is analogous art in dealing with a system and method for processing images with color adjustment (par. 9-10 and 53). Hayaishi discloses a different number of color values of each dimension in generating a 3D LUIT is advantageous in processing and adjusting color of images with fewer errors and lower data volume (par. 148). Consequently, a PHOSITA would incorporate the teachings of Hayaishi into Yang and Cha for processing and adjusting color of images with fewer errors and lower data volume. Therefore, claim 10 is rendered obvious to a PHOSITA before the effective filing date of the claimed invention.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Cha further in view of Gvsl further in view of Jones.
For claim 14, depending on claim 13, this claim is a combination of the limitations of claim 13 and claim 7. It follows claim 14 is rejected for the same reasons as to claim 13 and claim 7.
The rationale for combining the teachings of Jones with Yang, Cha and Gvsl is incorporated from claim 7.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Cha further in view of Gvsl further in view of Keshava.
For claim 15, depending on claim 13, this claim is a combination of the limitations of claim 13 and claim 8. It follows claim 15 is rejected for the same reasons as to claim 13 and claim 8.
The rationale for combining the teachings of Keshava with Yang, Cha and Gvsl is incorporated from claim 8.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Cha further in view of Gvsl further in view of Hayaishi.
For claim 17, depending on claim 11, this claim is a combination of the limitations of claim 11 and claim 10. It follows claim 17 is rejected for the same reasons as to claim 11 and claim 10.
The rationale for combining the teachings of Hayaishi with Yang, Cha and Gvsl is incorporated from claim 10.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES TSENG whose telephone number is (571)270-3857. The examiner can normally be reached 8-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Xiao Wu can be reached at (571) 272-7761. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHARLES TSENG/ Primary Examiner, Art Unit 2613
Prosecution Insights