DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I, claims 1-14 in the reply filed on 7/1/2026 is acknowledged. The traversal is on the ground(s) that claims 1-22 have the same subject matter, and a search and examination of both groups would not impose a serious burden on the Examiner. This is not found persuasive because Group I describes a memory device, and Group II describes an error correction device which could be used on the memory device. However, because the memory device of Group I could employ any materially different error correction device than that of Group II, a search for the invention of Group I would not necessarily encompass Group II. The requirement is still deemed proper and is therefore made FINAL. The Examiner notes that should the non-elected groups continue to be amended during prosecution to include language of the memory device that is ultimately found to be allowable, a rejoinder would be issued to rejoin withdraw the restriction requirement pertaining to those claims.
Claims 15-23 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-6 and 13-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 2-5 and 13-14 recite Tk. It is unclear what these terms mean because they haven’t been defined. Claim 6 is rejected in view of its dependency.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 7, 8, and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al (US Pat. Pub. 2022/0368351; hereinafter referred to as Jeong) in view of Zhang et al (US Pat. Pub. 2025/0104788; hereinafter referred to as Zhang).
As per claim 1: Jeong teaches a memory device comprising:
a memory core (Fig. 8, 830) grouped into a plurality of cell groups (Fig. 8, 831-838), each cell group including adjacent cell blocks disposed in a row direction and sharing sub-word line drivers with adjacent cell groups (paragraph 69); and
an error correction circuit (Fig. 8, 820) configured to, during a read operation, correct an error of main data in units of symbols (end of paragraph 77) by calculating the main data and an error correction code (Fig. 2), which are read from the memory core (paragraph 37), with a check matrix (Fig. 3), each unit of symbols including data output from one cell group (Figs. 9-10), or data output from cell blocks disposed at both ends of two adjacent cell groups based on a sub-word line driver shared between the two adjacent cell groups.
Not explicitly disclosed is a plurality of cell blocks grouped into the cell groups. However, Zhang in an analogous art teaches a cell group (paragraph 54) comprising cell blocks (Fig. 5, 210).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filling date to use the memory blocks of Zhang in the memory groups 831-838 of Jeong. This modification would have been obvious for one of ordinary skill in the art at the time of filing because a memory group may be comprised of memory blocks, as shown by Zhang.
As per claim 7:
Jeong further teaches the memory device of claim 1, further comprising: an error correction code (ECC) generation circuit (Fig. 8, 821), during a write operation, configured to generate the error correction code by calculating the main data to be written to the memory core with the check matrix (paragraph 67).
As per claim 8:
Jeong further teaches the memory device of claim 1, wherein the error correction circuit includes:
a syndrome generation circuit configured to generate a first syndrome (Fig. 16, 1621) and a second syndrome (Fig. 16, 1623) by comparing the error correction code with a calculation result (paragraph 143) obtained by calculating the main data with the check matrix (Fig. 2);
a syndrome comparison circuit (Fig. 16, 1625) configured to generate a result by calculating the first syndrome (Fig. 16, 1621) and a lower portion of the check matrix (Fig. 3), and generate a plurality of syndrome comparison signals corresponding to each of the plurality of cell blocks (Fig. 16, ERR) by comparing the result and the second syndrome (paragraph 143);
an error location detector configured to generate an error location signal indicating an error location in units of symbols based on the plurality of syndrome comparison signals (paragraph 48); and
an error corrector configured to correct an error of the main data according to the error location signal (paragraph 144).
Not explicitly disclosed is generating a plurality of sub-syndromes, and generating a plurality of syndrome comparison signals corresponding to each of the plurality of cell blocks by comparing the plurality of sub-syndromes and the second syndrome. However, the combination of Jeong and Zhang would have necessitated a sub-syndrome for each cell group of Zhang.
As per claim 10: Jeong further teaches the memory device of claim 1, wherein each of the cell groups includes: odd-numbered word lines sharing odd-numbered sub-word line drivers with a cell group adjacent to each other in a first direction of the row direction; and even-numbered word lines sharing odd-numbered sub-word line drivers with a cell group adjacent to each other in a second direction of the row direction, which is opposite to the first direction (see Fig. 8, 830).
Claim(s) 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeong in view of Zhang in view of Oh et al (US Pat. 2016/0163377; hereinafter referred to as Oh).
As per claim 11: Jeong teaches a memory device comprising:
a memory core (Fig. 8, 830) grouped into a plurality of cell groups (Fig. 8, 831-838), each cell group including adjacent cell blocks disposed in a row direction (see Fig. 8; paragraph 69); and
an error correction circuit (Fig. 8, 820), during a read operation, configured to correct an error of main data in units of symbols (end of paragraph 77) by calculating the main data and an error correction code (Fig. 2), which are read from the memory core (paragraph 37), with a check matrix (Fig. 3), each unit of symbols including data output from one cell group (Figs. 9-10), or data output from cell blocks disposed at both ends of two adjacent cell groups.
Not explicitly disclosed is a plurality of cell blocks grouped into the cell groups. However, Zhang in an analogous art teaches a cell group (paragraph 54) comprising cell blocks (Fig. 5, 210).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filling date to use the memory blocks of Zhang in the memory groups 831-838 of Jeong. This modification would have been obvious for one of ordinary skill in the art at the time of filing because a memory group may be comprised of memory blocks, as shown by Zhang.
Also not explicitly disclosed is a lower chip; and one or more upper chips stacked over the lower chip. However, Oh in an analogous art teaches a lower chip (Fig. 17, 1140); and one or more upper chips stacked over the lower chip (Fig. 17, 1150; paragraph 165).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filling date to use the memory of Jeong in the multi chip package of Oh. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it would have reduced power consumption for a plurality of memory chips (paragraph 168).
As per claim 12: Jeong further teaches the memory device of claim 11, wherein each of the plurality of cell groups is configured to share sub-word line drivers with adjacent cell groups, wherein the cell blocks disposed at both ends of two adjacent cell groups are configured to be disposed at both ends of two adjacent cell groups based on the sub-word line driver shared between the two adjacent cell groups (see Fig. 8, 830).
Allowable Subject Matter
Claims 2-6, 9, 13, and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if any applicable 112 rejections are overcome, and if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The prior art are directed to error correction methods in memory systems, particularly across sub-word lines.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVE N NGUYEN whose telephone number is (571)272-7214. The examiner can normally be reached M-F 9-5.
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/STEVE N NGUYEN/Primary Examiner, Art Unit 2111
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