DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-7 and 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over CN202111033089 to Xu et al. (For the purpose of the current Office Action, US 2024/0172508 will be used as an equivalent English translation); in view of US 2007/0296662 to Lee et al.
As per claim 1, Xu et al. teach a shift register unit, comprising:
a shift register (Fig. 5A); and
a voltage adjusting circuit (Fig. 5A, GPT1/GPT8/GPC2/GPC1), coupled to a set node (Fig. 5A, GPD2/GPD1) of the shift register, and configured to adjust a voltage of the set node in response to a signal of a first clock signal terminal (Fig. 5A, node GPD1 is adjusted based on clock signal GPCK enabling transistor GPT1),
wherein the set node comprises a pull-up node (Fig, 5A, node GPD2 controls transistor GPT4, which in turns pulls up output GPOUT).
Xu et al. do not teach wherein the voltage adjusting circuit comprises a first capacitor; a first terminal of the first capacitor is coupled to the first clock signal terminal, and a second terminal of the first capacitor is coupled to the pull-up node.
Lee et al. teach wherein the voltage adjusting circuit comprises a first capacitor; a first terminal of the first capacitor is coupled to the first clock signal terminal, and a second terminal of the first capacitor is coupled to the pull-up node (Fig. 9, see capacitors Cgd and Cgs, see also paragraph 118, “The ninth transistor T9 has an asymmetric structure. In detail, a parasitic capacitance Cgs between the gate and source electrodes of the ninth transistor T9 is different from a parasitic capacitance Cgd between the gate and drain electrodes of the ninth transistor T9. In more detail, the parasitic capacitance Cgs is greater than the parasitic capacitance Cgd”).
It would have been obvious to one of ordinary skill in the art, to modify the device of Xu, so that the voltage adjusting circuit comprises a first capacitor; a first terminal of the first capacitor is coupled to the first clock signal terminal, and a second terminal of the first capacitor is coupled to the pull-up node, such as taught by Lee, for the purpose of reducing ripples.
As per claim 3, Xu and Lee et al. teach the shift register unit according to claim 1, wherein the set node comprises a pull-down node (Fig. 5A, GPD1), the voltage adjusting circuit further comprises a second capacitor (Fig. 5A, GPC2); a first terminal of the second capacitor is coupled to the first clock signal terminal (Fig. 5A, a terminal of GPC2 is at least indirectly connected to GPCK via GPT4 -> GPC1 -> GPT2), and a second terminal of the second capacitor is coupled to the pull-down node (Fig. 5A, a second terminal of GPC2 is at least indirectly coupled to GPD1 via GPT8).
As per claim 4, Xu and Lee et al. teach the shift register unit according to claim 1, wherein the shift register comprises:
an input circuit (Fig. 5A, circuit comprising transistor GPT1), configured to provide a signal of an input signal terminal (Fig. 5A, GPI) to a pull-down node (Fig. 5A, GPD1) in response to the signal of the first clock signal terminal (Fig. 5A, GPCK);
a node control circuit (Fig. 5A, GPT2/GPT6/GPT7), configured to control a signal of a pull-up node and a signal of the pull-down node;
an output circuit (Fig. 5A, GPT4/GPT5), configured to provide a signal of a first reference signal terminal (Fig. 5A, GPvgh) to an output terminal (Fig. 5A, GPOUT) in response to the signal of the pull-up node, and provide a signal of a second clock signal terminal (Fig. 5A, GPCG) to the output terminal in response to the signal of the pull-down node (Fig. 5A, the signal of GPDI controls the gate of GPT5 when GPT8 is enabled).
As per claim 5, Xu and Lee et al. teach the shift register unit according to claim 4, wherein the input circuit comprises: a first transistor (Fig. 5A, GPTI); a control terminal of the first transistor is coupled to the first clock signal terminal (Fig. 5A, GPCK), a first terminal of the first transistor is coupled to the input signal terminal (Fig. 5A, GPI), and a second terminal of the first transistor is coupled to the pull-down node (Fig. 5A, GPDI).
As per claim 6, Xu and Lee et al. teach the shift register unit according to claim 4, wherein the node control circuit comprises a second transistor (Fig. 5A, GPT3), a third transistor (Fig. 5A, GPT2), a fourth transistor (Fig. 5A, GPT6), and a fifth transistor (Fig. 5A, GPT7);
a control terminal of the second transistor (Fig. 5A, gate of GPT3) is coupled to the first clock signal terminal (Fig. 5A, GPCK), a first terminal of the second transistor is coupled to a second reference signal terminal (Fig. 5A, GPvgl), and a second terminal of the second transistor is coupled to the pull-up node (Fig. 5A, GPD2);
a control terminal of the third transistor (Fig. 5A, gate of GPT2) is coupled to a second terminal of a first transistor (Fig. 5A, GPT1), a first terminal of the third transistor is coupled to the pull-up node (Fig. 5A, GPD2), and a second terminal of the third transistor is coupled to the first clock signal terminal (Fig. 5A, GPCK);
a control terminal of the fourth transistor (Fig. 5A, gate of GPT6) is coupled to the pull-up node (Fig. 5A, GPD2), a first terminal of the fourth transistor is coupled to the first reference signal terminal (Fig. 5A, GPvgh), and a second terminal of the fourth transistor is coupled to a first terminal of the fifth transistor (Fig. 5A, GPT7);
a control terminal of the fifth transistor (Fig. 5A, gate of GPT7) is coupled to the second clock signal terminal (Fig. 5A, GPCB), and a second terminal of the fifth transistor is coupled to the pull-down node (Fig. 5A, GPD1).
As per claim 7, Xu and Lee et al. teach the shift register unit according to claim 4, wherein the output circuit comprises a sixth transistor (Fig. 5A, GPT5) and a seventh transistor (Fig. 5A, GPT4);
a control terminal of the sixth transistor (Fig. 5A, gate of GPT5) is coupled to the pull-down node (Fig. 5A, GPD1 via GPT8), a first terminal of the sixth transistor is coupled to the output terminal (Fig. 5A, GPOUT), and a second terminal of the sixth transistor is coupled to the second clock signal terminal (Fig. 5A, GPCB);
a control terminal of the seventh transistor (Fig. 5A, gate of GPT5) is coupled to the pull-up node (Fig. 5A, GPD2), a first terminal of the seventh transistor is coupled to the first reference signal terminal (Fig. 5A, GPvgh), and a second terminal of the seventh transistor is coupled to the output terminal (Fig. 5A, GPOUT).
As per claim 10, Xu and Leet al. teach a gate driving circuit, comprising: a plurality of cascaded shift register units each according to claim 1; wherein:
an input signal terminal of a shift register unit of a first stage is configured to be coupled to a frame start signal terminal (paragraph 118, “the input terminal GNI is configured to be connected to a trigger signal line STV to receive a trigger signal as an input signal”); and
in every two adjacent shift register units, an input signal terminal of a shift register unit of a next stage is configured to be coupled to an output terminal of a shift register unit of a previous stage (paragraph 118, “A second electrode of a first transistor GNT1 in each of the other stages of first shift register units 221 is electrically connected to an output terminal of a previous stage of first shift register unit 221 to receive an output signal output from an output terminal EOUT of the previous stage of first shift register unit 221 as an input signal”).
As per claim 11, Xu and Lee et al. teach a display device (Fig. 12, paragraph 250), comprising the gate driving circuit according to claim 10.
As per claim 12, Xu and Lee et al. teach a driving method of the shift register according to claim 1, comprising outputting, by the shift register, a driving signal (Fig. 5A, signal output by GPOUT terminal);
adjusting, by the voltage adjusting circuit (Fig. 5A, GPT1/GPT8/GPC2/GPC1), a voltage of a set node (Fig. 5A, GPD2/GPD1) of the shift register in response to a signal of a first clock signal terminal (Fig. 5A, node GPD1 is adjusted based on clock signal GPCK enabling transistor GPT1).
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over CN202111033089 to Xu et al. (For the purpose of the current Office Action, US 2024/0172508 will be used as an equivalent English translation); in view of US 2007/0296662 to Lee et al.; in view of CN202111435505 to Feng et al. (For the purpose of the current Office Action, US 2024/0185793 will be used as an equivalent English translation).
As per claim 8, Xu and Lee et al. teach the shift register unit according to claim 4.
Xu and Lee et al. do not teach wherein the output circuit further comprises a third capacitor; a first terminal of the third capacitor is coupled to the first reference signal terminal, and a second terminal of the third capacitor is coupled to the pull-up node.
Feng et al. teaches wherein the output circuit further comprises a third capacitor; a first terminal of the third capacitor is coupled to the first reference signal terminal, and a second terminal of the third capacitor is coupled to the pull-up node (Fig. 12A, paragraph 81, “the capacitor structure C1 in the embodiment of the present disclosure includes: at least two capacitor units CU connected to each other in parallel, a first voltage writing electrode p1 of each capacitor unit CU is coupled to the gate electrode g of the output transistor Mt, and a second voltage writing electrode p2 of each capacitor unit CU is coupled to the signal output line OUT configured for the driving output circuit”, in other words, the claimed limitation seems to read on a capacitor parallel to GPC1 in Fig. 5A of Xu, such as suggested by Feng).
It would have been obvious to one of ordinary skill in the art, to modify the device of Xu and Lee et al., so that the output circuit further comprises a third capacitor; a first terminal of the third capacitor is coupled to the first reference signal terminal, and a second terminal of the third capacitor is coupled to the pull-up node, such as taught by Feng et al., for the purpose of improving manufacturing yield and reliability.
As per claim 9, Xu and Lee et al. teach the shift register unit according to claim 4.
Xu and Lee et al. do not teach wherein the output circuit further comprises a fourth capacitor;5a first terminal of the fourth capacitor is coupled to the output terminal, and a second terminal of the fourth capacitor is coupled to the pull-down node.
Feng et al. teaches wherein the output circuit further comprises a fourth capacitor; a first terminal of the fourth capacitor is coupled to the output terminal, and a second terminal of the fourth capacitor is coupled to the pull-down node (Fig. 12A, paragraph 81, “the capacitor structure C1 in the embodiment of the present disclosure includes: at least two capacitor units CU connected to each other in parallel, a first voltage writing electrode p1 of each capacitor unit CU is coupled to the gate electrode g of the output transistor Mt, and a second voltage writing electrode p2 of each capacitor unit CU is coupled to the signal output line OUT configured for the driving output circuit”, in other words, the claimed limitation seems to read on a capacitor parallel to GPC2 in Fig. 5A of Xu, such as suggested by Feng).
It would have been obvious to one of ordinary skill in the art, to modify the device of Xu and Lee et al., so that the output circuit further comprises a fourth capacitor; a first terminal of the fourth capacitor is coupled to the output terminal, and a second terminal of the fourth capacitor is coupled to the pull-down node, such as taught by Feng et al., for the purpose of improving manufacturing yield and reliability.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JOSE R SOTO LOPEZ/Primary Examiner, Art Unit 2622