DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim status
Claims 1-20 are pending; claim 1 is independent.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2023/0320154), and further in view of Wang (WO 2022246610), provided by applicant’s IDS and using (US 2024/0221590) as English translation.
Regarding claim 1, Kim teaches a pixel circuit (fig. 3 and fig. 10), comprising N sub-pixels (fig. 10), N first initial voltage terminals (figs 3, 10 and VINT) and N second initial voltage terminals (figs 3, 10 and Vbias), wherein N is an integer greater than 1 and n is a positive integer less than or equal to N;
an nth sub-pixel comprises an nth driving circuit (figs 3, 10, a first thin film transistor T1 (a driving transistor)), an nth light emitting element (figs 3, 10 and an organic light-emitting diode (OLED)), an nth one of first initialization circuits (figs 3, 10 and the fourth thin film transistor T4 (a driving initialization transistor)) and an organic light-emitting diode (OLED)), an nth one of second initialization circuits (figs 3, 10 and the eighth thin film transistor T8) and an nth one of first light emitting control circuits (figs 3, 10 and the sixth thin film transistor T6 (a second light-emitting control transistor));
a control terminal of the nth driving circuit is electrically connected to an nth one of first nodes (figs 3, 10, a gate terminal of transistor T1 connected to a second node N2) a first terminal of the nth driving circuit is electrically connected to an nth one of second nodes (figs 3, 10, a first terminal of transistor T1 connected to a first node N1), a second terminal of the nth driving circuit is electrically connected to an nth one of third nodes (figs 3, 10, a second terminal of transistor T1 connected to a third node N3), and the nth driving circuit is configured to generate a driving current for driving the nth light emitting element under the control of a potential of the nth one of the first nodes (figs 3, 10 and Para 0081);
the nth one of the first light emitting control circuits (figs 3, 10 and transistor T6) is electrically connected to each of a light emitting control terminal, the nth one of the third nodes and a first electrode of the nth light emitting element, and is configured to control the nth one of the third nodes to be electrically connected to the first electrode of the nth light emitting element under the control of a light emitting control signal provided by the light emitting control terminal, and a second electrode of the nth light emitting element is electrically connected to a second voltage terminal (figs 3, 10, the sixth thin film transistor T6 (a second light-emitting control transistor) and Para 0085);
the nth one of the first initialization circuits (figs 3, 10 and transistor T4) is electrically connected to each of a first reset control terminal, an nth one of the first initial voltage terminals and the nth one of the third nodes, and is configured to write an nth one of first initial voltages provided by the nth one of the first initial voltage terminals into the nth one of the third nodes under the control of a first reset control signal provided by the first reset control terminal (figs 3, 10 and the fourth thin film transistor T4 (a driving initialization transistor) and 0084, wherein the driving initialization voltage VINT transmitted to the third node N3 via the third thin film transistor T3 );
the nth one of the second initialization circuits (figs 3, 10 and transistor T8)is electrically connected to each of a second reset control terminal, an nth one of the second initial voltage terminals and the nth one of the second nodes, and is configured to write an nth one of second initial voltages provided by the nth one of the second initial voltage terminals into the nth one of the second nodes under the control of a second reset control signal provided by the second reset control terminal (figs 3, 10 and the eighth thin film transistor T8 and Para 0087);
Kim does not expressly disclose first initial voltages provided by at least two of the first initial voltage terminals are different from each other, and/or the second initial voltages provided by at least two of the second initial voltage terminals are different from each other.
However, Wang “first initial voltages provided by at least two of the first initial voltage terminals are different from each other”, figs 3, 4, 8, Paras 0100 and 0107.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified a pixel circuit of Kim with the teaching of Wang to include a three subpixels are electrically connected to different initialization voltage lines, corresponding initialization voltages may be input into the subpixels via respective initialization voltage lines, as a result, the first, second and third subpixels have consistent charging time, as a known technique to yield a predictable result.
Regarding claim 2, Kim in view of Wang teaches the pixel circuit according to claim 1, wherein the pixel circuit comprises three sub-pixels, wherein a first one of the sub-pixels is a red sub-pixel, a second one of the sub-pixels is a green sub-pixel, and a third one of the sub-pixels is a blue sub-pixel (fig. 2 and Para 0074, Kim);
Kim in view of Wang teaches a first one of the first initial voltages is different from a third one of the first initial voltages, and a second one of the first initial voltages is different from the third one of the first initial voltages (figs 3, 4, 8, Paras 0100 and 0107, Wang).
Regarding claim 3, Kim in view of Wang teaches the pixel circuit according to claim 2, wherein a driving transistor comprised in each driving circuit is a p-type transistor, the first one of the first initial voltages is greater than the third one of the first initial voltages, and the second one of the first initial voltages is greater than the third one of the first initial voltages;
or
a driving transistor comprised in each driving circuit is an n-type transistor, the first one of the first initial voltages is less than the third one of the first initial voltages, and the second one of the first initial voltages is less than the third one of the first initial voltages (figs 3, 4, 8, Paras 0100 and 0107, wherein the initialization voltage input into the green subpixel G is set to be higher than that input into the red subpixel R, and the initialization voltage input into the red subpixel R is set to be higher than that input into the blue subpixel B, Wang).
Regarding claim 4, Kim in view of Wang teaches the pixel circuit according to claim 3, wherein the first one of the first initial voltages is equal to the second one of the first initial voltages (fig. 10 and Para 0169, wherein one electrode of the OLED of the second sub-pixel Pr that emits light of a red color and one electrode of the OLED of the third sub-pixel Pg that emits light of a green color may be electrically connected to the second initialization voltage line VAIL2 and may receive a second initialization voltage AINT(R/G), Kim).
Regarding claim 5, Kim in view of Wang teaches the pixel circuit according to claim 3, wherein the driving transistor is the p-type transistor, and the first one of the first initial voltages is less than the second one of the first initial voltages;
or
the driving transistor is the n-type transistor, and the first one of the first initial voltages is greater than the second one of the first initial voltages (figs 3, 4, 8, Paras 0100 and 0107, wherein the initialization voltage input into the green subpixel G is set to be higher than that input into the red subpixel R, Wang).
Regarding claim 6, Kim in view of Wang teaches the pixel circuit according to claim 1, wherein the pixel circuit comprises three sub-pixels, a first one of the sub-pixels is a red sub-pixel, a second one of the sub-pixels is a green sub-pixel, and a third one of the sub-pixels is a blue sub-pixel (fig. 2 and Para 0074, Kim);
a first one of the second initial voltages is different from a third one of the second initial voltages, and a second one of the second initial voltages is different from the third one of the second initial voltages (figs 3, 4, 8, Paras 0100 and 0107, Wang).
Regarding claim 7, Kim in view of Wang teaches the pixel circuit according to claim 6, wherein a driving transistor comprised in each driving circuit is a p-type transistor, the first one of the second initial voltages is greater than the third one of the second initial voltages, and the second one of the second initial voltages is greater than the third one of the second initial voltages; or
a driving transistor comprised in each driving circuit is an n-type transistor, the first one of the second initial voltages is less than the third one of the second initial voltages, and the second one of the second initial voltages is less than the third one of the second initial voltages (figs 3, 4, 8, Para and 0107, wherein the initialization voltage input into the green subpixel G is set to be higher than that input into the red subpixel R, and the initialization voltage input into the red subpixel R is set to be higher than that input into the blue subpixel B, Wang).
Regarding claim 8, Kim in view of Wang teaches the pixel circuit according to claim 7, wherein the first one of the second initial voltages is equal to the second one of the second initial voltages (fig. 10 and Para 0169, wherein one electrode of the OLED of the second sub-pixel Pr that emits light of a red color and one electrode of the OLED of the third sub-pixel Pg that emits light of a green color may be electrically connected to the second initialization voltage line VAIL2 and may receive a second initialization voltage AINT(R/G), Kim).
Regarding claim 9, Kim in view of Wang teaches the pixel circuit according to claim 7, wherein the driving transistor is the p-type transistor, and the first one of the second initial voltages is less than the second one of the second initial voltages;
or
the driving transistor is the n-type transistor, and the first one of the second initial voltages is greater than the second one of the second initial voltages (figs 3, 4, 8, Para and 0107, wherein the initialization voltage input into the green subpixel G is set to be higher than that input into the red subpixel R, and the initialization voltage input into the red subpixel R is set to be higher than that input into the blue subpixel B, Wang).
Regarding claim 10, Kim in view of Wang teaches the pixel circuit according to claim 1, wherein the pixel circuit further comprises N third initial voltage terminals (fig. 3, AINT, Kim), and the nth sub-pixel further comprises an nth one of third initialization circuits (fig. 3, a seventh thin film transistor T7 (an initialization transistor, Kim);
the nth one of the third initialization circuits is electrically connected to each of a third reset control terminal, an nth one of the third initial voltage terminals and the first electrode of the nth light emitting element, and is configured to write an nth one of third initial voltages provided by the nth one of the third initial voltage terminals into the first electrode of the nth light emitting element under the control of a third reset control signal provided by the third reset control terminal (fig. 3, a seventh thin film transistor T7 (an initialization transistor and Para 0084, Kim).
Regarding claim 11, Kim in view of Wang teaches the e pixel circuit according to claim 10, wherein the respective third initial voltages provided by the N third initial voltage terminals are the same (figs 3, 10 and Para 0169, wherein one electrode of the OLED of the second sub-pixel Pr that emits light of a red color and one electrode of the OLED of the third sub-pixel Pg that emits light of a green color may be electrically connected to the second initialization voltage line VAIL2 and may receive a second initialization voltage AINT(R/G, Kim).
Regarding claim 12, Kim in view of Wang teaches the pixel circuit according to claim 1, wherein the nth sub-pixel further comprises an nth energy storage circuit (figs 3, 10, a capacitor Cst), an nth compensation control circuit (figs 3, 10, a third thin film transistor T3 (a compensation transistor)) and an nth data writing circuit (figs 3, 10, a second thin film transistor T2 (a switching transistor));
a first terminal of the nth energy storage circuit is electrically connected to the nth one of the first nodes, a second terminal of the nᵗʰ energy storage circuit is electrically connected to a direct current voltage terminal, and the nth energy storage circuit is configured to store electrical energy (figs 3, 10, a capacitor Cst and Para 0089, Kim);
the nth compensation control circuit is electrically connected to each of a compensation control terminal, the nth one of the first nodes and the nth one of the third nodes, and is configured to control the nth one of the first nodes to be electrically connected to the nth one of the third nodes under the control of a compensation control signal provided by the compensation control terminal (figs 3, 10, a third thin film transistor T3 (a compensation transistor) and Para 0083, Kim); and
the nth data writing circuit is electrically connected to each of a writing control terminal, an nth data line and the nth one of the second nodes, and is configured to write an nth data voltage provided by the nᵗʰ data line into the nᵗʰ one of the second nodes under the control of a writing control signal provided by the writing control terminal (figs 3, 10, a second thin film transistor T2 (a switching transistor) and Para 0082, Kim).
Regarding claim 13, Kim in view of Wang teaches the pixel circuit according to claim 1, wherein the nth sub-pixel further comprises an nth one of second light emitting control circuits (figs 3, 10, a fifth thin film transistor T5 (a first light-emitting control transistor));
the nth one of the second light emitting control circuits is electrically connected to each of the light emitting control terminal, a first voltage terminal and the nth one of the second nodes, and is configured to control the first voltage terminal to be electrically connected to the nth one of the second nodes under the control of the light emitting control signal (figs 3, 10, a fifth thin film transistor T5 (a first light-emitting control transistor) and Para 0085, Kim).
Regarding claim 14, Kim in view of Wang teaches the driving method, applied to the pixel circuit according to claim 1, wherein the driving method comprises:
generating, by the nth driving circuit, the driving current for driving the nth light emitting element under the control of a potential of the nth one of the first nodes (fig. 3, a first transistor T1 and Para 0081, Kim);
controlling, by the nth one of the first light emitting control circuits, the nth one of the third nodes to be electrically connected to the first electrode of the nth light emitting element under the control of the light emitting control signal (fig. 3, a fifth transistor T6 and Para 0085, Kim);
writing, by the nth one of the first initialization circuits, the nth one of the first initial voltages provided by the nth one of the first initial voltage terminals into the nth one of the third nodes under the control of the first reset control signal (figs 3, 10 and the fourth thin film transistor T4 (a driving initialization transistor) and 0084, wherein the driving initialization voltage VINT transmitted to the third node N3 via the third thin film transistor T3, Kim);
writing, by the nth one of the second initialization circuits, the nth one of the second initial voltages provided by the nth one of the second initial voltage terminals into the nth one of the second nodes under the control of the second reset control signal (figs 3, 10 and the eighth thin film transistor T8 and Para 0087, Kim);
wherein N is an integer greater than 1, and n is a positive integer less than or equal to N (figs 10-12 Kim);
Kim does not expressly disclose the first initial voltages provided by the at least two of the first initial voltage terminals are different from each other, and/or the second initial voltages provided by the at least two of the second initial voltage terminals are different from each other.
However, Wang “the first initial voltages provided by the at least two of the first initial voltage terminals are different from each other”, figs 3, 4, 8, Paras 0100 and 0107.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the driving method of Kim with the teaching of Wang to include a three subpixels are electrically connected to different initialization voltage lines, corresponding initialization voltages may be input into the subpixels via respective initialization voltage lines, as a result, the first, second and third subpixels have consistent charging time, as a known technique to yield a predictable result
Regarding claim 15, Kim in view of Wang teaches a display device comprising the pixel circuit according to claim 1 (fig. 1 and Paras 0065-0066, Kim).
Regarding claim 16, Kim in view of Wang teaches the display device according to claim 15, wherein the pixel circuit comprises three sub-pixels, wherein a first one of the sub-pixels is a red sub-pixel, a second one of the sub-pixels is a green sub-pixel, and a third one of the sub-pixels is a blue sub-pixel (fig. 2 and Para 0074, Kim);
a first one of the first initial voltages is different from a third one of the first initial voltages, and a second one of the first initial voltages is different from the third one of the first initial voltages (figs 3, 4, 8, Paras 0100 and 0107, Wang).
Regarding claim 17, Kim in view of Wang teaches the display device according to claim 16, wherein a driving transistor comprised in each driving circuit is a p-type transistor, the first one of the first initial voltages is greater than the third one of the first initial voltages, and the second one of the first initial voltages is greater than the third one of the first initial voltages;
or
a driving transistor comprised in each driving circuit is an n-type transistor, the first one of the first initial voltages is less than the third one of the first initial voltages, and the second one of the first initial voltages is less than the third one of the first initial voltages (figs 3, 4, 8, Paras 0100 and 0107, wherein the initialization voltage input into the green subpixel G is set to be higher than that input into the red subpixel R, and the initialization voltage input into the red subpixel R is set to be higher than that input into the blue subpixel B, Wang).
Regarding claim 18, Kim in view of Wang teaches the display device according to claim 17, wherein the first one of the first initial voltages is equal to the second one of the first initial voltages (fig. 10 and Para 0169, wherein one electrode of the OLED of the second sub-pixel Pr that emits light of a red color and one electrode of the OLED of the third sub-pixel Pg that emits light of a green color may be electrically connected to the second initialization voltage line VAIL2 and may receive a second initialization voltage AINT(R/G), Kim).
Regarding claim 19, Kim in view of Wang teaches the display device according to claim 17, wherein the driving transistor is the p-type transistor, and the first one of the first initial voltages is less than the second one of the first initial voltages;
or
the driving transistor is the n-type transistor, and the first one of the first initial voltages is greater than the second one of the first initial voltages(figs 3, 4, 8, Paras 0100 and 0107, wherein the initialization voltage input into the green subpixel G is set to be higher than that input into the red subpixel R, Wang).
Regarding claim 20, Kim in view of Wang teaches the display device according to claim 15, wherein the pixel circuit comprises three sub-pixels, a first one of the sub-pixels is a red sub-pixel, a second one of the sub-pixels is a green sub-pixel, and a third one of the sub-pixels is a blue sub-pixel (fig. 2 and Para 0074, Kim);
a first one of the second initial voltages is different from a third one of the second initial voltages, and a second one of the second initial voltages is different from the third one of the second initial voltages (figs 3, 4, 8, Paras 0100 and 0107, Wang).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
LI (US 2021/0125562), relates to the field of display technologies, and particularly to a pixel circuit, a method for driving the same, a display panel and a display device.
Kim (US 2023/0206858), relates to a display device, and more particularly, to a display device which reduces color variation.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAIFELDIN E ELNAFIA whose telephone number is (571)270-5852. The examiner can normally be reached 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WILLIAM BODDIE can be reached at (571) 272-0666. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/S.E.E/Examiner, Art Unit 2625 9/19/2026
/WILLIAM BODDIE/Supervisory Patent Examiner, Art Unit 2625
Prosecution Insights