Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received on 08 January 2025 for application number 18/992,478. The Office hereby acknowledges receipt of the following and placed of record in file: Oath/Declaration, Abstract, Specification, Drawings, and Claims.
Claims 2 – 13 are currently amended.
Claims 14 – 20 are new.
Claims 1 – 20 are presented for examination.
Priority
As required by M.P.E.P. 201.14(c), acknowledgement is made of applicant’s claim for priority based on the application filed on 08 July 2022 (GB2210082.0).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08 January 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The applicant’s drawings submitted are acceptable for examination purposes.
Specification
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The examiner believes that the title of the invention is imprecise. A descriptive title indicative of the invention will help in proper indexing, classifying, searching, etc. See MPEP 606.01. However, the title of the invention should be limited to 500 characters.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 5 – 7, 18, and 20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 5 recites “the respective bank”. However, a respective bank is not previously cited in the claim language. There is a lack of antecedent basis. Claims 6, 18, and 20 recite similar language and are rejected similarly.
Claim 7 recites in the last few limitations “determine whether the data has been correctly overwritten; upon determining that the data has not been correctly overwritten, re-overwrite the data at the first address; and/or upon determining that the data has been correctly overwritten, overwrite data at a second address.” It is unclear as to the exact meaning of “correctly” overwritten. The metes and bounds are not clearly defined to determine what constitutes correct or incorrect data overwrites.
Claim 7 recites in the second and third limitation “overwrite data at a first address; read data from the first address…” It is unclear how data is read if it is overwritten, or if the overwritten data is the data that is read or the original data is read.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Fujiki et al. [hereafter as Fujiki], US Pub. No. 2014/0189213 A1 in view of Moore et al. [hereafter as Moore], US Pub. No. 2004/0098416 A1 and further in view of Haukness [hereafter as Haukness], US Pub. No. 2011/0060868 A1.
As per claim 1, Fujiki discloses a data system comprising:
a memory comprising a plurality of banks [“a plurality of storage device banks”] [para. 0011];
a processor configured to write data to and/or read data from one of the plurality of banks at a time [“For example, a read access or a write access to the flash memory”] [para. 0018] [“the CPU 10 to actually perform data reading and data writing for the banks 0 and 1 by designating an access address”] [para. 0026] [“A time is required for a data erasure, and accordingly, as there are more storage device banks of which data can be simultaneously erased,”] [para. 0012]; and
an erasure module configured to perform an erasure operation on two or more of the plurality of banks concurrently, wherein on one of the two or more banks is independent of another of the two or more banks [“As a method for shortening the data erasure time, there are a method of simultaneously erasing data of a plurality of storage device banks”] [para. 0003] [“A time is required for a data erasure, and accordingly, as there are more storage device banks of which data can be simultaneously erased,”] [para. 0012].
However, Fujiki does not explicitly disclose a data erasure system:
erasure module to perform erasure operation by overwriting data concurrently, wherein overwriting data is overwriting data.
Moore teaches a data erasure system [“FIG. 2 is a flow chart of a method implemented by the data storage system 10 and memory array controller 20 of FIG. 1 in response to a delete command.”] [para. 0018]:
to perform erasure operation by overwriting data concurrently, wherein overwriting data is overwriting data [“the controller 20 can simultaneously over-write memory cells in multiple layers that share a given row and column address”] [para. 0025].
Fujiki and Moore are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Fujiki with Moore in order to modify Fujiki for “a data erasure system: to perform erasure operation by overwriting data concurrently, wherein overwriting data is overwriting data” as taught by Moore. One of ordinary skill in the art would be motivated to combine Fujiki with Moore before the effective filing date of the claimed invention to improve a system by providing for the ability where a “controller can over-write a complete page, block or other set of memory cells simultaneously to increase the speed of the over-write operation.” [Moore, para. 0025].
However, Fujiki and Moore do not explicitly disclose erasure module.
Haukness teaches erasure module [“In FIG. 3A, each of the sharable program/erase controllers 306 integrates the program control and erase control into a single shareable module.”] [para. 0053].
Fujiki, Moore, and Haukness are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Fujiki and Moore with Haukness in order to modify Fujiki and Moore for “erasure module” as taught by Haukness. One of ordinary skill in the art would be motivated to combine Fujiki and Moore with Haukness before the effective filing date of the claimed invention to improve a system by providing for “a multi-bank memory architecture that facilitates independently controlling different banks within a memory to improve memory utilization.” [Haukness, para. 0001].
As per claim 4, Fujiki in view of Moore and further in view of Haukness discloses the data erasure system according to any preceding claim 1, Haukness teaches further comprising, for each of the plurality of banks, a switching circuit configured to electrically couple one of the processor or the erasure module to a respective bank [“one or more memory banks, wherein each memory bank includes non-volatile memory cells; a set of sharable controllers that control memory operations for the one or more memory banks; a switching circuit adapted to couple the set of sharable controllers to the one or more memory banks;”] [para. 0055] [Fig. 7C].
Claims 2, 3, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Fujiki et al. [hereafter as Fujiki], US Pub. No. 2014/0189213 A1 in view of Moore et al. [hereafter as Moore], US Pub. No. 2004/0098416 A1 and further in view of Haukness [hereafter as Haukness], US Pub. No. 2011/0060868 A1 as applied to claim 1 above, and further in view of Chin et al. [hereafter as Chin], US Pub. No. 2015/0081986 A1.
As per claim 2, Fujiki in view of Moore and further in view of Haukness discloses the data erasure system according to claim 1, Moore teaches wherein the erasure is configured to overwrite data [“FIG. 2 is a flow chart of a method implemented by the data storage system 10 and memory array controller 20 of FIG. 1 in response to a delete command.”] [para. 0018] [“the controller 20 can simultaneously over-write memory cells in multiple layers that share a given row and column address”] [para. 0025].
Haukness teaches erasure module [“In FIG. 3A, each of the sharable program/erase controllers 306 integrates the program control and erase control into a single shareable module.”] [para. 0053].
However, Fujiki, Moore, and Haukness do not explicitly disclose further comprising a plurality of dedicated buses, each dedicated bus corresponding to a respective one of the plurality of banks, and data on each of the plurality of banks via the corresponding dedicated bus.
Chin teaches further comprising a plurality of dedicated buses, each dedicated bus corresponding to a respective one of the plurality of banks, and data on each of the plurality of banks via the corresponding dedicated bus [“Memory 206 and transactional memory 212 may be physically configured in a variety of ways without departing from the scope of the invention. For example, memory 206 and transactional memory 210 may reside on one or more memory banks connected to the processing entities using shared or dedicated busses in computing device 200.”] [para. 0049].
Fujiki, Moore, Haukness, and Chin are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Fujiki, Moore, and Haukness with Chin in order to modify Fujiki, Moore, and Haukness “further comprising a plurality of dedicated buses, each dedicated bus corresponding to a respective one of the plurality of banks, and data on each of the plurality of banks via the corresponding dedicated bus” as taught by Chin. One of ordinary skill in the art would be motivated to combine Fujiki, Moore, and Haukness with Chin before the effective filing date of the claimed invention to improve a system by providing “techniques for providing reliable and efficient access to non-transactional resources, using transactional memory.” [Chin, para. 0005].
As per claim 3, Fujiki in view of Moore and further in view of Haukness discloses the data erasure system according to claim 1, however Fujiki, Moore, and Haukness do not explicitly disclose further comprising a shared bus, wherein the processor is configured to write data to and/or read data from one of the plurality of banks at a time via the shared bus.
Chin teaches further comprising a shared bus, wherein the processor is configured to write data to and/or read data from one of the plurality of banks at a time via the shared bus [“Memory 206 and transactional memory 212 may be physically configured in a variety of ways without departing from the scope of the invention. For example, memory 206 and transactional memory 210 may reside on one or more memory banks connected to the processing entities using shared or dedicated busses in computing device 200.”] [para. 0049] [“reading and writing to transactional memory 212, and the like.”] [para. 0052].
Fujiki, Moore, Haukness, and Chin are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Fujiki, Moore, and Haukness with Chin in order to modify Fujiki, Moore, and Haukness “further comprising a shared bus, wherein the processor is configured to write data to and/or read data from one of the plurality of banks at a time via the shared bus” as taught by Chin. One of ordinary skill in the art would be motivated to combine Fujiki, Moore, and Haukness with Chin before the effective filing date of the claimed invention to improve a system by providing “techniques for providing reliable and efficient access to non-transactional resources, using transactional memory.” [Chin, para. 0005].
Claim 19 is rejected with like reasoning.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Fujiki et al. [hereafter as Fujiki], US Pub. No. 2014/0189213 A1 in view of Moore et al. [hereafter as Moore], US Pub. No. 2004/0098416 A1 and further in view of Haukness [hereafter as Haukness], US Pub. No. 2011/0060868 A1 as applied to claim 1 above, and further in view of Ki et al. [hereafter as Ki], US Pub. No. 2021/0181983 A1.
As per claim 8, Fujiki in view of Moore and further in view of Haukness discloses the data erasure system according to claim 1, however Fujiki, Moore, and Haukness do not explicitly disclose wherein the erasure module comprises an application-specific integrated circuit or a field-programmable gate array.
Ki teaches wherein the erasure module comprises an application-specific integrated circuit or a field-programmable gate array [“Erasure Coding module 335 may be implemented using a general purpose processor executing appropriate instructions, or using an FPGA, an ASIC, a GPU, or any other desired implementation.”] [para. 0049].
Fujiki, Moore, Haukness, and Ki are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Fujiki, Moore, and Haukness with Ki in order to modify Fujiki, Moore, and Haukness “wherein the erasure module comprises an application-specific integrated circuit or a field-programmable gate array” as taught by Ki. One of ordinary skill in the art would be motivated to combine Fujiki, Moore, and Haukness with Ki before the effective filing date of the claimed invention to improve a system by providing for “enhanced SSD reliability”. [Ki, Title].
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Fujiki et al. [hereafter as Fujiki], US Pub. No. 2014/0189213 A1 in view of Moore et al. [hereafter as Moore], US Pub. No. 2004/0098416 A1 and further in view of Haukness [hereafter as Haukness], US Pub. No. 2011/0060868 A1 as applied to claim 1 above, and further in view of Yagi [hereafter as Yagi], US Pub. No. 2005/0257017 A1.
As per claim 9, Fujiki in view of Moore and further in view of Haukness discloses the data erasure system according to claim 1, however Fujiki, Moore, Haukness do not explicitly disclose wherein the erasure module is configured to write an overwrite pattern to each of the plurality of banks during the erasure operation.
Yagi teaches wherein the erasure module is configured to write an overwrite pattern to each of the plurality of banks during the erasure operation [“Methods, apparatus, software and systems for securely erasing data from a memory card. A number of hidden spare blocks of memory in an inaccessible region of each memory bank is determined. A block of memory is repeatedly overwritten with a data pattern in each memory bank up to the number of hidden spare blocks in one embodiment. A block of memory is repeatedly erased in each memory bank up to the number of hidden spare blocks in another embodiment. The blocks of memory in the accessible region of each memory bank are erased or overwritten with the data pattern.”] [Abstract].
Fujiki, Moore, Haukness, and Yagi are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Fujiki, Moore, and Haukness with Yagi in order to modify Fujiki, Moore, and Haukness “wherein the erasure module is configured to write an overwrite pattern to each of the plurality of banks during the erasure operation” as taught by Yagi. One of ordinary skill in the art would be motivated to combine Fujiki, Moore, and Haukness with Yagi before the effective filing date of the claimed invention to improve a system by providing for the ability to “securely erase data within a memory card” where how data is erased is “an important issue with respect to data security.” [Yagi, paras. 0003 – 0006].
Claims 10, 12, 14, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Fujiki et al. [hereafter as Fujiki], US Pub. No. 2014/0189213 A1 in view of Moore et al. [hereafter as Moore], US Pub. No. 2004/0098416 A1 and further in view of Haukness [hereafter as Haukness], US Pub. No. 2011/0060868 A1 as applied to claim 1 above, and further in view of Milton [hereafter as Milton], US Pub. No. 2016/0202749 A1.
As per claim 10, Fujiki in view of Moore and further in view of Haukness discloses the data erasure system according to claim 1, Haukness teaches the erasure module during the erasure operation [“erase control into a single shareable module. … performing an erase operation”] [para. 0053].
However Fujiki, Moore, and Haukness do not explicitly disclose further comprising:
a backup power source configured to output a first voltage;
a step-up converter configured to receive the first voltage from the backup power source and to output a second voltage higher than the first voltage; and
a capacitor bank comprising one capacitor or a plurality of capacitors connected in parallel,
the capacitor bank configured to be charged by the output of the step-up converter,
and wherein the capacitor bank is configured to supply power to the erasure module during the erasure operation.
Milton teaches a backup power source configured to output a first voltage [“The memory system 10 also includes a secondary power supply or a backup power supply such as a power module 80.”] [para. 0011] [“a backup operation based on the voltage of the power module 80.”] [para. 0024];
a step-up converter configured to receive the first voltage from the backup power source and to output a second voltage higher than the first voltage [“A step-up voltage circuit 82, for example, may be used to step-up a voltage received from a host through the host interface/connector 50 to a higher voltage than received to charge a capacitor array 86.”] [para. 0015]; and
a capacitor bank comprising one capacitor or a plurality of capacitors connected in parallel [“For an embodiment, a capacitor bank or array 86 includes one or more capacitors coupled together in series and/or in parallel”] [para. 0011], the capacitor bank configured to be charged by the output of the step-up converter [“step-up a voltage received from a host through the host interface/connector 50 to a higher voltage than received to charge a capacitor array 86.”] [para. 0015], and wherein the capacitor bank is configured to supply power during the operation [“The memory system 10 also includes a secondary power supply or a backup power supply such as a power module 80... the secondary power supply may include a battery. For example, the secondary power supply may include a battery and one or more capacitors.”] [para. 0011] [“a backup operation based on the voltage of the power module 80.”] [para. 0024].
Fujiki, Moore, Haukness, and Milton are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Fujiki, Moore, and Haukness with Milton in order to modify Fujiki, Moore, and Haukness for “a backup power source configured to output a first voltage;
a step-up converter configured to receive the first voltage from the backup power source and to output a second voltage higher than the first voltage; and
a capacitor bank comprising one capacitor or a plurality of capacitors connected in parallel,
the capacitor bank configured to be charged by the output of the step-up converter,
and wherein the capacitor bank is configured to supply power to the erasure module during the erasure operation” as taught by Milton. One of ordinary skill in the art would be motivated to combine Fujiki, Moore, and Haukness with Milton before the effective filing date of the claimed invention to improve a system by providing for the ability “to determine an energy threshold for a power module based on a previous backup operation providing the benefit of reducing the amount of time a power module needs to charge before it is ready for a backup operation.” [Milton, para. 0010].
Claim 12 is rejected with like reasoning.
Claim 14 is rejected with like reasoning as claim 1 above.
Claim 17 is rejected with like reasoning as claim 4 above.
Claims 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Fujiki et al. [hereafter as Fujiki], US Pub. No. 2014/0189213 A1 in view of Moore et al. [hereafter as Moore], US Pub. No. 2004/0098416 A1 and further in view of Haukness [hereafter as Haukness], US Pub. No. 2011/0060868 A1 and further in view of Milton [hereafter as Milton], US Pub. No. 2016/0202749 A1 as applied to claim 14 above, and further in view of Chin et al. [hereafter as Chin], US Pub. No. 2015/0081986 A1.
Claim 15 is rejected with like reasoning as claim 2 above.
Claim 16 is rejected with like reasoning as claim 3 above.
Conclusion
STATUS OF CLAIMS IN THE APPLICATION
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1 – 20 have received a first action on the merits and are subject of a first action non-final. Claims 5 – 7, 18, and 20 are rejected under a 112 rejection. Claim 1 – 4, 8 – 10, 12, 14 – 17, and 19 are rejected under a 103 rejection.
Allowable Subject Matter
Claims 5 – 7, 11, 13, and 18 are objected to as being dependent upon a rejected based claim, but are considered as containing allowable subject matter. These claims would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) set forth in this Office action and to include all of the limitations of the base claim and any intervening claims in independent form. Claim 20 depends from claim 5 and is subsequently objected to as considered containing allowable subject matter.
The following is a statement of reasons for the indication of allowable subject matter: for dependent claim 5 and 18 the prior art of record, neither anticipates, nor renders obvious each bank of the plurality of banks has a respective switching circuit and each respective switching circuit couples a processor to each bank via the respective switching circuit via a shared bus, and each respective switching circuit couples an erasure module to each individual respective bank via a respective dedicated bus. Claim 20 depends from claim 5 and would be allowable based on its dependency.
The following is a statement of reasons for the indication of allowable subject matter: for dependent claim 6 the prior art of record, neither anticipates, nor renders obvious each switching circuit comprising a pair of buffers, where one of the buffers interfaces between a processor and a respective bank, and the other buffer in the pair interfaces between an erasure module and a respective bank.
The following is a statement of reasons for the indication of allowable subject matter: for dependent claim 7 the prior art of record, neither anticipates, nor renders obvious an erasure module erase operation that overwrites data at a first address, reads data from the first address, determines whether the data has been overwritten correctly, where when it is determined the data has not been correctly overwritten it re-overwrites the data at the first address, and when it is determined the data has been correctly overwritten then data at a second address is overwritten.
The following is a statement of reasons for the indication of allowable subject matter: for dependent claims 11 and 13 the prior art of record, neither anticipates, nor renders obvious monitoring the output of the backup power source and determining if the output is below a predetermined threshold voltage for sufficient power to perform an erasure operation, and when it is determined output is below the predetermined threshold, a signal is sent to the erasure module to perform the erasure operation.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Traister et al., US Pub. No. 2009/0089482 A1 – teaches “Erase blocks are operated in banks, with each bank having a dedicated bus and controller.” [Abstract]
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD WADDY JR whose telephone number is (571)272-5156. The examiner can normally be reached M-Th 8am-5pm.
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/EW/Examiner, Art Unit 2135
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135