DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is in reply to an application and a preliminary amendment both filed on January 8, 2025 regarding Application No. 18/992,529. Applicants amended claims 4, 18, 20, and 23 and canceled claims 5, 21-22, and 24 in the preliminary amendment. Claims 1-4, 6-20, and 23 are pending.
Priority
The instant application is a 371 National Stage of International Application No. PCT/CN2024/111994, filed on August 14, 2024, which claims priority to Chinese Patent Application No. CN 202311160362.2, filed on September 8, 2023.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 23, 2025 in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the Office. Please note that the Office has included the filing date and art unit number on the IDS.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, “wherein orthographic projections of at least some segments of the power line, the first initialization signal line, the second initialization signal line, the data line, the gate line, the light emission control signal line, and the reset control signal line on the display substrate overlap with the orthographic projection of the anode on the display substrate” recited in claim 17 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 1-4, 6-20, and 23 are objected to for the reasons discussed below.
Claim 1: “the first pixel circuit” (2nd to the last line) should be changed to “[[the]]a first pixel circuit” since the term was not previously recited.
Claim 4: “20um and less than or equal to 40um” (last line) should be changed to “20 micrometers (um) and less than or equal to 40um” to identify the term corresponding to “um”.
Claim 8: “a first electrode of the first circuit transistor” (ll. 5-6) should be changed to “[[a]]the first electrode of the first circuit transistor” since the claim language was previously recited.
Also, “the first electrode of the six circuit transistor” (3rd-4th to the last lines) should be changed to “[[the]]a first electrode of the sixth circuit transistor” since “first electrode...” was not previously recited and for claim language consistency.
Claim 10: “a first electrode and a second electrode of the third circuit transistor that are on a side of the gate away from the active layer” (ll. 2-3) may need to be changed to “[[a]]the first electrode and [[a]]the second electrode of the third circuit transistor [[that ]]are on a side of the gate away from the active layer”, if appropriate. For purposes of examination, the claim language is interpreted as discussed in the rejections.
Claim 13: “a first electrode and a second electrode of the storage capacitor” should be changed to “[[a]]the first electrode plate and [[a]]the second electrode plate of the storage capacitor” since the terms were previously recited and for claim language consistency. For purposes of examination, the claim language is interpreted as discussed in the rejections.
Claim 17: “the orthographic projection of the anode” (3rd to the last line) should be changed to “[[the]]an orthographic projection of the anode” since the claim language was not previously recited.
Claim 20: “a number of the first display regions” (4th to the last line) should be changed to “a number of [[the ]]first display regions” since “first display regions” was not previously recited.
Claims 2-4, 6-20, and 23: these claims depend from an objected to claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 18, and 23 are rejected under 35 U.S.C. 102(a)(1) and/or (a)(2) as being anticipated by Cai et al. in CN 110824797 A (hereinafter Cai; June 23, 2025 IDS reference – an original copy and translation of the abstract was submitted with the IDS; an original copy and full machine language translation is/was provided with the first Office action mailed in response to the filing of the instant application and the preliminary amendment).
Regarding claim 1, Cai teaches:
A display substrate (see FIGs. 7-8), comprising: at least one first display region (4a), a second display region (4b) on at least one side of the at least one first display region, wherein light transmittance of the second display region is lower than light transmittance of the at least one first display region (Cai: FIGs. 7-8, p. 5, ¶ 6 (“... [S]ubstrate 10”), and p. 9, ¶ 1 (“... Referring to FIGS. 7 and 8, the display panel 4 of this embodiment includes a transparent display area 4 a and a non-transparent display area 4 b....”), see also FIGs. 2-6); and
first sub pixels (see 4a in FIG. 8) in the at least one first display region, wherein each of the first sub pixels comprises a first light-emitting element (40) and a first pixel circuit (corresponding to elements below 40 in 4a), wherein the first pixel circuit is configured to drive the first light-emitting element to emit light (Cai: FIGs. 3 and 7-8, p. 7, ¶ 7 (“FIG. 3 is a circuit diagram of a pixel driving circuit with a 2T1C structure.”) and 4th to the last ¶ (“The gate of the switching transistor X1 is electrically connected to a row of scanning signal lines Sn. When the row of scanning signals is the turn-on voltage, the switching transistor X1 keeps the data signals on a column of data signal lines VData on one plate of the first storage capacitor C; scanning When the signal is the turn-off voltage, the data signal held on the first storage capacitor C keeps the driving transistor X2 turned on, so that the power signals on a column of power signal lines VDD continuously supply power to the first sub-pixel 40.”), and p. 9, ¶ 1 (“... The transparent display area 4 a [in FIGs. 7-8] is provided with any of the above-mentioned transparent display panels 1, 2, and 3.”), see also FIGs. 2 and 4-6 and p. 6, ¶ 4 (“As shown in FIG. 1 to FIG. 3, the transparent display panel 1 includes a plurality of first sub-pixels 40 and a first pixel driving circuit located below each first sub-pixel 40....”));
wherein the first pixel circuit comprises transistors (LTPO TFT and LTPS TFT in FIG. 8), wherein at least one of the transistors is an oxide transistor (LTPO TFT) (Cai: FIGs. 3 and 8, p. 6, ¶ 4 (“... Each first pixel driving circuit includes a plurality of first The transistor.... The plurality of first transistors include at least one of a low-temperature polycrystalline oxide transistor and a low-temperature polycrystalline silicon transistor; the low-temperature polycrystalline oxide transistor and / or the low-temperature polycrystalline silicon transistor....”), and p. 9, ¶ 1 (“... The transparent display area 4 a [in FIGs. 7-8] is provided with any of the above-mentioned transparent display panels 1, 2, and 3.”), see also FIGs. 2 and 4-5 and p. 6, ¶5, 4th to the last ¶, and 3rd to the last ¶ (“... Low temperature polysilicon oxide TFT (LTPO TFT)....”)).
Regarding claim 2, Cai teaches:
The display substrate according to claim 1, wherein the transistors comprise oxide transistors and do not comprise polycrystalline silicon transistors (Cai: FIGs. 3 and 8, p. 6, ¶ 4 (“... Each first pixel driving circuit includes a plurality of first The transistor.... The plurality of first transistors include... the low-temperature polycrystalline oxide transistor and / or the low-temperature polycrystalline silicon transistor....”), and p. 9, ¶ 1 (“... The transparent display area 4 a [in FIGs. 7-8] is provided with any of the above-mentioned transparent display panels 1, 2, and 3.”), see also p. 6, ¶ 5 (“... [W]hen several first transistors only include a low-temperature polycrystalline oxide transistor....”)).
Regarding claim 18, Cai teaches:
The display substrate according to claim 1, wherein the display substrate further comprises second sub pixels (see 4b in FIG. 8) in the second display region, wherein each of the second sub pixels comprising a second light emitting element (50) and a second pixel circuit (corresponding to elements below 50 in 4b), wherein the second pixel circuit is configured to drive the second light emitting element to emit light (Cai: FIGs. 7-8 and p. 9, ¶ 2 (“As shown in FIG. 8, the non-transparent display area 4 b may include a plurality of second pixel units, and the second pixel unit includes a plurality of second sub-pixels 50....”) and ¶ 3 (“In FIG. 8, there is a second pixel driving circuit below each second sub-pixel 50. Each second pixel driving circuit includes a plurality of second transistors and a second storage capacitor C ′, and the first transistor and the second transistor have the same function. The first transistor having the same function as the low temperature polycrystalline oxide transistor or the same low-temperature polysilicon transistor and the corresponding layer in the second transistor are located on the same layer. The corresponding layer may include at least one of a gate, a low-temperature polycrystalline oxide layer, a low-temperature polysilicon layer, a gate insulating layer, a source, and a drain. Exemplarily, having the same function means that both the first transistor and the second transistor are switching transistors, or both are driving transistors, or both are light emitting transistors.”), see also FIGs. 2-3, p. 7, ¶ 7 and 4th to the last ¶, and p. 9, ¶ 1);
wherein the second pixel circuit comprises transistors (LTPO TFT and LTPS TFT in FIG. 8), wherein the transistors of the second pixel circuit comprise oxide transistors (LTPO TFTs) and/or polycrystalline silicon transistors (LTPS TFTs) (Cai: FIG. 8 and p. 9, ¶ 3 (“... Each second pixel driving circuit includes a plurality of second transistors... ”, and the first transistor and the second transistor have the same function. The first transistor having the same function as the low temperature polycrystalline oxide transistor or the same low-temperature polysilicon transistor and the corresponding layer in the second transistor are located on the same layer. The corresponding layer may include at least one of... a low-temperature polycrystalline oxide layer... [and] a low-temperature polysilicon layer....”), see also p. 6, ¶ 4).
Regarding claim 23, Cai teaches:
A display device (e.g., mobile phone) comprising the display substrate according to claim 1 (Cai: p. 11, 8th to the last ¶ (“Based on the... display panel 4, an embodiment of the present invention further provides a display device.”), 7th to the last ¶ (“The display device may be a display device such as a mobile phone, a tablet computer, an on-board display, and the like.”), 6th to the last ¶ (“The display device includes:”), and 4th to the last ¶ (“... [D]isplay panel 4 are covered on the casing....”); claim 1 above);
wherein the display device further comprises at least one optical sensor (photosensitive device), and the at least one first display region is set respectively corresponding to the at least one optical sensor (Cai: p. 11, 3rd to the last ¶ (“The device area is located below... the transparent display area 4a of the display panel 4, and the device area is provided with light... collected through... the transparent display area 4a. Photosensitive device.” and 2nd to the last ¶ (“The light sensing device may include at least one of a camera, an infrared sensor,... a flood light sensing element, [and] an ambient light sensor....”)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicants are advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 3 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Cai in view of Li et al. in US 2022/0139968 A1 (hereinafter Li).
Regarding claim 3, Cai teaches:
The display substrate according to claim 1, wherein the transistors comprise an oxide transistor and a polycrystalline silicon transistor (Cai: p. 6, ¶ 4 (“... Each first pixel driving circuit includes a plurality of first The transistor.... The plurality of first transistors include at least one of a low-temperature polycrystalline oxide transistor and a low-temperature polycrystalline silicon transistor; the low-temperature polycrystalline oxide transistor and / or the low-temperature polycrystalline silicon transistor....”), and p. 9, ¶ 1 (“... The transparent display area 4 a [in FIGs. 7-8] is provided with any of the above-mentioned transparent display panels 1, 2, and 3.”), see also FIGs. 2-6 and 8).
However, it is noted that Cai does not teach:
the oxide transistor and polycrystalline silicon transistor are oxide transistors and polycrystalline silicon transistors,
and a number of the polycrystalline silicon transistors is greater than a number of the oxide transistors.
Li teaches:
wherein transistors (T1-T6 and Td in Fig. 2) comprise oxide transistors and polycrystalline silicon transistors, and a number of the polycrystalline silicon transistors is greater than a number of the oxide transistors (Li: Fig. 2 and “[0069]... [T]he first transistor T1 and the second transistor T2 are set to be oxide transistors..., and the other transistors are still low temperature poly-silicon transistors....”).
Before the effective filing date of the claimed invention, it would have been obvious to include: the features taught by Li, such that Cai as modified teaches: wherein the transistors comprise oxide transistors and polycrystalline silicon transistors, and a number of the polycrystalline silicon transistors is greater than a number of the oxide transistors (transistors and oxide and polycrystalline silicon transistors of Cai combined with the transistors, oxide and polycrystalline silicon transistors, and number of polycrystalline silicone transistors, and number of oxide transistors of Li), so that a capacitor can be well closed. (Li: “[0069] In the pixel drive circuit shown in FIG. 2, each transistor is a low temperature poly-silicon transistor, due to the higher leakage of low temperature poly-silicon transistor, the capacitor Cst cannot be well closed.... In the present disclosure, when the first transistor T1 and the second transistor T2 are set to be oxide transistors with low leakage, and the other transistors are still low temperature poly-silicon transistors, the above problem can be well solved.”).
Regarding claim 7, Cai as modified teaches:
The display substrate according to claim 6, wherein the second circuit transistor is an oxide transistor (Cai: p. 10, ¶ 5 (“... [T]he first sub-transistor M1 of the second pixel driving circuit is... a low-temperature polycrystalline oxide transistor....”)).
However, it is noted that Cai as modified does not teach:
the first circuit transistor is an oxide transistor.
Li teaches:
wherein a first circuit transistor (T1 in Fig. 2) and a second circuit transistor (T2) are oxide transistors (Li: Fig. 2 and “[0069]... [T]he first transistor T1 and the second transistor T2 are set to be oxide transistors....”).
Before the effective filing date of the claimed invention, it would have been obvious to include: the features taught by Li, such that Cai as modified teaches: wherein the first circuit transistor and the second circuit transistor are oxide transistors (first and second circuit transistors and oxide transistor of Cai as modified combined with the first and second circuit transistors and oxide transistors of Li), so that a capacitor can be well closed. (Li: “[0069] In the pixel drive circuit shown in FIG. 2, each transistor is a low temperature poly-silicon transistor, due to the higher leakage of low temperature poly-silicon transistor, the capacitor Cst cannot be well closed.... In the present disclosure, when the first transistor T1 and the second transistor T2 are set to be oxide transistors with low leakage, and the other transistors are still low temperature poly-silicon transistors, the above problem can be well solved.”).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Cai in view of Yamashita et al. in US 2016/0125805 A1 (hereinafter Yamashita).
Regarding claim 4, Cai teaches:
The display substrate according to claim 1, wherein the first pixel circuit comprises a driving transistor (X2 in FIG.3), wherein the driving transistor is a polycrystalline silicon transistor (Cai: FIGs. 3 and 8, p. 6, ¶ 4 (“... Each first pixel driving circuit includes a plurality of first The transistor.... The plurality of first transistors include at least one of a low-temperature polycrystalline oxide transistor and a low-temperature polycrystalline silicon transistor; the low-temperature polycrystalline oxide transistor and / or the low-temperature polycrystalline silicon transistor....”), p. 7, 5th to the last ¶ (“As shown in FIG. 3, the first pixel driving circuit includes... a driving transistor X2....”), and p. 9, ¶ 1 (“... The transparent display area 4 a [in FIGs. 7-8] is provided with any of the above-mentioned transparent display panels 1, 2, and 3.”), see also FIGs. 2 and 4-6 and p. 6, ¶¶ 6-7).
However, it is noted that Cai does not teach:
wherein a length of a channel of the driving transistor is greater than or equal to 20um and less than or equal to 40um.
Yamashita teaches:
wherein a length of a channel of a driving transistor (Trd in FIG. 5) is greater than or equal to 20um and less than or equal to 40um (Yamashita: e.g., equal to 20 μm; FIGs. 1-2 and 5, “[0044]... The transistor[]... Trd [of pixel circuit 2 is a]... polysilicon TFT....”, “[0056]...FIG. 5 shows a schematic diagram depicting a single pixel circuit taken out of the image display device shown in FIG. 2....”, and “[0063]... [T]he length L of the drive transistor Trd is designed to be 10 μm or greater....”).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to include: the features taught by Yamashita, such that Cai as modified teaches: wherein a length of a channel of the driving transistor is greater than or equal to 20um and less than or equal to 40um (driving transistor of Cai combined with the length of a channel of a driving transistor of Yamashita), “[f]or the measures against image quality defectives....” (Yamashita: [0063]).
Claims 6, 8-9, 11, and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Cai.
Regarding claim 6, Cai teaches:
The display substrate according to claim 1, wherein the first pixel circuit comprises a third circuit transistor (X2 in FIG. 3), wherein the third circuit transistor is a driving transistor (Cai: FIGs. 3 and 8, p. 7, 5th to the last ¶ (“As shown in FIG. 3, the first pixel driving circuit includes... a driving transistor X2....”), and p. 9, ¶ 1 (“... The transparent display area 4 a [in FIGs. 7-8] is provided with any of the above-mentioned transparent display panels 1, 2, and 3.”).
However, it is noted that Cai (FIGs. 1-3 and 7-8) does not teach:
wherein the first pixel circuit comprises a first circuit transistor, a second circuit transistor, wherein a first electrode of the first circuit transistor, a gate of the third circuit transistor, and a second electrode of the second circuit transistor are connected, a first electrode of the second circuit transistor is connected to a second electrode of the third circuit transistor.
Cai (FIG. 9) also teaches:
wherein a first pixel circuit (see FIG. 9) comprises a first circuit transistor (M5), a second circuit transistor (M1), and a third circuit transistor (M7), wherein a first electrode (upper electrode) of the first circuit transistor, a gate of the third circuit transistor, and a second electrode (upper electrode) of the second circuit transistor are connected, a first electrode (lower electrode) of the second circuit transistor is connected to a second electrode (lower electrode) of the third circuit transistor, and the third circuit transistor is a driving transistor (Cai: FIG. 9, p. 9, 5th to the last ¶ (“... The first pole of the first sub-transistor M1 and the sixth sub-transistor M6 are connected. The first pole of the first sub-transistor M7 is connected to the second pole of the seventh sub-transistor M7, and the second pole of the first sub-transistor M1 is connected to the gate of the seventh sub-transistor M7 and the second plate of the second storage capacitor C';”) and last ¶ (“... The first pole of the fifth sub-transistor M5 is connected to the gate of the seventh sub-transistor M7 and the second of the second storage capacitor C ′....;”), and p. 10, ¶ 4 (“... [T]he seventh sub-transistor M7 is a driving transistor.”)).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to include: the features also taught by Cai, such that Cai as modified teaches:
wherein the first pixel circuit comprises a first circuit transistor, a second circuit transistor, and a third circuit transistor, wherein a first electrode of the first circuit transistor, a gate of the third circuit transistor, and a second electrode of the second circuit transistor are connected, a first electrode of the second circuit transistor is connected to a second electrode of the third circuit transistor, and the third circuit transistor is a driving transistor (first pixel circuit, third circuit transistor, and driving transistor of Cai combined with the first pixel circuit, first to third circuit transistors, connected, and driving transistor also of Cai), for image display.
Regarding claim 8, Cai as modified teaches:
The display substrate according to claim 6, wherein the first pixel circuit further comprises a power line (VDD in FIG. 9), a first initialization signal line (Vint corresponding to M5), a second initialization signal line (Vint corresponding to M4), and a data line (VData) (Cai: FIG. 9, p. 5, 10th to the last ¶ (“Power signal line VDD...”), and p. 9, 4th to the last ¶ (“... [D]ata signal line VData....”), 2nd to the last ¶ (“... The second electrode [of the fourth sub-transistor M4] is connected to the initial voltage signal line Vinit....”), and last ¶ (“... [T]he second electrode of the fifth sub-transistor M5 is connected to the initial voltage signal line Vinit....”));
wherein the first pixel circuit comprises a storage capacitor (C’), a fourth circuit transistor (M2), a fifth circuit transistor (M3), a sixth circuit transistor (M6), and a seventh circuit transistor (M4), wherein a first electrode of the first circuit transistor is connected to a first electrode plate (lower electrode plate) of the storage capacitor, a second electrode (lower electrode) of the first circuit transistor is connected to the first initialization signal line, the power line is connected to a second electrode plate (upper electrode plate) of the storage capacitor and a first electrode (right side electrode) of the fifth circuit transistor, a second electrode (left side electrode) of the fifth circuit transistor is connected to a first electrode (upper electrode) of the third circuit transistor and a second electrode (right side electrode) of the fourth circuit transistor, a first electrode (left side electrode) of the fourth circuit transistor is connected to the data line, the first electrode of the second circuit transistor is connected to the first electrode (upper electrode) of the six circuit transistor, a second electrode (lower electrode) of the sixth circuit transistor is connected to a second electrode (left side electrode) of the seventh circuit transistor, and a first electrode (right side electrode) of the seventh circuit transistor is connected to the second initialization signal line (Cai: FIG. 9 and p. 9, 5th to the last ¶ - p. 10, ¶ 3).
Regarding claim 9, Cai as modified teaches:
The display substrate according to claim 8, wherein the third circuit transistor is a polycrystalline silicon transistor, and the second circuit transistor and the sixth circuit transistor are oxide transistors (Cai: p. 10, ¶ 5 (“... [T]he first sub-transistor M1 of the second pixel driving circuit is... a low-temperature polycrystalline oxide transistor....”), 3rd to the last ¶ (“... [T]he seventh sub-transistor M7 of the second pixel driving circuit is... a low-temperature polysilicon transistor....”), and 2nd to the last ¶ (“... [T] the sixth sub-transistor M6 of the second pixel driving circuit is also a low temperature polycrystalline oxide transistor....”)).
However, it is noted that Cai as modified does not teach:
the first circuit transistor, the fourth circuit transistor, the fifth circuit transistor, and the seventh circuit transistor are oxide transistors,
but which would have been obvious to include, such that Cai as modified teaches: wherein the third circuit transistor is a polycrystalline silicon transistor, and the first circuit transistor, the second circuit transistor, the fourth circuit transistor, the fifth circuit transistor, the sixth circuit transistor, and the seventh circuit transistor are oxide transistors (first to seventh transistors, polycrystalline silicon transistor, and oxide transistors of Cai modified as discussed), since it would have been within the general skill of one of ordinary skill in the art to select features based on their suitability for the intended use for higher light transmittance.
Regarding claim 11, Cai as modified teaches:
The display substrate according to claim 9, wherein the first light-emitting element comprises an anode (41 in FIG. 8), a light-emitting layer (42), and a cathode (43) that are arranged sequentially away from the first pixel circuit (Cai: FIGs. 2-3 and 8, p. 6, 2nd to the last ¶ (“... The first electrode 41, the first light-emitting structure block 42, and the second electrode 43 constitute a first sub-pixel 40.... The first electrode 41 may be an anode.... The second electrode 43 may be a cathode....”), and p. 9, ¶ 1 (“The transparent display area 4 a [in FIGs. 7-8] is provided with any of the above-mentioned transparent display panels 1, 2, and 3.”));
wherein an orthographic projection of the third circuit transistor on the display substrate is within an orthographic projection of the anode on the display substrate (Cai: FIGs. 2-3 and 8, p. 6, last ¶ (“Referring to FIG. 2, the low-temperature polysilicon transistor includes, from bottom to top, a low-temperature polysilicon semiconductor active layer 11 (including a first source region, a first drain region, and a first trench between the first source region and the first drain region). (Track region), the first gate insulating layer 12, the first gate 13, the first source 14a connected to the first source region, and the first drain 14b connected to the first drain region.”), p. 9, ¶ 1 (“The transparent display area 4 a [in FIGs. 7-8] is provided with any of the above-mentioned transparent display panels 1, 2, and 3.”), and p. 10, 3rd to the last ¶ (“In the embodiment shown in FIG. 8, the driving transistor X2 of the first pixel driving circuit is a low temperature polysilicon transistor....”)).
Regarding claim 13, Cai as modified teaches:
The display substrate according to claim 8, wherein a first electrode and a second
electrode of the storage capacitor are both made of transparent conductive materials (Cai: FIGs. 2-3 and 8-9, p. 7, ¶ 1 (“... The material of the lower electrode plate 21 and the upper electrode plate
23 [of the first storage capacitor C in FIG. 2] may be metal or transparent conductive metal oxide (ITO).”), and p. 9, ¶ 1 (“The transparent display area 4 a [in FIGs. 7-8] is provided with any of the above-mentioned transparent display panels 1, 2, and 3.”); Note: “first electrode” and “second electrode” are interpreted as discussed in the claim objections above).
Regarding claim 14, Cai as modified teaches:
The display substrate according to claim 8, further comprising: a gate line (Sn in FIG. 9), a light emission control signal line (EM), and a reset control signal line (Sn-1), wherein the gate line is connected to a gate of the second circuit transistor and a gate of the fourth circuit transistor; the light emission control signal line is connected to a gate of the fifth circuit transistor and a gate of the sixth circuit transistor; and the reset control signal line is connected to a gate of the first circuit transistor and a gate of the seventh circuit transistor (Cai: FIG. 9, p. 9, 5th to the last ¶ (“The gate of the first sub-transistor M1 is connected to the scanning signal line Sn....”), 3rd to the last ¶ (“The gate of the third sub-transistor M3 is connected to the gate of the sixth sub-transistor M6....”), 2nd to the last ¶ (“The gate of the fourth sub-transistor M4 is connected to the scanning signal line Sn-1.... The second electrode is connected to the initial voltage signal line Vinit....”), and last ¶ (“The gate of the fifth sub-transistor M5 is connected to the scanning signal line Sn-1.... [T]he second electrode of the fifth sub-transistor M5 is connected to the initial voltage signal line Vinit....”), and p. 10, ¶ 1 (“The gate of the sixth sub-transistor M6 is connected to the light-emitting signal line EM....”), see also FIG. 3 and p. 7, 4th to the last ¶ (“The gate of the switching transistor X1 [in FIG. 3] is electrically connected to a row of scanning signal lines Sn....”)).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Cai in view Xu et al. in US 2022/0102460 A1 (hereinafter Xu ‘460).
Regarding claim 10, Cai as modified teaches:
The display substrate according to claim 9, wherein the third circuit transistor comprises an active layer (11 in FIG. 8), a gate (13) on a side of the active layer, a first electrode (one of 14a and 14b) and a second electrode (other of 14a and 14b) of the third circuit transistor that are on a side of the gate away from the active layer, wherein the first electrode and the second electrode of the third circuit transistor are connected to the active layer (Cai: FIGs. 2 and 8, p. 5, ¶ 10 (“Low-temperature polysilicon semiconductor active layer 11...”), and p. 10, 3rd to the last ¶ (“... [T]he low-temperature polysilicon semiconductor layer 11 in the driving transistor X2 of the first pixel driving circuit..., and the first gate in the driving transistor X2 of the first pixel driving circuit 13..., and the first source electrode 14a / first drain electrode 14b in the driving transistor X2 of the first pixel driving circuit....”), see also FIG. 3 and p. 9, ¶ 1).
However, it is noted that Cai as modified does not teach:
the display substrate further comprises a first light shielding layer, wherein the first light shielding layer is on a side of the active layer away from the gate, and an orthographic projection of the third circuit transistor on the display substrate is within an orthographic projection of the first light shielding layer on the display substrate.
Xu ‘460 teaches:
a display substrate (see FIGs. 2A-B) further comprises a first light shielding layer (11), wherein the first light shielding layer is on a side of an active layer (21) away from a gate (22), and an orthographic projection of a third circuit transistor (T2) on the display substrate is within an orthographic projection of the first light shielding layer on the display substrate (Xu ‘460: FIGs. 2A-B, “[0101]... The drive transistor T2 includes an active layer 21, a gate electrode 22, a first electrode 23 and a second electrode 24....”, and “[0107]... [A]s shown in FIGS. 2A to 2B, a display substrate... further includes a light shield layer 11... disposed on a side of the active layer of the transistor close to the base substrate 10....”, see also [0106], [0112], and [0132]).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to include: the features taught by Xu, such that Cai as modified teaches: and the display substrate further comprises a first light shielding layer, wherein the first light shielding layer is on a side of the active layer away from the gate, and an orthographic projection of the third circuit transistor on the display substrate is within an orthographic projection of the first light shielding layer on the display substrate (display substrate, active layer, gate, and third circuit transistor of Cai as modified combined with the display substrate, first light shielding layer, active layer, gate, and orthographic projections of Xu ‘460), to block light.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Cai in view Park et al. in US 2021/0020723 A1 (hereinafter Park).
Regarding claim 12, Cai as modified teaches:
The display substrate according to claim 8.
However, it is noted that Cai as modified does not teach:
wherein the display substrate comprises a second light shielding layer, wherein orthographic projections of the first circuit transistor, the second circuit transistor, the fourth circuit transistor, the fifth circuit transistor, the sixth circuit transistor, and the seventh circuit transistor on the display substrate is within an orthographic projection of the second light shielding layer on the display substrate.
Park teaches:
wherein a display substrate (see FIGs. 6 and 8) comprises a second light shielding layer (BSM in FIG. 8), wherein orthographic projections of a first circuit transistor (ST1 in FIG. 6), a second circuit transistor (ST3), a fourth circuit transistor (ST2), a fifth circuit transistor (ST4), a sixth circuit transistor (ST5), and a seventh circuit transistor (ST6) on the display substrate is within an orthographic projection of the second light shielding layer on the display substrate (Park: FIGs. 6 and 8 and “[0173]... [T}he light shielding layer BSM may overlap not only the active layer DT_ACT of the driving transistor DT but also the active layers ACT1 through ACT6 of the first through sixth transistors ST1 through ST6. The light shielding layer BSM may be a single layer or a multilayer....”).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to include: the features taught by Park, such that Cai as modified teaches: wherein the display substrate comprises a second light shielding layer, wherein orthographic projections of the first circuit transistor, the second circuit transistor, the fourth circuit transistor, the fifth circuit transistor, the sixth circuit transistor, and the seventh circuit transistor on the display substrate is within an orthographic projection of the second light shielding layer on the display substrate (display substate and first, second, and fourth to seventh circuit transistors of Cai as modified combined with the display substrate, second light shielding layer, and orthographic projections of Park), to block light. (Park: see [0173]).
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Cai in view Xu et al. in US 2020/0243801 A1 (hereinafter Xu ‘801).
Regarding claim 15, Cai as modified teaches:
The display substrate according to claim 14.
However, it is noted that Cai as modified does not teach:
wherein at least one of the power line, the first initialization signal line, the second initialization signal line, the data line, the gate line, the light emission control signal line, and the reset control signal line is made of a transparent conductive material.
Xu ‘801 teaches:
wherein at least one of a power line (VDD), an initialization signal line (Vref signal line), a data line (Vdata), a gate line (SCAN line), a light emission control signal line (EM line), and a reset control signal line (SCAN corresponding to Vref) is made of a transparent conductive material (Xu ‘801: FIG. 2, “[0079] A laminate 002 is disposed on the substrate 001, and the laminate here forms a pixel circuit, such as... 7T1C and other pixel circuits....”, and “[0082]... The conductive lines [0041 in FIG. 2] comprise at least one of the scan lines, data lines, power lines, and reset lines. The scan lines may comprise a SCAN line and an EM line, and the data line is Vdata, the power line is VDD..., and the reset line is Vref.... [T]he conductive line 0041 may be made of transparent conductive materials....”).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to include: the features taught by Xu ‘801, such that Cai as modified teaches: wherein at least one of the power line, the first initialization signal line, the second initialization signal line, the data line, the gate line, the light emission control signal line, and the reset control signal line is made of a transparent conductive material (power, data, and gate lines and first and second initialization, light emission control, and reset control signals lines of Cai as modified combined with the power, data, and gate lines, initialization, light emission control, and reset control signals lines, and transparent conductive material of Xu ‘801; also, it would have been obvious to include the claimed features since it would have been within the general skill of one of ordinary skill in the art to select features on the basis of their suitability for the intended use for higher light transmittance), for higher light transmittance.
Regarding claim 16, Cai as modified by Xu ‘801 teaches:
The display substrate according to claim 15, wherein all of the power line, the first initialization signal line, the second initialization signal line, the data line, the gate line, the light emission control signal line, and the reset control signal line are made of transparent conductive materials (Xu ‘801: FIG. 2, “[0079] A laminate 002 is disposed on the substrate 001, and the laminate here forms a pixel circuit, such as... 7T1C and other pixel circuits....”, and “[0082]... The conductive lines [0041 in FIG. 2] comprise at least one of the scan lines, data lines, power lines, and reset lines. The scan lines may comprise a SCAN line and an EM line, and the data line is Vdata, the power line is VDD..., and the reset line is Vref.... [T]he conductive line 0041 may be made of transparent conductive materials....”; claim 8 above; also, it would have been obvious to include the claimed features since it would have been within the general skill of one of ordinary skill in the art to select features on the basis of their suitability for the intended use for higher light transmittance).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Cai in view Shang et al. in WO 2021/189305 A1 (hereinafter Shang; US 2022/0320244 A1 is being used as a translation thereof).
Regarding claim 17, Cai as modified teaches:
The display substrate according to claim 14, wherein the first light-emitting element comprises an anode (41 in FIG. 8), a light-emitting layer (42), and a cathode (43) that are arranged sequentially away from the first pixel circuit (Cai: FIGs. 2-3 and 8, p. 6, 2nd to the last ¶ (“... The first electrode 41, the first light-emitting structure block 42, and the second electrode 43 constitute a first sub-pixel 40.... The first electrode 41 may be an anode.... The second electrode 43 may be a cathode....”), and p. 9, ¶ 1 (“The transparent display area 4 a [in FIGs. 7-8] is provided with any of the above-mentioned transparent display panels 1, 2, and 3.”)).
However, it is noted that Cai as modified does not teach:
wherein orthographic projections of at least some segments of the power line, the first initialization signal line, the second initialization signal line, the data line, the gate line, the light emission control signal line, and the reset control signal line on the display substrate overlap with the orthographic projection of the anode on the display substrate, wherein the at least some segments overlapping with the anode are made of metal materials, and remaining segments are made of transparent conductive materials.
Shang teaches:
wherein orthographic projections of at least some segments of a power line (151 in FIGs. 31 and 37A), a first initialization signal line (141 corresponding to T6 in FIG. 31, see also 141 in FIG. 37A), a second initialization signal line (141 corresponding to T7, see also 141 in FIG. 37A), a data line (152 in FIG. 31, see also 150 in FIG. 37A), a gate line (132 in FIGs. 31 and 37A), a light emission control signal line (133 in FIG. 31), and a reset control signal line (131 in FIGs. 31 and 37A) on a display substrate (see FIGs. 31 and 37A) overlap with the orthographic projection of an anode (1751-1754 in FIGs. 37A-B) on the display substrate (Shang: FIGs. 31 and 37A-B,”[0243]... [A]s shown in FIG. 31,... a data line 152, and... the power line 151.... [R]eset signal line 131 and gate electrode line 132.”, “[0244]... [T]he initialization signal line 141....”, “[0247]... [T]he emission control line 133....”, and “[0270] FIG. 37A is a partial schematic diagram of another display substrate... FIG. 37B shows only the anode layer [(first to fourth anodes 1751-1754)]....”, see also FIGs. 30B-D, 32, and 38, “[0285]... [A]s shown in FIG. 30D, the first conductive layer 150 includes a power line 151... [and] a data line 152... that extend along the second direction....”, and “[0294]... As shown in FIG. 38, the display device 400 includes any foregoing display substrate 100....”).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to include: the features taught by Shang, for “improving the long-term light emission stability and the service life of the display substrate.” (Shang: [0271]).
However, it is noted that Cai as modified by Shang does not teach:
wherein the at least some segments overlapping with the anode are made of metal materials, and remaining segments are made of transparent conductive materials,
but which would have been obvious to include, such that Cai as modified teaches: wherein orthographic projections of at least some segments of the power line, the first initialization signal line, the second initialization signal line, the data line, the gate line, the light emission control signal line, and the reset control signal line on the display substrate overlap with the orthographic projection of the anode on the display substrate (power, data, and gate lines, first and second initialization, light emission control, and reset control signal lines, anode, and display substrate of Cai as modified combined with the at least some segments of the power, data, and gate lines, first and second initialization, light emission control, and reset control signal lines, anode, and display substrate of Shang), wherein the at least some segments overlapping with the anode are made of metal materials, and remaining segments are made of transparent conductive materials (anode of Cai as modified combined with the at least some segments overlapping with the anode of Shang modified as discussed), since it would have been within the general skill of one of ordinary skill in the art to select features based on their suitability for the intended use for higher light transmittance.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Cai in view Liu et al. in US 2022/0093699 A1 (hereinafter Liu), in further view of Xu ‘801.
Regarding claim 19, Cai teaches:
The display substrate according to claim 18.
However, it is noted that Cai (FIGs. 1-3 and 7-8) does not teach:
wherein the third pixel circuit comprises a power line, a first initialization signal line, a second initialization signal line, a data line, a gate line, a light emission control signal line, and a reset control signal line, wherein the power line, the first initialization signal line, the second initialization signal line, the data line, the gate line, the light emission control signal line, and the reset control signal line in the third pixel circuit are metal wires, and the third pixel circuit uses same transistors as the first pixel circuit.
Cai (FIG. 9) also teaches:
wherein a pixel circuit (see FIG. 9) comprises a power line (VDD), a first initialization signal line (Vint corresponding to M5), a second initialization signal line (Vint corresponding to M4), a data line (VData), a gate line (Sn), a light emission control signal line (EM), and a reset control signal line (Sn-1) (Cai: FIG. 9, p. 5, 10th to the last ¶ (“Power signal line VDD...”), and p. 9, 5th to the last ¶ (“The gate of the first sub-transistor M1 is connected to the scanning signal line Sn....”), 3rd to the last ¶ (“The gate of the third sub-transistor M3 is connected to the gate of the sixth sub-transistor M6....”), 4th to the last ¶ (“... [D]ata signal line VData....”), 2nd to the last ¶ (“The gate of the fourth sub-transistor M4 is connected to the scanning signal line Sn-1.... The second electrode is connected to the initial voltage signal line Vinit....”), and last ¶ (“The gate of the fifth sub-transistor M5 is connected to the scanning signal line Sn-1.... [T]he second electrode of the fifth sub-transistor M5 is connected to the initial voltage signal line Vinit....”), and p. 10, ¶ 1 (“The gate of the sixth sub-transistor M6 is connected to the light-emitting signal line EM....”), see also FIG. 3 and p. 7, 4th to the last ¶ (“The gate of the switching transistor X1 [in FIG. 3] is electrically connected to a row of scanning signal lines Sn....”)).
Before the effective filing date of the claimed invention, it would have been obvious to include: the features also taught by Cai, for image display.
However, it is noted that Cai as modified does not teach:
further comprising a transition display region between the at least one first display region and the second display region, wherein the transition display region surrounds the at least one first display region; and
the display substrate further comprises third sub pixels located in the transition display region, wherein each of the third sub pixels comprise a third light emitting element and a third pixel circuit, wherein the third pixel circuit is configured to drive the third light emitting element to emit light; and
wherein the third pixel circuit comprises the power line, the first initialization signal line, the second initialization signal line, the data line, the gate line, the light emission control signal line, and the reset control signal line, wherein the power line, the first initialization signal line, the second initialization signal line, the data line, the gate line, the light emission control signal line, and the reset control signal line in the third pixel circuit are metal wires, and the third pixel circuit uses same transistors as the first pixel circuit.
Liu teaches:
a transition display region (22 in FIGs. 2-3) between at least one first display region (21) and a second display region (23), wherein the transition display region surrounds the at least one first display region (Liu: FIGs. 2-3 and “[0020]... [Referring to FIG. 2,] since the second display area 22 is located between the first display area 21 and the third display area 23, and the display substrate 2 includes a plurality of first pixel circuits 26 arranged in the first display area 21 and arranged in an array, the display substrate 2 includes a plurality of second pixel circuits 27 arranged in the third display area 23 and arranged in an array, and the display substrate 2 includes a plurality of first pixel circuits 26 and a plurality of second pixel circuits 27 arranged in the second display area 22 and arranged in an array, each of the first pixel circuits 26 is different from each of the second pixel circuits 27, so that a display brightness of the second display area 22 is between a display brightness of the first display area 21 and a display brightness of the third display area 23. In this way, a display brightness of the display substrate 2 can be gradually transitioned....”, see also FIGs. 1 and 4 and [0031]); and
a display substrate (see FIGs. 2-3) further comprises third sub pixels located in the transition display region, wherein each of the third sub pixels comprise a third light emitting element and a third pixel circuit (26 in 22 in FIG. 3), wherein the third pixel circuit is configured to drive the third light emitting element to emit light (Liu: FIG. 3 and “[0019]... [T]he plurality of first sub-pixels are connected with the plurality of first pixel circuits 26.... The display substrate 2 includes a plurality of first sub-pixels... arranged in the second display area 22, the display substrate 2 also includes a plurality of first pixel circuits 26... arranged in the second display area 22....”, see also FIG. 2, [0020], and [0031]); and
wherein the third pixel circuit is a 7T1C pixel circuit, and the third pixel circuit uses same transistors as a first pixel circuit (26 in 21 in FIG. 3) (Liu: FIG. 3, “[0019]... [T]he plurality of first pixel circuits 26... are arranged in the first display area 21.... [A] plurality of first pixel circuits 26... arranged in the second display area 22....”, “[0034]... [T]he first pixel circuit 26 is an nTmC pixel circuit....”, “[0035]... [T]he above-mentioned nTmC pixel circuit can be... a 7T1C pixel circuit....”, and “[0037]... A transistor in the first pixel circuit 26 is a low-temperature polysilicon (LTPS) transistor....”, see also [0038]).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to include: the features taught by Liu, to improve display effect, resolution, and a refresh rate, and reduce power consumption. (Liu: “[0020]... [A] display brightness of the second display area 22 is between a display brightness of the first display area 21 and a display brightness of the third display area 23. In this way, a display brightness of the display substrate 2 can be gradually transitioned, thereby avoiding an obvious boundary between adjacent display areas due to a large difference in display brightness between adjacent display areas, and thus display effect is improved.” and “[0037]... [W]hen the number of transistors in the first pixel circuit 26 is equal to the number of transistors in the second pixel circuit 27, the number of capacitors in the first pixel circuit 26 is equal to the number of capacitors in the second pixel circuit 27, the transistors in the first pixel circuit 26 are low-temperature polysilicon transistors, and the transistors in the second pixel circuit 27 are low-temperature polycrystalline oxide transistors, it is convenient to improve a resolution and a refresh rate of the third display area 23 and reduce a power consumption of the third display area 23.”).
However, it is noted that Cai as modified by Liu does not teach:
wherein the power line, the first initialization signal line, the second initialization signal line, the data line, the gate line, the light emission control signal line, and the reset control signal line in the third pixel circuit are metal wires.
Xu ‘801 teaches:
wherein a power line (VDD), an initialization signal line (Vref signal line), a data line (Vdata), a gate line (SCAN line), a light emission control signal line (EM line), and a reset control signal line (SCAN corresponding to Vref) in a pixel circuit are metal wires (Xu: FIG. 2, “[0079] A laminate 002 is disposed on the substrate 001, and the laminate here forms a pixel circuit, such as... 7T1C and other pixel circuits....”, and “[0082]... The conductive lines [0041 in FIG. 2] comprise at least one of the scan lines, data lines, power lines, and reset lines. The scan lines may comprise a SCAN line and an EM line, and the data line is Vdata, the power line is VDD..., and the reset line is Vref.... [T]he conductive line 0041 may be made of transparent conductive materials. Indium tin oxide (ITO), indium zinc oxide (IZO), or silver-doped oxide, Indium tin oxide (Ag+ITO), or silver-doped indium zinc oxide (Ag+IZO) may be generally used....”).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to include: the features taught by Xu ‘801, such that Cai as modified teaches: further comprising a transition display region between the at least one first display region and the second display region, wherein the transition display region surrounds the at least one first display region (at least one first and second display regions of Cai combined with the transition, at least one first, and second display regions of Liu); and the display substrate further comprises third sub pixels located in the transition display region, wherein each of the third sub pixels comprise a third light emitting element and a third pixel circuit, wherein the third pixel circuit is configured to drive the third light emitting element to emit light (display substrate of Cai combined with the display substrate, each/third sub pixels, light emitting element, pixel circuit, transition display region, drive, and emit of Liu); and wherein the third pixel circuit comprises a power line, a first initialization signal line, a second initialization signal line, a data line, a gate line, a light emission control signal line, and a reset control signal line, wherein the power line, the first initialization signal line, the second initialization signal line, the data line, the gate line, the light emission control signal line, and the reset control signal line in the third pixel circuit are metal wires, and the third pixel circuit uses same transistors as the first pixel circuit (pixel circuit, power, data, and gate lines, and first and second initialization, light emission control, and reset control signal lines of Cai as modified combined with the third and first pixel circuits and same transistors of Liu and the power, data, and gate lines, initialization, light emission control, and reset control signal lines, pixel circuit, and metal wires of Xu ‘801; also, it would have been obvious to include the claimed features since it would have been within the general skill of one of ordinary skill in the art to select features on the basis of their suitability for the intended use for higher light transmittance and to simplify manufacturing and reduce manufacturing costs), for higher light transmittance.
Regarding claim 20, Cai as modified by Liu and Xu ‘801 teaches:
The display substrate according to claim 19, wherein a pixel density of the second sub pixels is greater than a pixel density of the first sub pixels, and the pixel density of the second sub pixels is greater than a pixel density of the third sub pixels (Note: this limitation is not treated on the merits as the claim language is met by an alternative limitation as discussed below); or
a pixel density of the second sub pixels is greater than a pixel density of the third sub pixels, and the pixel density of the third sub pixels is greater than a pixel density of the first sub pixels (Note: this limitation is not treated on the merits as the claim language is met by an alternative limitation as discussed below); or
a number of the first display regions is 2 or 3 (Note: this limitation is not treated on the merits as the claim language is met by an alternative limitation as discussed below); or
transmittance of the second display region is lower than transmittance of the transition display region, and the transmittance of the transition display region is lower than transmittance of the at least one first display region (Liu: “[0024]... [T]he light transmittance of the first display area 21 is greater than the light transmittance of the second display area 22... [and] the light transmittance of the second display area 22 is greater than the light transmittance of the third display area 23....”).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to K. Kiyabu whose telephone number is (571) 270-7836. The examiner can normally be reached Monday to Thursday 9:00 A.M. - 5:00 P.M. ET.
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/K. K./
Examiner, Art Unit 2626
/TEMESGHEN GHEBRETINSAE/Supervisory Patent Examiner, Art Unit 2626 7/21/26
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