DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to application 18992572 filed on 01/09/2025. Claims 1-18 are presented for examination.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy of foreign priority document, Application No. CN202211139247.2, filed in China on 09/19/2022, has been received.
Prior Art Rejections
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsujita (US Patent Pub. No. 2016/0343278 A1).
Regarding claim 1, Tsujita teaches a pixel driving circuit (Tsujita, Fig. 3, pixel 400), comprising:
a driving circuit, connected to a first node, a second node and a third node (Tsujita, Fig. 3, drive transistor 401 with gate, drain and source respectively), wherein the driving circuit is configured to provide a driving current using a voltage difference between the second node and the third node in response to a voltage signal at the first node (Tsujita, [0062]-[0063], drive current correspond to signal voltage reflecting a video signal; Tsujita, [0080], a voltage difference can affect current supplied); and
a first control circuit, connected to the second node, a first power supply terminal and an enable signal terminal, wherein the first control circuit is configured to transmit a voltage signal at the first power supply terminal to the second node in response to a signal at the enable signal terminal (Tsujita, Fig. 3, enable transistor 405 under the control of scanning line 425 to supply power supply voltage VTFT).
Regarding claim 2, Tsujita teaches the limitations of claim 1 and further teaches an activation level of the driving circuit has a same polarity as an activation level of the first control circuit (Tsujita, Fig. 3, both 401 and 405 are N-type, i.e., activated by the same activation level).
Regarding claim 3, Tsujita teaches the limitations of claim 1 and further teaches the driving circuit comprises:
a driving transistor, wherein a first electrode of the driving transistor is connected to the second node, a second electrode of the driving transistor is connected to the third node, and a gate of the driving transistor is connected to the first node, the driving transistor is configured to provide the driving current using the voltage difference between the second node and the third node in response to the voltage signal at the first node (Tsujita, Fig. 3, drive transistor 401); and
the first control circuit comprises:
a fifth transistor, wherein a first electrode of the fifth transistor is connected to the second node, a second electrode of the fifth transistor is connected to the first power supply terminal, and a gate of the fifth transistor is connected to the enable signal terminal, the fifth transistor is configured to transmit the voltage signal at the first power supply terminal to the second node in response to the signal at the enable signal terminal (Tsujita, Fig. 3, enable transistor 405).
Regarding claim 4, Tsujita teaches the limitations of claim 3 and further teaches the driving transistor and the fifth transistor are both N-type transistors (Tsujita, Fig. 3, both 401 and 405 are N-type).
Regarding claim 5, Tsujita teaches the limitations of claim 1 and further teaches a first reset circuit, connected to the third node, a third gate signal terminal and a first initial signal terminal, wherein the first reset circuit is configured to transmit a signal at the first initial signal terminal to the third node in response to a signal at the third gate signal terminal (Tsujita, Fig. 3, initialization transistor 407);
a second reset circuit, connected to the first node, a second initial signal terminal and a second gate signal terminal, wherein the second reset circuit is configured to transmit a signal at the second initial signal terminal to the first node in response to a signal at the second gate signal terminal (Tsujita, Fig. 3, reference transistor 406);
a data writing circuit, connected to the first node, a first gate signal terminal and a data signal terminal, wherein the data writing circuit is configured to transmit a signal at the data signal terminal to the first node in response to a signal at the first gate signal terminal (Tsujita, Fig. 3, selection transistor 404); and
a coupling circuit, connected between the first node and the third node (Tsujita, Fig. 3, holding capacitor element 403).
Regarding claim 6, Tsujita teaches the limitations of claim 5 and further teaches the first reset circuit comprises:
a fourth transistor, wherein a first electrode of the fourth transistor is connected to the first initial signal terminal, a second electrode of the fourth transistor is connected to the third node, a gate of the fourth transistor is connected to the third gate signal terminal, and the fourth transistor is configured to transmit the signal at the first initial signal terminal to the third node in response to the signal at the third gate signal terminal (Tsujita, Fig. 3, initialization transistor 407);
the second reset circuit comprises:
a second transistor, wherein a first electrode of the second transistor is connected to the second initial signal terminal, a second electrode of the second transistor is connected to the first node, a gate of the second transistor is connected to the second gate signal terminal, and the second transistor is configured to transmit the signal at the second initial signal terminal to the first node in response to the signal at the second gate signal terminal (Tsujita, Fig. 3, reference transistor 406);
the data writing circuit comprises:
a first transistor, wherein a first electrode of the first transistor is connected to the data signal terminal, a second electrode of the first transistor is connected to the first node, a gate of the first transistor is connected to the first gate signal terminal, and the first transistor is configured to transmit the signal at the data signal terminal to the first node in response to the signal at the first gate signal terminal (Tsujita, Fig. 3, selection transistor 404); and
the coupling circuit comprises:
a storage capacitor, wherein a first electrode of the storage capacitor is connected to the first node, and a second electrode of the storage capacitor is connected to the third node (Tsujita, Fig. 3, holding capacitor element 403).
Regarding claim 7, Tsujita teaches the limitations of claim 6 and further teaches the fourth transistor, the second transistor and the first transistor are all N-type transistors (Tsujita, Fig. 3, 407, 406 and 404 are N-type).
Regarding claim 8, Tsujita teaches the limitations of claim 1 and further teaches a method for driving the pixel driving circuit according to any one of claim 1, comprising:
in a light-emitting stage, providing an activation level signal with a preset duty cycle to the enable signal terminal to control a preset duration of activation of the first control circuit, transmitting the signal at the first power supply terminal to the second node by the first control circuit, and controlling the driving circuit to provide the driving current by using the voltage difference between the second node and the third node (Tsujita, Fig. 8, when scanning line 425 is active).
Regarding claim 9, Tsujita teaches the limitations of claim 5 and further teaches a method for driving the pixel driving circuit according to claim 5, comprising:
in an initialization stage, transmitting the signal at the first initial signal terminal to the third node by the first reset circuit, and transmitting the signal at the second initial signal terminal to the first node by the second reset circuit (Tsujita, [0072]-[0081], initialization period);
in a data writing stage, transmitting the signal at the data signal terminal to the first node by the data writing circuit (Tsujita, [0072]-[0081], writing period); and
in a light-emitting stage, controlling the first control circuit to be activated for a preset duration, transmitting the signal at the first power supply terminal to the second node by the first control circuit, and controlling the drive circuit to provide the driving current by using the voltage difference between the second node and the third node (Tsujita, [0072]-[0081], light-emitting period).
Allowable Subject Matter
Claims 10-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 10-18, the prior art, whether considered alone or in combination, fail to disclose the technical features of the claimed invention in context as a whole. Specifically, the arrangement of the different active layers in the manner claimed as a whole, is not sufficiently taught or suggested in the prior art.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
U.S. Patent Publication No. 2008/0238955 A1 to Yamashita et al. discloses a similar invention as recited, specifically the pixel structure with enable circuit and reset circuit, see Fig. 2.
U.S. Patent Publication No. 2016/0133185 A1 to Yoon et al. discloses a similar invention as recited, specifically the pixel structure with enable circuit and reset circuit, see Fig. 2.
U.S. Patent Publication No. 2017/0092199 A1 to Park et al. discloses a similar invention as recited, specifically the pixel structure with enable circuit and reset circuit, see Fig. 2.
U.S. Patent Publication No. 2019/0035322 A1 to Kim et al. discloses a similar invention as recited, specifically the pixel structure with enable circuit and reset circuit, see Fig. 2.
U.S. Patent Publication No. 2022/0208094 A1 to Jang et al. discloses a similar invention as recited, specifically the pixel structure with enable circuit and reset circuit, see Fig. 2.
U.S. Patent Publication No. 2023/0386376 A1 to Kim discloses a similar invention as recited, specifically the pixel structure with enable circuit and reset circuit, see Fig. 3.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DONG HUI LIANG whose telephone number is (571)272-0487. The examiner can normally be reached M-F 7am-3pm EST.
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/DONG HUI LIANG/Primary Examiner, Art Unit 2629