DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 4, the phrase “a second electrode” is unclear because it implies the presence of a first electrode included with the semiconductor layer; however, the claims lack antecedent basis for a first electrode and only claim a connecting electrode as included with the semiconductor layer, thus resulting in a lack of clarity. The claim will be treated on its merits assuming that the connecting electrode is intended to be the first electrode of the semiconductor layer. Appropriate correction is required.
Claims 5-6 are rejected based on their dependence from claim 4.
Regarding claim 5, the phrase “second interval” and “third interval” are unclear because they imply the presence of a first interval; however, the claims lack antecedent basis for a first interval. The claim will be treated on its merits assuming that the connecting electrode is intended to be the first electrode of the semiconductor layer. Appropriate correction is required.
Claim 6 is rejected based on their dependence from claim 5.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4, and 37 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Jeong et al. (US 2017/0322471).
Regarding claim 1, Jeong discloses (Figs. 1-9) a display substrate, comprising an array substrate and a color filter substrate (110 & 210; Paragraphs [0045, 0082]); wherein the array substrate includes: a first substrate (110; Paragraph [0045]); a first conductive layer disposed on a side of the first substrate, and including at least one first signal line and a first pattern that are spaced apart (DL & SL2; Paragraph [0045]); a first insulating layer disposed on a side of the first conductive layer away from the first substrate (120; Paragraph [0045]); a first via hole at least penetrating the first insulating layer and exposing at least a portion of the first signal line (CNT1; Paragraph [0099]); a semiconductor layer disposed on a side of the first insulating layer away from the first substrate, and including a semiconductor pattern (GE & GL & 116 & SM; Paragraph [0045, 0126]); wherein the semiconductor pattern includes a first portion, a second portion and a channel structure located between the first portion and the second portion (GE & GL & 116 & SM; Paragraph [0045, 0126]); an orthogonal projection of the first portion on the first substrate partially overlaps with an orthogonal projection of the first signal line on the first substrate (Fig. 2, GE & GL & DL; Paragraph [0045]), and an orthogonal projection of the channel structure on the first substrate is located within a range of an orthogonal projection of the first pattern on the first substrate (Fig. 2, SM & SL2; Paragraph [0060]); and a connecting electrode disposed on a side of the semiconductor layer away from the first substrate (SE & BE1; Paragraph [0075]); at least a portion of the connecting electrode being located in the first via hole and connected to the first portion and the first signal line (Fig. 4, BE1 & SE & DL & CNT1).
Regarding claim 4, Jeong further discloses wherein the semiconductor layer further includes a second electrode connected to the second portion and integrally disposed with the second portion (DE; Paragraph [0060]).
Regarding claim 37, Jeong further discloses wherein and a driving circuit board electrically connected to the display substrate, and configured to transmit a control signal to the display substrate (Paragraph [0006]—Note it is considered characteristic to an LCD display with TFT control structure to have a driving circuit board connected to the display substrate that transmits a control signal to the display substrate in order to make the display function).
Allowable Subject Matter
Claims 2, 8-9, 13-16, 21-23, 26-28, and 30-31 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Specifically, in claim 2, the prior art of record neither teaches nor suggests the requirement wherein an orthogonal projection of the first electrode on the first substrate covers the orthogonal projection of the first signal line on the first substrate; or the array substrate further includes the first electrode: the first electrode is disposed on the side of the film layer where the connecting, electrode is located away from the first substrate, and the orthogonal projection of the first electrode on the first substrate covers the orthogonal projection of the first signal line on the first substrate: and the first electrode includes a first extending segment; an extending direction of the first extending, segment is the same as an extending, direction of the first signal line: an orthogonal projection of the first extending segment on the first substrate covers the orthogonal projection of the first signal line on the first substrate, and there is a first interval between boundaries, proximate to each other, of the orthogonal projections of the first extending, segment and the first signal line on the first substrate; the first interval is in a ranges from 2 µm to 5 µm.
Specifically, in claim 8, the prior art of record neither teaches nor suggests the requirement wherein the first insulating layer includes a first groove portion that is concave in a direction proximate to the first substrate, and at least a portion of the first groove portion is located between the first signal line and the first pattern; the first groove portion includes two first side walls disposed opposite to each other; the first portion includes two first sub-portions covering the two first side walls, and a second sub-portion covering other regions of the first insulating layer; a thickness of the first sub-portion is less than a thickness of the second sub-portion.
Claim 9 is objected to based on its dependence from claim 8.
Specifically, in claim 13, the prior art of record neither teaches nor suggests the requirement wherein the array substrate further includes a planarization layer; the planarization layer is located between the first conductive layer and the first insulating layer, and a surface of the planarization layer away from the first substrate is a flat surface; the planarization layer at least Attorney Docket No. 10406-2409006 covers the first signal line, the first pattern, and an interval between the first signal line and the first pattern; wherein the semiconductor layer further includes a second electrode; the second electrode is connected to the second portion and integrally disposed with the second portion; at least a portion of an orthogonal projection of the second electrode on the first substrate does not overlap with at least a portion of an orthogonal projection of the planarization layer on the first substrate.
Claim 14 is objected to based on its dependence from claim 13.
Specifically, in claim 15, the prior art of record neither teaches nor suggests the requirement wherein the at least one first signal line the first conductive layer includes a plurality of first signal lines; the plurality of first signal lines are disposed at intervals along a first direction and extend along a second direction; the array substrate further includes a plurality of signal line groups; the plurality of signal line groups are arranged at intervals along the second direction and extend along the first direction; the plurality of first signal lines and the plurality of signal line groups intersect each other to form a grid structure; a region where an orthogonal projection of any one of the plurality of signal line groups on the first substrate overlaps with an orthogonal projection of any one of the plurality of first signal lines the first signal line on the first substrate protrudes toward a side away from the first substrate to form a columnar structure; Attorney Docket No. 10406-2409006 the color filter substrate includes at least one spacer; the spacer is in a strip shape and extends along the first direction; an orthogonal projection of the spacer on the array substrate partially overlaps with the first signal line and the signal line group; the signal line group includes a wiring region; a position where at least one of the signal line groups intersects with the first signal line is provided with the wiring region; in the wiring region, the orthogonal projection of the spacer on the array substrate does not overlap with the columnar structure.
Claims 16, 21-23, 26-28, and 30-31 are objected to based on their dependence from claim 15.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANNE M HINES whose telephone number is (571)272-2285. The examiner can normally be reached on M-F: 8:00-4:30.
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/Anne M Hines/
Primary Examiner
Art Unit 2879
Prosecution Insights