DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in China on 06/30/2023.
Information Disclosure Statement
The Information Disclosure Statement has been considered and placed in the record on file and is in compliance with USPTO requirements.
Drawings
The Drawings have been considered and placed in the record on file and are in compliance with USPTO requirements.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 12, 17, 19, and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Han et al. (US 2024/0078971 A1 hereinafter Han).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
In regards to claim 1, Han discloses an array substrate, comprising a substrate and a plurality of pixel circuits disposed on the substrate, wherein the plurality of pixel circuits are arranged in a plurality of rows and a plurality of columns, and a pixel circuit of the plurality of pixel circuits includes a first light-emitting control transistor and a second light-emitting control transistor;
the array substrate further comprises:
a first light-emitting control signal line electrically connected to a gate of the first light-emitting control transistor (see figure 2A, EM1); and
a second light-emitting control signal line electrically connected to a gate of the second light-emitting control transistor (see figure 2A, EM2);
the array substrate further comprises a plurality of conductive layers (see figure 7B), the first light- emitting control signal line and the second light-emitting control signal line are electrically insulated, the first light-emitting control signal line and the second light-emitting control signal line are located in different conductive layers (see paragraph 0094, EM1 is located on an upper side, while EM2 is located on a lower side), and an orthographic projection of the first light- emitting control signal line on the substrate does not overlap with an orthographic projection of the second light-emitting control signal line on the substrate (see figure 6K, EM1 and EM2 do not overlap with each other).
In regards to claim 12, Han discloses a method for driving a pixel circuit, wherein the pixel circuit includes a driving transistor (see figure 2A, T3), a first light-emitting control transistor (see figure 2A, T5), and a second light-emitting control transistor (see figure 2A, T6); a gate of the first light-emitting control transistor is electrically connected to a first light-emitting control signal line (see figure 2A, EM2), a first electrode of the first light-emitting control transistor is electrically connected to a first voltage signal line (see figure 2A, VDD), and a second electrode of the first light- emitting control transistor is electrically connected to a first electrode of the driving transistor (see figure 2A); a gate of the second light-emitting control transistor is electrically connected to a second light- emitting control signal line (see figure 2A, EM1), a first electrode of the second light-emitting control transistor is electrically connected to a second electrode of the driving transistor (see figure 2A), and a second electrode of the second light-emitting control transistor is electrically connected to a light-emitting device (see figure 2A, element 121); the first light-emitting control signal line is configured to transmit a first pulse width modulation signal (see figure 2B), and the second light-emitting control signal line is configured to transmit a second pulse width modulation signal (see figure 2B);
a display cycle includes a light-emitting phase; and the method comprises that: in the light-emitting phase, the first pulse width modulation signal has a first operating level period, the second pulse width modulation signal has a second operating level period, the first operating level period is different from the second operating level period, and the first operating level period partially overlaps with the second operating level period (see figure 2B, EM1 overlaps with EM2).
In regards to claim 17, as recited in claim 12, Han further discloses wherein the first operating level period is within the second operating level period, a start time of the first operating level period and a start time of the second operating level period are spaced apart, and an end time of the first operating level period and an end time of the second operating level period are spaced apart; or the second operating level period is within the first operating level period (see figure 2B, EM1 occurs during part of the time EM2 occurs), the start time of the first operating level period and the start time of the second operating level period are spaced apart (see figure 2B, the start time of EM1 and EM2 are spaced apart), and the end time of the first operating level period and the end time of the second operating level period are spaced apart (see figure 2B, the end time of EM1 and EM2 are spaced apart).
In regards to claim 19, Han discloses a display panel, comprising:
the array substrate according to claim 1 (see rejection above); and a plurality of light-emitting devices disposed on the array substrate, each light- emitting device being electrically connected to a pixel circuit (see figure 4L and paragraph 0168, plurality of pixel circuits).
In regards to claim 20, Han discloses a display apparatus, comprising: the display panel according to claim 19 (see rejection above); and a driver circuit board electrically connected to the display panel and configured to transmit control signals to the display panel (see figures 9 and 2A, display panel 800 with pixel circuits, therefore a driver to supply the control signals).
Allowable Subject Matter
Claims 2-11, 13-16, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER J KOHLMAN whose telephone number is (571)270-5503. The examiner can normally be reached 9-5:30.
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/CHRISTOPHER J KOHLMAN/Primary Examiner, Art Unit 2628