DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to application 18992946 filed on 01/09/2025 Claims 1-20 are presented for examination.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy of foreign priority document, Application No. CN202310789132.6, filed in China on 06/29/2023, has been received.
Prior Art Rejections
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5, 8-11, 13, 14 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang (CN116072044A).
Regarding claim 1, Wang teaches a pixel driving circuit (Wang, Fig. 5, pixel circuit), comprising: a driving transistor (Wang, Fig. 5, Td), a light-emitting device (Wang, Fig. 5, DL), a first reset control sub-circuit (Wang, Fig. 5, 60 and 50), a data writing sub-circuit (Wang, Fig. 5, 20), and a light-emitting control sub-circuit (Wang, Fig. 5, 70 and 80); wherein
a gate of the driving transistor is coupled to a first node, a first electrode of the driving transistor is coupled to a second node, and a second electrode of the driving transistor is coupled to a third node, and the driving transistor is configured to, based on a data voltage, generate a drive current (Wang, Fig. 5, N1, N2 and N3 respectively; Wang, page 16 third paragraph of translation Td provide a drive signal based on the voltage in the nodes);
the first reset control sub-circuit is coupled to the second node and a fourth node, and is configured to reset a level of the second node and a level of the fourth node (Wang, Fig. 5, 60 and 50 are connected to N2 and N4 respectively and provide voltage Init3 and Init2 respectively);
the data writing sub-circuit is coupled to the second node, and is configured to, in response to a signal at a first scanning signal terminal, input the data voltage at a data signal terminal into the first node (Wang, Fig. 5, 20 connected to N2 to provide Data under control of Scan1; Wang, Fig. 9A a driving signal for circuit in Fig. 5, when Scan1 is low, Scan2 is high, SW is low, the path between N1 and N3 is connected and data from N3 to N1); and
the light-emitting control sub-circuit is coupled to the light-emitting device through the driving transistor, and the light-emitting control sub-circuit is configured to provide the drive current generated by the driving transistor to the light-emitting device (Wang, Fig. 5, 80 provided between Td and DL).
Regarding claim 5, Wang teaches the limitations of claim 1 and further teaches a second reset control sub-circuit; wherein
the second reset control sub-circuit is coupled to the first node and the third node, and is configured to reset the first node and the third node (Wang, Fig. 5, 40 to provide Init1 to N1 and N3 via 30).
Regarding claim 8, Wang teaches the limitations of claim 1 and further teaches the data writing sub-circuit comprises: a sixth switching transistor; wherein
a control terminal of the sixth switching transistor is coupled to the first scanning signal terminal, a first terminal of the sixth switching transistor is coupled to the data signal terminal, and a second terminal of the sixth switching transistor is coupled to the second node (Wang, Fig. 5, 20 with T4 connected to Scan1, Data and N2 respectively).
Regarding claim 9, Wang teaches the limitations of claim 1 and further teaches the light-emitting control sub-circuit comprises: a seventh switching transistor; wherein
a control terminal of the seventh switching transistor is coupled to an enable signal terminal, a first terminal of the seventh switching transistor is coupled to the fourth node, and a second terminal of the seventh switching transistor is coupled to the third node (Wang, Fig. 5, 80 with T9 connected to EM, N3 and N4 respectively).
Regarding claim 10, Wang teaches the limitations of claim 1 and further teaches an eighth switching transistor; wherein
a control terminal of the eighth switching transistor is coupled to an enable signal terminal, a first terminal of the eighth switching transistor is coupled to the second node, and a second terminal of the eighth switching transistor is coupled to a first power supply terminal (Wang, Fig. 5, 70 with T8 connected to EM, N2 and VDD respectively).
Regarding claim 11, Wang teaches the limitations of claim 1 and further teaches a first capacitor; wherein a first terminal of the first capacitor is coupled to the first node, and a second terminal of the first capacitor is coupled to a first power supply terminal (Wang, Fig. 5, Cst connected to N1 and VDD respectively).
Regarding claim 13, Wang teaches the limitations of claim 1 and further teaches a display device, comprising: the pixel driving circuit according to claim 1 (Wang, page 1 second paragraph of translation, display device).
Regarding claim 14, Wang teaches the limitations of claim 1 and further teaches a driving method of the pixel driving circuit according to claim1,comprising:
resetting, by the first reset control sub-circuit, the level of the second node coupled to the driving transistor;
inputting, by the data writing sub-circuit, the data voltage at the data signal terminal into the first node coupled to the driving transistor in response to the signal at the first scanning signal terminal;
generating, by the driving transistor, the drive current based on the data voltage; and
providing, by the light-emitting control sub-circuit, the drive current generated by the driving transistor to the light-emitting device (Wang, page 8 fourth paragraph, includes a reset phase, data writing phase and a light emitting phase).
Regarding claim 18, Wang teaches the limitations of claim 5 and further teaches an eighth switching transistor; wherein
a control terminal of the eighth switching transistor is coupled to an enable signal terminal, a first terminal of the eighth switching transistor is coupled to the second node, and a second terminal of the eighth switching transistor is coupled to a first power supply terminal (Wang, Fig. 5, 70 with T8 connected to EM, N2 and VDD respectively).
Allowable Subject Matter
Claims 2-4, 6, 7, 12, 15-17, 19 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 2-4, 15-17 and 20, the prior art, whether considered alone or in combination, fail to disclose the technical features of the claimed invention in context as a whole. Specifically, the respective structures and connections of the components in the first reset control sub-circuit in the manner claimed as a whole, is not sufficiently taught or suggested in the prior art.
Regarding claims 6, 7 and 19, the prior art, whether considered alone or in combination, fail to disclose the technical features of the claimed invention in context as a whole. Specifically, the respective structures and connections of the components in the second reset control sub-circuit in the manner claimed as a whole, is not sufficiently taught or suggested in the prior art.
Regarding claim 12, the prior art, whether considered alone or in combination, fail to disclose the technical features of the claimed invention in context as a whole. Specifically, the use of a double-gate transistor for the light-emitting control sub-circuit and the specific gates connections in the manner claimed as a whole, is not sufficiently taught or suggested in the prior art.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
U.S. Patent Publication No. 2017/0249900 A1 to Xiang et al. discloses a similar invention as recited, specifically providing of reset signal to one of the node of the driving transistor and to a different node at a pixel circuit, see Fig. 4, initialization module 42.
U.S. Patent Publication No. 2023/0290310 A1 to Wang et al. discloses a similar invention as recited, specifically providing of reset signal to one of the node of the driving transistor and to a different node at a pixel circuit, see Fig. 30B, third sub-circuit 31 and second reset sub-circuit 60.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DONG HUI LIANG whose telephone number is (571)272-0487. The examiner can normally be reached M-F 7am-3pm EST.
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/DONG HUI LIANG/Primary Examiner, Art Unit 2629