DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 12 is objected to because of the following informalities:
At Line 5 of Claim 12: the recitation “isa” requires a change to - - is a - - to correct an essentially typographical error.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 5, 7 – 9, 13, 15, and 17 - 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gai et al. (China Patent Document CN 115294940 A (Please see original document provided for Figure references and translation of original document provided for Page and Line references), hereinafter referenced as Gai.
Regarding Claim 1, Gai discloses “A pixel driving circuit” (Figure 3 and Page 7, Lines 8 – 9 (Notice that pixel driving circuit is shown in Figure 3.)), “comprising: a driving transistor” (Figure 3, Item T0, and Page 11, Line 33), “a light-emitting device” (Figure 3, Item 13, and Page 11, Line 13), “a data writing sub-circuit” (Figure 3, Item T1, and Page 11, Line 30 (Notice that T1 is scanned to write a data voltage to the gate of T0.)), “a threshold compensation sub-circuit” (Figure 3, Items C1, T3, and Page 11, Lines 25 and 28 (Notice that first capacitor C1 and transistor T3 form a threshold compensation sub-circuit.)), “and a first light-emitting control sub-circuit” (Figure 3, Item T6, and Page 11, Line 27 (Notice that transistor T6 provides a first light-emitting control subcircuit.)), “wherein the driving transistor is configured to, based on a threshold voltage of the driving transistor and a data voltage, generate a drive current” (Figure 3, Item T0 (Notice that the connection of the driving transistor T0 configures it to generate a drive current based on the threshold voltage of the gate (G) of T0 and data voltage Vdata conveyed from T1.)), “the data writing sub-circuit is coupled to a gate of the driving transistor, and is configured to, in response to a signal at a scanning signal terminal, input the data voltage at a data signal terminal into the gate of the driving transistor” (Figure 3, Item T1 (Notice that T1 provides a data writing subcircuit that is coupled to the gate G of the driving transistor T0 as is configured to input the data voltage at a data signal terminal connected to Vdata to the gate of T0 in response to scanning signal terminal receiving signal S1.)), “the threshold compensation sub-circuit is coupled to the driving transistor, and is configured to, in response to a signal at a compensation signal terminal, provide the threshold voltage of the driving transistor to the gate of the driving transistor” (Figure 3 (Notice that the threshold compensation sub-circuit comprised of C1 and T3 is coupled to driving transistor T0 to provided the threshold voltage to the gate G of TO in response to a compensation signal S3 at a compensation signal terminal.)), “and the first light-emitting control sub-circuit is coupled to the driving transistor, and is configured to, in response to a signal at a control signal terminal, provide the drive current generated by the driving transistor to the light-emitting device” (Figure 3, Items T6 and 13 (Notice that the first light-emitting control sub-circuit T6 is coupled to the driving transistor T and provides drive current to the light-emitting device 13 in response to an emission signal EM at a control signal terminal.)).
Regarding Claim 2, Gai discloses everything claimed as applied above (See Claim 1). In addition, Gai discloses “wherein the threshold compensation sub-circuit comprises a first switching transistor” (Figure 3, Item T3), “and a first capacitor” (Figure 3, Item C1), “wherein a control terminal of the first switching transistor is coupled to the compensation signal terminal, a first terminal of the first switching transistor is coupled to the gate of the driving transistor, and a second terminal of the first switching transistor is coupled to a second electrode of the driving transistor” (Figure 3 (Notice that the gate of first switching transistor T3 is coupled to a compensation terminal to obtain signal S3, a first terminal of T3 is coupled to the gate of driving transistor T0, and a second terminal of T3 is coupled to the second, source (S) electrode of the driving transistor T0.)), “and a first terminal of the first capacitor is coupled to the gate of the driving transistor, and a second terminal of the first capacitor is coupled to the second electrode of the driving transistor” (Figure 3 (Notice that a first terminal of first capacitor C1 is coupled to the gate G of driving transistor T0 and a second terminal of C1 is coupled to the second, source electrode of driving transistor T0.)).
Regarding Claim 3, Gai discloses everything claimed as applied above (See Claim 1). In addition, Gai discloses “wherein the data writing sub-circuit comprises a second switching transistor” (Figure 3, Item T1), “wherein a control terminal of the second switching transistor is coupled to the scanning signal terminal, a first terminal of the second switching transistor is coupled to the data signal terminal, and a second terminal of the second switching transistor is coupled to the gate of the driving transistor” (Figure 3 (Notice that gate control terminal of second switching transistor T1 is coupled to the scanning terminal receiving scanning signal S1, a first terminal of T1 is couples to the terminal receiving data signal Vdata, and a second terminal of T1 is electrically coupled to the gate G of driving transistor T0.)).
Regarding Claim 4, Gai discloses everything claimed as applied above (See Claim 1). In addition, Gai discloses “wherein the first light-emitting control sub-circuit comprises a third switching transistor” (Figure 3, Item T6), “wherein a control terminal of the third switching transistor is coupled to the control signal terminal, a first terminal of the third switching transistor is coupled to a first power supply terminal, and a second terminal of the third switching transistor is coupled to a first electrode of the driving transistor” (Figure 3 (Notice that gate control terminal of the third switching transistor T6 is coupled to the terminal receiving control signal EM, a first terminal of T6 is coupled to terminal supplied with power Vdd, and a second terminal of T6 is coupled to the first, drain electrode of driving transistor T0.)).
Regarding Claim 5, Gai discloses everything claimed as applied above (See Claim 1). In addition, Gai discloses “further comprising: a first reset sub-circuit” (Figure 3, Item T5 (Notice that transistor T5 provides at least part of a first reset sub-circuit.)), “wherein the first reset sub-circuit is coupled to [the] first electrode of the driving transistor” (Figure 3 (Notice that first reset sub-circuit T5 is electrically coupled to the first, drain electrode of driving transistor T0.)), “and is configured to, in response to a signal at a first reset signal terminal, provide a signal at a reference signal terminal to the first electrode of the driving transistor” (Figure 3 (Notice that T5 is configured to, in response to a signal S2 at a first reset signal terminal gate of T5, provide a signal Vref from a reference signal terminal to the first, drain electrode D of T0 via electrical connection.)).
Regarding Claim 7, Gai discloses everything claimed as applied above (See Claim 1). In addition, Gai discloses “further comprising: a second reset sub-circuit’ (Figure 3, Item T2), “wherein the second reset sub-circuit is coupled to the gate of the driving transistor, and is configured to, in response to a signal at a second reset signal terminal, provide an initialization signal at an initialization signal terminal to the gate of the driving transistor” (Figure 3 (Notice that second reset sub-circuit T2 is coupled to the gate of driving transistor T0 and provides an initialization data signal to the gate of T0 in response to a signal S2 applied to a second reset signal terminal at the gate of S2.)).
Regarding Claim 8, Gai discloses everything claimed as applied above (See Claim 7). In addition, Gai discloses “wherein the second reset sub-circuit comprises a fifth switching transistor” (Figure 3, Item T2), “wherein a control terminal of the fifth switching transistor is coupled to the second reset signal terminal, a first terminal of the fifth switching transistor is coupled to the initialization signal terminal, and a second terminal of the fifth switching transistor is coupled to the gate of the driving transistor” (Figure 3 (Notice that a control gate terminal of fifth switching transistor T2 is coupled to a reset signal S2 via a second reset signal terminal, a first terminal of T2 is coupled to the initialization terminal coming from T1, and a second terminal of T2 is coupled to the gate of driving transistor T0.)).
Regarding Claim 9, Gai discloses everything claimed as applied above (See Claim 1). In addition, Gai discloses “wherein a second electrode of the driving transistor is coupled to the light-emitting device and the threshold compensation sub-circuit” (Figure 3 (Notice that second, source electrode of driving transistor T0 is coupled to light-emitting device 13 and the capacitor C1 and transistor T3 making up the threshold compensation sub-circuit.)).
Regarding Claim 13, Gai discloses everything claimed as applied above (See Claim 1). In addition, Gai discloses “wherein the driving transistor is a single-gate transistor or a double-gate transistor” (Figure 3 (Notice that driving transistor T0 has two gates/ is a double-gate transistor.)), “wherein when the driving transistor is the double-gate transistor, a first gate of the driving transistor is coupled to the data writing sub-circuit” (Figure 3 (Notice that a first gate of T0 is coupled to the above described data writing sub-circuit T1.)), “and a second gate of the driving transistor is coupled to a second power supply terminal” (Figure 3 (Notice that the second gate of T0 is electrically coupled to Vref at a second power supply terminal connected to Vref.)).
Regarding Claim 15, Gai discloses everything claimed as applied above (See Claim 1). In addition, Gai discloses “A display device, comprising the pixel driving circuit according to claim 1 (Page 6, Lines 38 – 39 and the argument of claim 1 (Notice that Gai proved a display panel device with the pixel driving circuit described in the argument of Claim 1 above.)).
Regarding Claim 17, Gai discloses everything claimed as applied above (See Claim 2). In addition, Gai discloses “wherein a second electrode of the driving transistor is coupled to the light-emitting device and the threshold compensation sub-circuit” (Figure 3 (Notice that second, source electrode of driving transistor T0 is coupled to light-emitting device 13 and the capacitor C1 and transistor T3 making up the threshold compensation sub-circuit.)).
Regarding Claim 18, Gai discloses everything claimed as applied above (See Claim 3). In addition, Gai discloses “wherein a second electrode of the driving transistor is coupled to the light-emitting device and the threshold compensation sub-circuit” (Figure 3 (Notice that second, source electrode of driving transistor T0 is coupled to light-emitting device 13 and the capacitor C1 and transistor T3 making up the threshold compensation sub-circuit.)).
Regarding Claim 19, Gai discloses everything claimed as applied above (See Claim 4). In addition, Gai discloses “wherein a second electrode of the driving transistor is coupled to the light-emitting device and the threshold compensation sub-circuit” (Figure 3 (Notice that second, source electrode of driving transistor T0 is coupled to light-emitting device 13 and the capacitor C1 and transistor T3 making up the threshold compensation sub-circuit.)).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Gai in view of Chung et al. (United States Patent Application Publication US 2011/0063197 A1), hereinafter referenced as Chung.
Regarding Claim 14, Gai discloses everything claimed as applied above (See Claim 1). In addition, Gai discloses “a first switching transistor in the threshold compensation sub-circuit” (Figure 3, Item T3), “a fourth switching transistor in a first reset sub-circuit in the pixel driving circuit” (Figure 3, Item T5), “and a fifth switching transistor in a second reset sub-circuit in the pixel driving circuit have an N-type polarity” (Figure 3, Item T4 (Notice that each of T3, T5, and T4 are NMOS or n-type polarity.)). However, Gai fails to explicitly disclose wherein “a second switching transistor in the data writing sub-circuit” is an N-type (i.e. where T1 is p-type by circuit symbol) and “a third switching transistor in the first light-emitting control sub-circuit” is an N-type (i.e. where T6 is p-type by circuit symbol).
In a similar field of endeavor, Chung teaches that NMOS or n-type transistors have faster operational speed than PMOS (Paragraph [0061].
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide “a second switching transistor in the data writing sub-circuit” of an N-type and “a third switching transistor in the first light-emitting control sub-circuit” of an N-type because one having ordinary skill in the art would want to increase operational speed over PMOS.
Allowable Subject Matter
Claims 6, 10 - 12, 16, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Note that Claim 12 also requires the Objection made of record above be overcome to place Claim 12 in full condition for allowance.
In the prior art of record, it has been shown to provide for the limitations of Claims 5, 1, 9, and 2 from which Claims 6 (dependent on Claim 5), 11 (dependent upon Claim 9), 10, 12, and 16 (dependent upon Claim 1), and 20 (dependent upon Claim 2) are according dependent. However, it has not been shown in the prior art record to provide for the limitations of Claim 6 in combination with those of Claim 5, the limitations of Claim 11 in combination with those of Claim 9, the limitations of Claims 10, 12, and 16 in individual combination with Claim 1 through respective chains of dependency, and for the limitations of Claim 20 in combination with those of Claim 2.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN M BUTCHER whose telephone number is (571)270-5575. The examiner can normally be reached on Monday – Friday from 6:30 AM to 3:00 PM.
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/BRIAN M BUTCHER/Primary Examiner, Art Unit 2627 February 18, 2026