DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 4 is objected to because of the following informalities:
As to claim 4, the phrase “a pixel driving sub-circuit” in line 8 of the claim should be changed to “the pixel driving sub-circuit”, since “pixel driving sub-circuit” was previously recited in line 2 of claim 4, and line 9 of claim 1. Appropriate correction is required.
As to claim 4, the phrase “a first reset transistor” in line 9 of the claim should be changed to “the first reset transistor”, since “a first reset transistor” was previously recited in lines 2-3 of the claim. Appropriate correction is required.
As to claim 4, the phrase “a data writing transistor” in line 10 of the claim should be changed to “the data writing transistor”, since “a data writing transistor” was previously recited in line 2 of the claim. Appropriate correction is required.
As to claim 4, the phrase “a first lead segment” in lines 10-11 of the claim should be changed to “the first lead segment”, since “a first lead segment” was previously recited in line 15 of claim 1. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 6-9 and 18-19 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Li et al. (US 2023/0180549 A1).
As to claim 1, Li et al. teaches a display panel, comprising a display area ({0054]: display area AA), wherein the display area includes a middle area and two edge areas, and the middle area is located between the two edge areas along a first direction (Fig. 1, middle area of display area AA is located between two edge areas along a horizontal direction);
the display panel further comprising a base substrate (10 in Fig. 5) and a driving circuit layer (20 in Fig. 5) located at a side of the base substrate (10 in Fig. 5);
the driving circuit layer (20 in Fig. 5) including:
a plurality of pixel circuit units arranged in a plurality of rows and a plurality of columns in the display area (Figs. 1 and 4; [0055]: Each of the data lines Da corresponds to a column of sub-pixels in the display panel), and provides a data signal for the column of sub-pixels ([0055]: provides data signal to the data lines Da. Each of the data lines Da corresponds to a column of sub-pixels in the display panel);
one of the plurality of pixel circuit units including at least one pixel driving sub-circuit (Fig. 4; [0057]: large number of sub-pixels P;[0061]}; the pixel driving sub-circuit including a driving transistor ([0061]: driving transistor T1);
a plurality of data writing signal lines ([0055]: data lines Da) located in the display area ([0055]: display area AA provided with data lines Da); the plurality of data writing signal lines (Da in Fig. 1) being arranged along the first direction (direction D2 in Fig. 1) and extending along a second direction (direction D1 in Fig. 1); the second direction (direction D1 in Fig. 1) intersecting the first direction (direction D2 in Fig. 1); one of the plurality of data writing signal data writing signal line being connected to a column of pixel driving sub-circuits (Figs. 1 and 4; [0055]: Each of the data lines Da corresponds to a column of sub-pixels in the display panel and provides a data signal for the column of sub-pixels);
a plurality of data leads (S1 in Fig. 1), wherein one of the plurality of data leads includes a first lead segment (horizontal portion of line S1 in Fig. 1) and a second lead segment (vertical portion of line S1 in Fig. 1);
an end of the first lead segment (horizontal portion of line S1 in Fig. 1) is electrically connected to one of the plurality of data writing signal lines (Da in Fig. 1) located in the edge area (edge area of display AA in Fig. 1), and another end of the first lead segment (horizontal portion of line S1 in Fig. 1) is electrically connected to an end of the second lead segment (vertical portion of line S1 in Fig. 1); the first lead segment (horizontal portion of line S1 in Fig. 1) extends along the first direction (direction D2 in Fig. 1), and the second lead segment (vertical portion of line S1 in Fig. 1) extends along the second direction (direction D1 in Fig. 1); the second lead segment (vertical portion of line S1 in Fig. 1) is located in the middle area (middle area of display AA in Fig. 1);
an orthogonal projection of the second lead segment on the base substrate at least partially overlaps with an orthogonal projection of a first electrode of at least one driving transistor in the at least one pixel driving sub-circuit on the base substrate ([0008]: drive circuit layer on the substrate;[0040]; [0058]: gate trace G is connected to the driving transistor T1 in the pixel circuit to control the operation state of the driving transistor T1;[0060]; Fig. 3 shows drive trace S1 overlaps gate trace G;[0067];[0071]); and
a shielding layer (B in Figs. 2-3), wherein the shielding layer is configured to have a constant voltage signal ([0059]: shield trace B is electrically connected to the constant voltage trace V to ensure a specific voltage on the shield trace B); the shielding layer includes at least one first shielding pattern ([0043]; [0071]: shield trace B);
the first shielding pattern (B in Fig. 3) is located between the first electrode of the driving transistor (G in Fig. 3) and the second lead segment (S1 in Fig. 3;[0040]); an orthogonal projection of the first shielding pattern (B in Figs. 3 and 5) on the base substrate ([0065]: substrate), an orthogonal projection of the first electrode of the driving transistor (G in Fig. 3;[0058]: gate trace G is connected to the driving transistor T1 in the pixel circuit to control the operation state of the driving transistor T1.;[0067]: any one of the first gate trace G1 and the second gate trace G2 corresponds to the gate trace G in Fig. 5) on the base substrate ([0065]: substrate), and the orthogonal projection of the second lead segment on the base substrate overlap (Fig. 3 shows shielding trace B, gate trace G and drive trace S1 overlap; [0040]; [0052]; [0060];[0067];[0071]).
As to claim 2, Li et al. teaches the display panel according to claim 1, wherein the orthogonal projection of the first shielding pattern (B in Fig. 3) on the base substrate covers the orthogonal projection of the first electrode of the driving transistor (G in Fig. 3;[0058]: gate trace G is connected to the driving transistor T1 in the pixel circuit to control the operation state of the driving transistor T1)
on the base substrate ({0033];[0065]).
As to claim 3, Li et al. teaches the display panel according to claim 1, wherein along the first direction (horizontal direction in Fig. 3), the second lead segment (S1 in Fig. 3;[0040];[0060]) and the first shielding pattern (B in Fig. 3;[0059]) are located at a same side of a gate of the driving transistor (G in Fig. 3; [0058]).
As to claim 6, Li et al. teaches the display panel according to claim 1, wherein the pixel circuit unit includes two pixel driving sub-circuits arranged along the first direction ([0075]: first sub-pixel P1 and second sub-pixel P2, Fig. 6), and the two pixel driving sub-circuits are a first pixel driving sub-circuit and a second pixel driving sub-circuit, respectively ([0075]: first sub-pixel P1 and second sub-pixel P2, Fig. 6);
the second lead segment (S1 in Fig. 6) corresponding to the first pixel driving sub-circuit (P1 in Fig. 6) is adjacent to the second lead segment (S1 in FIg. 6) corresponding to the second pixel driving sub-circuit (P2 in Fig. 6); and
a first shielding pattern (B in Fig. 6) in the first pixel driving sub-circuit (P1 in Fig. 6) is disposed adjacent to a first shielding pattern (B in Fig. 6) in the second pixel driving sub-circuit (P2 in Fig. 6).
As to claim 7, Li et al. teaches the display panel according to claim 6, wherein the first shielding pattern (B in Fig. 6) in the first pixel driving sub-circuit (P1 in Fig. 6) is electrically connected to the first shielding pattern (B in Fig. 6) in the second pixel driving sub-circuit (P2 in Fig. 6; Fig. 1 shows data lines Da connected to driving chip IC through drive traces S1; Fig. 4 shows driving transistor T1 connected to data line Da;[0061]: A source and a drain of the drive transistor T1 are electrically connected to the constant voltage trace V;[0066]: the shield trace B is electrically connected to the constant voltage trace V), and the first shielding pattern (B in Fig. 6) in the first pixel driving sub- circuit (P1 in Fig. 6) is disposed in the same layer as the first shielding pattern (B in Fig. 6) in the second pixel driving sub- circuit (P2 in Fig. 6; [0064]: shield traces B on shield layer;[0067]) .
As to claim 8, Li et al. teaches the display panel according to claim 6, wherein the first pixel driving sub-circuit (P1 in Fig. 6) and the second pixel driving sub-circuit (P2 in Fig. 6) are symmetrical along the first direction (direction D2 in Fig. 6).
As to claim 9, Li et al. teaches the display panel according to claim Lany one of claim 1, wherein an orthogonal projection of the first lead segment (S1 in Fig. 5) on the substrate (10 in Fig. 5) partially overlaps with an orthogonal projection of the data writing signal line (Da in Fig. 5) on the substrate (10 in Fig. 5); the shielding layer further includes at least one second shielding pattern (B in Fig. 5); the second shielding pattern (B in Fig. 5) is located between the first lead segment (S1 in Fig. 5) and the data writing signal line (Da in Fig. 5); an orthogonal projection of the second shielding pattern (B in Fig. 5) on the base substrate (10 in Fig. 5), the orthogonal projection of the first lead segment (S1 in Fig. 5) on the base substrate(10 in Fig. 5), and the orthogonal projection of the data writing signal line (Da in Fig. 5) on the base substrate overlap (10 in Fig. 5).
As to claim 18, Li et al. teaches the display panel according to claim 1, further comprising a bonding area (non-display area NA in Fig. 1); the bonding area (non-display area NA in Fig. 1) being located at a side of the display area (display area AA in Fig. 1); the bonding area including a connecting lead (portion of trace S1 directly connecting IC in non-display area NA), and a predetermined end of the data lead (portion of trace S1 in the display area AA) being electrically connected to the connecting lead (portion of trace S1 directly connecting IC in non-display area NA).
As to claim 19, Li et al. teaches a display device ([0002];[0006]: display), comprising the display panel according to claim 1 (see rejection for claim 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 2023/0180549 A1) in view of Song et al. (US 2022/0198968 A1).
As to claim 4, Li et al. teaches the display panel according to claim 1, wherein the pixel
driving sub-circuit further includes a data writing transistor (T2 in Fig. 4); a first electrode of the data writing transistor (T2 in Fig. 4) is electrically connected to one of the plurality of data writing signal lines (Da in Fig. 4), a second electrode of the data writing transistor (T2 in Fig. 4) is electrically connected to the first electrode of the driving transistor (T1 in Fig. 4); but does not explicitly disclose a first reset transistor; a first electrode of the first reset transistor is electrically connected to a gate of the driving transistor; along the second direction, in a pixel driving sub-circuit of one of the plurality of pixel circuit units, a first reset transistor is located at a side of a data writing transistor away from the driving transistor, and at least a portion of a first lead segment extending through the same pixel circuit unit is located at a side of the first reset transistor away from the data writing transistor.
However, Song et al. teaches a first reset transistor (T4 in Fig. 9); a first electrode of the first reset transistor (T4 in Fig. 9) is electrically connected to a gate of the driving transistor (T1 in Fig. 9); along the second direction (vertical direction in Figs. 9 and 11), in a pixel driving sub-circuit of one of the plurality of pixel circuit units ([0075]: pixels), a first reset transistor (T4 in Fig. 9; T4_1 in Fig. 11) is located at a side of a data writing transistor (T2 in Figs. 9 and 11) away from the driving transistor (T1 in Figs. 9 and 11); and at least a portion of a first lead segment (BR1_A in Fig. 11) extending through the same pixel circuit unit is located at a side of the first reset transistor (T4_1 in Fig. 11) away from the data writing transistor (T2 in Fig. 11).
It would have been obvious to one of ordinary skill in the art before the effective filing
date of the claimed invention to modify the device of Li et al. with a first reset transistor
electrically connected to a gate of the driving transistor, wherein along the second direction, in
a pixel driving sub-circuit of one of the plurality of pixel circuit units, a first reset transistor is
located at a side of a data writing transistor away from the driving transistor, and at least a
portion of a first lead segment extending through the same pixel circuit unit is located at a side
of the first reset transistor away from the data writing transistor as taught by Song et al. in
order to optimize space utilization of the display.
Claim(s) 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 2023/0180549 A1) in view of Liang et al. (CN 102751200 A, attached English machine translation is used in the current rejection).
As to claim 10, Li et al. teaches the display panel according to claim 1, wherein the driving circuit layer further includes a first gate metal layer ([0077]: metal layer of trace Z), a second gate metal layer ([0067]: metal layer of shield trace B), a first wiring metal layer (horizontal portion of S1 in Fig. 1:[0067]: metal layer of drive trace S1), and a second wiring metal layer (vertical portion of S1 in Fig. 1) stacked on the base substrate ([0065]: substrate);
the first lead segment is located in the first wiring metal layer (horizontal portion of S1 in Fig. 1:[0067]: metal layer of drive trace S1), and the second lead segment is located in the second wiring metal layer (vertical portion of S1 in Fig. 1:[0067]: metal layer of drive trace S1); the first shielding pattern is located in the second gate metal layer and/or the first wiring metal layer ([0067]: metal layer of shield trace B), but does not explicitly disclose a first semiconductor layer, the first electrode of the driving transistor is located in the first semiconductor layer.
However, Liang et al. teaches a first semiconductor layer, the first electrode of the driving transistor is located in the first semiconductor layer (Abstract: use of polysilicon as gate electrode).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Li et al. with a first semiconductor layer, the first electrode of the driving transistor is located in the first semiconductor layer as taught by Liang et al. in order to reduce leakage current.
As to claim 11, Li et al. teaches the display panel according to claim of claims wherein the driving circuit layer further includes a first gate metal layer ([0077]: metal layer of trace Z), a second gate metal layer ([0067]: metal layer of shield trace B), a first wiring metal layer (horizontal portion of S1 in Fig. 1: [0067]: metal layer of drive trace S1), a second wiring metal layer ([0067]: metal layer of constant voltage trace V), and a third wiring metal layer (vertical portion of S1 in Fig. 1:[0067]: metal layer of drive trace S1) stacked on the base substrate ([0065]: substrate);
the first lead segment is located in the first wiring metal layer (horizontal portion of S1 in Fig. 1: [0067]: metal layer of drive trace S1), and the second lead segment is located in the third wiring metal layer (vertical portion of S1 in Fig. 1:[0067]: metal layer of drive trace S1);
the first shielding pattern is located in at least one of the second gate metal layer, the first wiring metal layer, and the second wiring metal layer ([0067]: metal layer of shield trace B; note that paragraph [0056] of applicant’s specification discloses “the phrase "at least one of A, B, and C" has the same meaning as the phrase "at least one of A, B, or C”), but does not explicitly disclose a first semiconductor layer, the first electrode of the driving transistor is located in the first semiconductor layer.
However, Liang et al. teaches a first semiconductor layer, the first electrode of the driving transistor is located in the first semiconductor layer (Abstract: use of polysilicon as gate electrode).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Li et al. with a first semiconductor layer, the first electrode of the driving transistor is located in the first semiconductor layer as taught by Liang et al. in order to reduce leakage current.
Allowable Subject Matter
Claims 5, and 12-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STACY KHOO whose telephone number is (571)270-3698. The examiner can normally be reached Mon-Fri 8:00 am-5:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached at 571-270-7230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STACY KHOO/Primary Examiner, Art Unit 2624
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