The present application is being examined under the pre-AIA first to invent provisions.
Detailed Action
Current Status of Claims
This action is issued in response to communication of January 12, 2025. By preliminary amendment of January 12, 2025, the Applicant amended claims 5, 7, 8, 12, 13, 14, 16, 17, 18, 20-23 and canceled claims 6, 15, and 19. Therefore, claims 1-5, 7-14, 16-18, and 20-23 are currently active in the application.
Allowable Subject Matter
Claims 7-13, 16-18, and 20-22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Specifically, the prior art of the record does not show the limitation “the flip-flop circuit, wherein the input control sub-circuit comprises a first transistor; the duty ratio adjustment module comprises a third transistor, a first capacitor and a second capacitor; the control module comprises a
fourth transistor; the first transistor has the same switching characteristics as the third
transistor, and switching characteristics of the third transistor and switching characteristics of the fourth transistor are opposite to each other; a control electrode of the first transistor is connected to an input control signal terminal, a first electrode of the first transistor is connected to the first power supply voltage terminal, and a second electrode of the first transistor is connected to the first input terminal; a control electrode of the third transistor is electrically connected to the first node and a first terminal of the second capacitor, a first electrode of the third transistor is connected to a second power supply voltage terminal and a second terminal of the second capacitor, and a second electrode of the third transistor is connected to a first terminal of the first capacitor and the first input terminal of the AND gate; and a second terminal of the first capacitor is connected to the first power supply voltage terminal or the second power supply voltage terminal; and a control electrode of the fourth transistor is connected to a data voltage control signal terminal, a first electrode of the fourth transistor is connected to the first power supply voltage terminal, and a second electrode of the fourth transistor is connected to the first node.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-5, 14, and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoon et al. (US Patent Publication Application 2009/0085624 A1) in view of Shigeta et al. (US Patent Publication Application 2020/0265777 A1).
In regard of claim 1, Yoon et al. disclose a flip-flop circuit, comprising: an AND gate having a first input terminal, a second input terminal, and an output terminal, wherein the AND gate is configured to control the output terminal to output a clock signal based on potentials at the first input terminal and the second input terminal, and a potential of the clock signal jumps between a first power supply voltage and a second power supply voltage (See Figures 3, 4 of Yoon et al. illustrating a flip-flop circuit (310) with AND gate (314) and second input terminal (CLK) for controlling the output terminal and potential of the clock signal jumps between a first power supply voltage (VDD) and second power supply voltage (VSS) as discussed in paragraphs [0031-0035] of Yoon et al.); an input control sub-circuit configured to transmit the first power supply voltage or the second power supply voltage to at least one of the first input terminal and the second input terminal in response to an input control signal (See Figures 3 and 4 of Yoon et al. illustrating an input control sub-circuit (412) configured to transmit the first power supply voltage (VDD) to the first terminal as discussed in paragraph [0042-0043]); and a duty cycle adjustment sub-circuit configured to adjust a duty cycle of the clock signal in response to a data voltage control signal (See Figures 3, 4 of Yoon et al. illustrating duty cycle (312) adjustment/modulation in response to data voltage control signal (VDD) as discussed in paragraphs [0031-0033] of Yoon et al.).
However, the reference to Yoon et al. does not specifically illustrate a data voltage control signal in response to which the duty cycle adjustment sub-circuit adjusts a duty cycle of the clock signal.
In the same field of endeavor, Shigeta et al. discloses a plurality of pixels including a duty cycle adjustment sub-circuit (120) which adjusts a duty cycle of the clock signal in response to a data voltage control signal (Vdata(m), PWM) as shown in Figures 6A-6B and discussed in paragraphs [0124-0128] of Shigeta et al.
Therefore, it would be obvious for a person skilled in the art at the moment the invention was filed to use the data voltage control signal as shown by Shigeta et al. with the device of Yoon et al. in order to setting the clock data voltage and a light emitting period in which the light emitting element emits light during a duration adjusted according to a data voltage control signal.
In regard of claim 2, Yoon et al. and Shigeta et al. further disclose the flip-flop circuit of claim 1, wherein the duty cycle adjustment sub-circuit comprises a control module and a duty cycle adjustment module (See Figures 3-4 of Yoon et al. illustrating duty cycle adjustment sub-circuit (312) including a control module (410) and dusty cycle adjustment circuit (430) as discussed in paragraph [0040-0041] of Yoon et al.); and a connection node connected between the control module and the duty ratio adjustment sub-circuit is a first node (See Figures 3-4 of Yoon et al. illustrating a connection node between the control module (410) and duty ration adjustment (430) as discussed in paragraph [0040]); the control module is configured to control a potential at the first node through the first power supply voltage or the second power supply voltage in response to the data voltage control signal (See Figures 3-4 of Yoon et al. and Figure 6A of Shigeta et al. illustrating the control module (410) controls a potential at the first node through the first power supply voltage (Vdd) as discussed in paragraph [0040-0041] of Yoon et al. and data voltage control signal (Vdata (m)); and the duty cycle adjustment module is configured to adjust the duty cycle of the clock signal output by the output terminal based on the potential at the first node (See Figure 3 of Yoon et al. illustrating the duty cycle (312, 332) adjust the duty cycle of the clock signal (CLK) based on potential on the first node)
In regard of claim 3, Yoon et al. and Shigeta et al. further disclose the flip-flop circuit of claim 2, further comprising a reset sub-circuit configured to respond to a reset signal and reset the first node by the reset signal (See Figure 3 of Yoon et al. illustrating a reset sub-circuit (312, 332) responding to a reset signal (RST1, RST2) as discussed in paragraphs [0033-0034] of Yoon et al.).
In regard of claim 4, Yoon et al. and Shigeta et al. further disclose the flip-flop circuit of claim 3, wherein the reset sub-circuit comprises a second transistor, and
a control electrode of the second transistor is connected to a first electrode of the second transistor and a reset signal terminal, and a second electrode of the second transistor is connected to the first node (See Figure 4 of Yoon et al. illustrating the reset sub-circuit (414) comprising a second transistor (PM2) connected to reset terminal (RST1) and a first node as discussed in paragraph [0039] of Yoon et al.).
In regard of claim 5, Yoon et al. and Shigeta et al. further disclose the flip-flop circuit of claim 3, wherein the first input terminal of the AND gate is electrically connected to a first power supply voltage terminal through the input control sub-circuit, and the second input terminal of the AND gate is directly connected to the first power supply voltage terminal; and the duty ratio adjustment module is connected to the first input terminal of the AND gate, or the first input terminal and the second input terminal of the AND gate are connected to a first power supply voltage terminal through the input control sub-circuit (See Figures 3-4 of Yoon et al. illustrating the first input terminal connected to AND gate (314) and first power supply (Vdd) and the duty ratio adjustment circuit (312) connected to AND gate (314) and first power supply (Vdd) ).
In regard of claim 14, Yoon et al. and Shigeta et al. further disclose the flip-flop circuit of claim 3, wherein the first input terminal of the AND gate is electrically connected to a second power supply voltage terminal through the input control sub-circuit, and the second input terminal of the AND gate is directly connected to a first power supply voltage terminal; and the duty ratio adjustment module is electrically connected to the first input terminal of the AND gate, or the first input terminal and the second input terminal of the AND gate are electrically connected to a second power supply voltage terminal through the input control sub-circuit (See Figures 3-4 of Yoon et al. illustrating AND gate (314) connected to the second power supply (Vss) and to first power supply (Vdd) and the duty ration adjustment module (312) as discussed in paragraphs [0032-0037]).
In regard of claim 23, Yoon et al. and Shigeta et al. further disclose a pixel driving circuit, comprising a driving transistor and the flip-flop circuit of claim 1; wherein a control electrode of the driving transistor is connected to the flip-flop circuit (See Figure 14A of Shigeta et al. illustrating a pixel driving circuit with a driving transistor (Td) with a control electrode connected to the flip-flop circuit (120) as discussed in paragraph [0185]).
Conclusion
The prior art made of record on form PTO-892 and not relied upon is considered pertinent to Applicant’s disclosure. Applicant is required under 37 C.F.R. 1.111 (c ) to consider these references fully when responding to this action.
US Patent Publication Application 2023/0006550 A1 to Screenivas et al.
US Patent Publication Application 2022/0102293 A1 to Poon et al.
Examiner’s Note: Examiner has cited particular columns, line numbers, and figures in the references as applied to the claims above for the convenience of the Applicant. Although the specified citations are representative of the teaching of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Olga V. Merkoulova whose telephone number is ((571)270-7796. The examiner can normally be reached on Mon-Fri. from 7:30-5:00.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's Supervisor, LunYi Lao can be reached on (571) 272-7671. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/OLGA V MERKOULOVA/Primary Examiner, Art Unit 2621