Detailed Action
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
2. Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Claim Rejections - 35 USC § 112
3. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. — The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
4. Claims 15 and 17 are rejected under 35 U.S.C. 112(b) (pre-AIA 35 U.S.C. 112, second paragraph), as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 15 depends on claim 1 and recites the limitations “the common voltage line”, “the first conductive connection structures”, “the first portion”, “the second portion”, and “the first conductive connection structure”. Claim 17 depends on claim 1 and recites the limitation “the common voltage line” and “the second conductive connection structure”. There is insufficient antecedent basis for each of the limitations. To the best of examiner understanding, claim 15 and claim 17 depend on claim 14, respectively.
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 1-3, 5, 7, and 24-25 are rejected under 35 U.S.C. 103 as unpatentable over WU (CN 111599826 A) in view of LEE (US 20060081850 A1).
Regarding claim 1, WU (e.g., Figs. 3-4) discloses a display substrate, comprising: a base substrate (array substrate 200) comprising an active display region (display area AA) and a dummy region (dummy area DU), wherein the dummy region comprises at least one first dummy sub-region arranged in a first direction together with the active display region (dummy area DU and display area AA arranged in a X direction); a plurality of active gate lines in the active display region and extending along the first direction (gate lines 241 extending along X direction), wherein at least one end of at least one active gate line each extends into a first dummy sub-region of the at least one first dummy sub- region on the same side as the end (left end of a gate line 241 extending into dummy area DU); and at least one dummy data line within the at least one first dummy sub- region and extending along a second direction, wherein the first direction intersects with the second direction (dummy data line 26a extending along Y direction, X direction intersects with Y direction); wherein an orthographic projection of an end of the at least one active gate line in the first dummy sub-region on the base substrate does not overlap with an orthographic projection of any dummy data line on the base substrate (an orthographic projection of an end of the gate line 241 in the dummy region DU on the base substrate 200 does not overlap with an orthographic projection of dummy data line 26a on the base substrate 200).
WU does not disclose the dummy region surrounding the active display region. However, LEE (Figs. 1 and 3) discloses a display device, comprising an active display region (Fig. 3; display area including display pixels PX) and a dummy region surrounding the active display region (Fig. 3; dummy area including dummy data lines L1 and L2 surrounding the display pixel area). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the signal line arrangement as taught from WU to the display panel of LEE or incorporate the teaching of LEE to the display panel of WU. The combination/motivation would be to prevent electrical short circuit between signal lines.
Regarding claim 2, WU in view of LEE discloses the display substrate of claim 1, LEE (e.g., Fig. 3) discloses wherein the dummy region comprises two first dummy sub-regions on two opposite sides of the active display region in the first direction, respectively (Fig. 3; dummy region comprises two dummy sub-regions on two opposite sides of the display pixel region in the first direction, the first dummy sub-region comprising dummy data line L1, and the second dummy sub-region comprising dummy data line L2); and two ends of each of the at least one active gate line extend into the two first dummy sub-regions at the two opposite sides corresponding to the two ends, respectively (Fig. 3; each gate line G extend into the two dummy sub-regions dummy data lines L1 and L2 at the two opposite sides corresponding to the two ends).
Regarding claim 3, WU in view of LEE discloses the display substrate of claim 1, WU (e.g., Fig. 3) discloses wherein the end of each of the at least one active gate line extending to the corresponding first dummy sub-region is on a side of one dummy data line, farthest from the active display region in the first dummy sub-region where the end is located, away from the active display region (e.g., Fig. 3; arrangement of gate line 241 and dummy data line 26a).
Regarding claim 5, WU in view of LEE discloses the display substrate of claim 1, LEE (e.g., Fig. 3) discloses wherein the dummy region comprises two first dummy sub-regions on two opposite sides of the active display region in the first direction (Fig. 3; dummy region comprises two dummy sub-regions on two opposite sides of the display pixel region in the first direction, the first dummy sub-region comprising dummy data line L1, and the second dummy sub-region comprising dummy data line L2), respectively, the base substrate further comprises a peripheral region surrounding the dummy region and comprising: two first peripheral sub-regions, each of which is on a side of a corresponding one of the two first dummy sub-regions away from the active display region (Figs. 1 and 3; peripheral region comprises two peripheral sub-regions on two opposite sides of the display pixel region and surrounding the dummy region, two peripheral sub-regions including one gate driver 401 or 402, respectively), and the display substrate further comprises a first gate driving circuit and a second gate driving circuit in the two first peripheral sub-regions, respectively (gate driver 401 and gate driver 402); the plurality of active gate lines in the active display region comprise: a plurality of first gate lines and a plurality of second gate lines alternately arranged along the second direction (odd-numbered gate lines G1, G3, G5, … G2n+1 and even-numbered gate lines G2, G4, G6, … G2n); an end of each first gate line close to the first gate driving circuit is on a side of one dummy data line, farthest from the active display region in the first dummy sub-region where the end is located, away from the active display region, and the first gate line is connected to a corresponding driving signal output terminal in the first gate driving circuit (odd-numbered gate lines G1, G3, G5, … G2n+1 connected to gate driver 401, two dummy sub-regions on two opposite sides of the display pixel region, the first dummy sub-region comprising dummy data line L1, and the second dummy sub-region comprising dummy data line L2); and an end of each second gate line close to the second gate driving circuit is on a side of one dummy data line, farthest from the active display region in the first dummy sub-region where the end is located, away from the active display region, and the second gate line is connected to a corresponding driving signal output terminal in the second gate driving circuit (even-numbered gate lines G2, G4, G6, … G2n connected to gate driver 402, two dummy sub-regions on two opposite sides of the display pixel region, the first dummy sub-region comprising dummy data line L1, and the second dummy sub-region comprising dummy data line L2).
Regarding claim 7, WU in view of LEE discloses the display substrate of claim 1, LEE (e.g., Fig. 3) discloses wherein the dummy region comprises two first dummy sub-regions on two opposite sides of the active display region in the first direction (Fig. 3; dummy region comprises two dummy sub-regions on two opposite sides of the display pixel region in the first direction, the first dummy sub-region comprising dummy data line L1, and the second dummy sub-region comprising dummy data line L2), respectively, the base substrate further comprises a peripheral region surrounding the dummy region and comprising: two first peripheral sub-regions, each of which is on a side of a corresponding one of the two first dummy sub-regions away from the active display region (Figs. 1 and 3; peripheral region comprises two peripheral sub-regions on two opposite sides of the display pixel region and surrounding the dummy region, two peripheral sub-regions including one gate driver 401 or 402, respectively), and the display substrate further comprises a first gate driving circuit and a second gate driving circuit in the two first peripheral sub-regions, respectively (gate driver 401 and gate driver 402); an end of each active gate line close to the first gate driving circuit is on a side of one dummy data line, farthest from the active display region in the first dummy sub-region where the end is located, away from the active display region, and the active gate line is connected to a corresponding driving signal output terminal in the first gate driving circuit (odd-numbered gate lines G1, G3, G5, … G2n+1 connected to gate driver 401, two dummy sub-regions on two opposite sides of the display pixel region, the first dummy sub-region comprising dummy data line L1, and the second dummy sub-region comprising dummy data line L2); and an end of each active gate line close to the second gate driving circuit is on a side of one dummy data line, farthest from the active display region in the first dummy sub-region where the end is located, away from the active display region, and the active gate line is connected to a corresponding driving signal output terminal in the second gate driving circuit (even-numbered gate lines G2, G4, G6, … G2n connected to gate driver 402, two dummy sub-regions on two opposite sides of the display pixel region, the first dummy sub-region comprising dummy data line L1, and the second dummy sub-region comprising dummy data line L2).
Regarding claim 24, WU in view of LEE discloses the display substrate of claim 1, LEE (e.g., Figs. 1-3) discloses a display panel, comprising: the display substrate (Fig. 2; display substrate 100) of claim 1 and an opposite substrate (Fig. 2; display substrate 200) opposite to the display substrate.
Regarding claim 25, WU in view of LEE discloses the display substrate of claim 24, LEE (e.g., Figs. 1-3) discloses a display apparatus, comprising: the display panel of claim 24 and a source driving chip (data driver 500); wherein the source driving chip (data driver 500) is connected to the plurality of active data lines (data lines D) and configured to provide a data voltage (Fig. 8; data signal) for each of the plurality of active data lines.
7. Claims 4, 6, and 26-27 are rejected under 35 U.S.C. 103 as unpatentable over WU (CN 111599826 A) in view of LEE (US 20060081850 A1) and further in view of HAN (US 20190096345 A1).
Regarding claim 4, WU in view of LEE discloses the display substrate of claim 1, but does not disclose wherein the at least one dummy data line within the first dummy sub-region comprises two or more dummy data lines. However, HAN (Figs. 1-3) discloses a display device similar to that disclosed by WU, wherein the at least one dummy data line within the first dummy sub-region comprises two or more dummy data lines; and the end of each of the at least one active gate line extending to the corresponding first dummy sub-region is between two dummy data lines farthest from the active display region in the first dummy sub-region where the end is located, and a portion, opposite to the end in the first direction, of the one dummy data line farthest from the active display region in the first dummy sub- region where the end is located, protrudes away from the active display region (Figs. 2-3; two or more dummy data lines, e.g., DDn-1 and DDn, are arranged in the dummy area, dummy data line DDn is farthest away from display area and has a portion protruding away from the display area, which corresponds to the end of gate line DS). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from HAN with Wu and LEE to a display panel. The combination/motivation would be to prevent electrical short circuit between signal lines.
Regarding claim 6, WU in view of LEE discloses the display substrate of claim 5, but does not disclose wherein the at least one dummy data line within the first dummy sub-region comprises two or more dummy data lines. However, HAN (Figs. 1-3) discloses a display device similar to that disclosed by WU, wherein the at least one dummy data line within the first dummy sub-region comprises two or more dummy data lines (Figs. 2-3; two or more dummy data lines, e.g., DDn-1 and DDn are arranged in the dummy area). Therefore, the combination of WU, LEE and HAN discloses an end of each first gate line close to the second gate driving circuit is between two dummy data lines farthest from the active display region in the first dummy sub-region where the end is located, and a portion, opposite to the end in the first direction, of the one dummy data line farthest from the active display region in the first dummy sub-region where the end is located, protrudes away from the active display region (Figs. 2-3; two or more dummy data lines, e.g., L2-1 and L2-2, are arranged in the dummy area, dummy data line L2-2 is farthest away from display area and has a portion protruding away from the display area, which corresponds to the end of odd-number gate line G1, G2, G3, … G2n+1); and an end of each second gate line close to the first gate driving circuit is between two dummy data lines farthest from the active display region in the first dummy sub-region where the end is located, and a portion, opposite to the end in the first direction, of the one dummy data line farthest from the active display region in the first dummy sub-region where the end is located, protrudes away from the active display region (Figs. 2-3; two or more dummy data lines, e.g., L1-1 and L1-2, are arranged in the dummy area, dummy data line L1-2 is farthest away from display area and has a portion protruding away from the display area, which corresponds to the end of even-number gate line G2, G3, G4, … G2n). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from HAN with Wu and LEE to a display panel. The combination/motivation would be to prevent electrical short circuit between signal lines.
Regarding claim 26, WU in view of LEE discloses the display substrate of claim 1, wherein the dummy region comprises two first dummy sub-regions on two opposite sides of the active display region in the first direction, respectively, the base substrate further comprises a peripheral region surrounding the dummy region and comprising: two first peripheral sub-regions, each of which is on a side of a corresponding one of the two first dummy sub-regions away from the active display region, and the display substrate further comprises a first gate driving circuit and a second gate driving circuit in the two first peripheral sub-regions, respectively; the plurality of active gate lines in the active display region comprise: a plurality of first gate lines and a plurality of second gate lines alternately arranged along the second direction; one end of each active gate line close to the first gate driving circuit is on a side of one dummy data line, farthest from the active display region in the first dummy sub-region where the one end is located, away from the active display region, and the active gate line is connected to a corresponding driving signal output terminal in the first gate driving circuit, and the other end of the active gate line close to the second gate driving circuit is between two dummy data lines farthest from the active display region in the first dummy sub-region where the other end is located, and a portion, opposite to the other end in the first direction, of the one dummy data line farthest from the active display region in the first dummy sub-region where the other end is located, protrudes away from the active display region; and one end of each active gate line close to the second gate driving circuit is on a side of one dummy data line, farthest from the active display region in the first dummy sub-region where the one end is located, away from the active display region, and the active gate line is connected to a corresponding driving signal output terminal in the second gate driving circuit, and the other end of each second gate line close to the first gate driving circuit is between two dummy data lines farthest from the active display region in the first dummy sub- region where the other end is located, and a portion, opposite to the other end in the first direction, of the one dummy data line farthest from the active display region in the first dummy sub-region where the other end is located, protrudes away from the active display region (claim 26 recites the limitations of claims 5 and 6, see rejections of claims 5 and 6).
Regarding claim 27, WU in view of LEE and further in view of HAN discloses the display substrate of claim 26, WU discloses wherein the portion comprises a first segment, a second segment, a second segment and a third segment connected in sequence (Fig. 3; segment 26ab, segment 26aa, segment 26ac); the first segment and the third segment extend along the first direction; and the third segment extends along the third direction (Fig. 3; segment 26ab, segment 26aa, segment 26ac); and the other end of the active gate line is opposite to the second segment connected between the first segment and the third segment (Fig. 3; segment 26ab, segment 26aa, segment 26ac, and the gate line 241).
8. Claim 8 is rejected under 35 U.S.C. 103 as unpatentable over WU (CN 111599826 A) in view of LEE (US 20060081850 A1) and further in view of HAN (US 20190096345 A1) and KIM (US 20160070147 A1).
Regarding claim 8, WU in view of LEE discloses the display substrate of claim 1, but does not disclose the features in claim 8. However, HAN discloses wherein a distance in the first direction between the end of each active gate line extending to the corresponding first dummy sub-region and any one dummy data line in the first dummy sub-region where the end is located is greater than or equal to 7um and less than or equal to 20um (Figs. 2-3 and [0036]; e.g., distance is in a range of 5-15um). Furthermore, KIM (Figs. 2 and 11) discloses a display device, wherein the display substrate further comprises: a common voltage line in the dummy region (Figs. 2 and 11; common voltage line Vcom in the dummy region including dummy data line DDL); and the plurality of active gate lines and the common voltage line are arranged in a same layer (Figs. 2 and 11; common voltage line VcomLm and gate lines GL are arranged in a same layer). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from HAN and KIM with Wu and LEE to a display panel. The combination/motivation would be to prevent electrical short circuit between signal lines and suppress electrostatic noise of display device.
9. Claims 10, 12, 14-15, and 17 are rejected under 35 U.S.C. 103 as unpatentable over WU (CN 111599826 A) in view of LEE (US 20060081850 A1) and further in view of HAN (US 20190096345 A1) and KIM (US 20180164620 A1).
Regarding claim 10, WU in view of LEE discloses the display substrate of claim 1, but does not disclose the features in claim 10. However, HAN (Figs. 1-3) discloses a display device similar to that disclosed by WU, wherein the at least one dummy data line within the first dummy sub-region comprises two or more dummy data lines (Figs. 2-3; two or more dummy data lines, e.g., DDn-1 and DDn are arranged in the dummy area), and KIM (Figs. 1-3 and 8-11) discloses a display device, wherein the display substrate further comprises: a common voltage line in the dummy region (common voltage line Vcom); and a plurality of active data lines in the active display region, extending along the second direction (data lines DL), and insulated from the common voltage line (common voltage line Vcom); and the at least one dummy data line within the first dummy sub-region comprises two or more dummy data lines connected to the common voltage line, and at least two dummy data lines are not in contact with each other (dummy data lines 501-506 connected to common voltage line Vcom), wherein the display substrate further comprises: first conductive connection structures on a side of the two or more dummy data lines away from the base substrate; wherein the two or more dummy data lines are connected to the common voltage line through corresponding first conductive connection structures, respectively, the first conductive connection structures each comprise a first portion and a second portion connected to each other, the first portion is connected to the corresponding dummy data line, and the second portion is connected to the common voltage (dummy data lines 501-506 connected to common voltage line Vcom through connection lines 41-43, connection lines 41-43 comprise a first portion connected to the corresponding dummy data line 501-506, and a second portion connected to the common voltage Vcom). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from HAN and KIM with Wu and LEE to a display panel. The combination/motivation would be to prevent electrical short circuit between signal lines and suppress electrostatic noise of display device.
Regarding claim 12, WU in view of LEE and further in view of HAN and KIM discloses the display substrate of claim 10, KIM (Figs. 1-3 and 8-11) discloses wherein the dummy region further comprises: two second dummy sub-regions on two opposite sides of the active display region in the second direction (Figs. 1-3 and 8-11; two second dummy sub-regions on two opposite sides of the active display region in Y direction); the common voltage line comprises: two second common voltage sub-lines in the two second dummy sub-regions, respectively, and extending along the first direction (Figs. 1-3 and 8-11; common voltage line comprises two second common voltage sub-lines Vcom and 401 in the two second dummy sub-regions, respectively, and extending along the X direction); and two ends of each dummy data line are connected to the two second common voltage sub-lines through the corresponding first conductive connection structures, respectively (Figs. 1-3 and 8-11; two ends of dummy data lines 501-506 connected to common voltage lines Vcom and 401); and wherein orthographic projections of the two ends of each dummy data line on the base substrate overlap with orthographic projections of the two second common voltage sub-lines on the base substrate, respectively (Figs. 1-3 and 8-11; orthographic projections of dummy data line 501-506 and two second common voltage sub-lines Vcom and 401 on the base substrate). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from HAN and KIM with Wu and LEE to a display panel for the same reason above.
Regarding claim 14, WU in view of LEE and further in view of HAN and KIM discloses the display substrate of claim 10, KIM (Figs. 1-3 and 8-11) discloses wherein the two ends of each dummy data line are a first end and a second end, respectively; first ends of at least two dummy data lines in a same first dummy sub- region are connected to different portions of a same first conductive connection structure of the first conductive connection structures (Figs. 1-3 and 8-11; dummy data lines 501-506 in first dummy sub- region and connection to common voltage sub-lines Vcom and 401); and second ends of the at least two dummy data lines in a same first dummy sub-region are connected to different portions of a same first conductive connection structure of the first conductive connection structures (Figs. 1-3 and 8-11; dummy data line 501-506 in first dummy sub- region and connection to common voltage sub-lines Vcom and 401). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from HAN and KIM with Wu and LEE to a display panel for the same reason above.
Regarding claim 15, WU in view of LEE and further in view of HAN and KIM discloses the display substrate of claim 1, KIM (Figs. 1-3 and 8-11) discloses the display substrate further comprising: a gate insulating layer on a side of the common voltage line away from the base substrate, wherein the at least one dummy data line is on a side of the gate insulating layer away from the base substrate; a planarization layer on a side of the at least one dummy data line away from the base substrate; a pixel electrode layer on a side of the planarization layer away from the base substrate, and comprising a plurality of pixel electrodes; and a passivation layer on a side of the pixel electrode layer away from the base substrate; wherein the first conductive connection structures are on a side of the passivation layer away from the base substrate, the first portion is connected to the corresponding dummy data line through a via in the passivation layer exposing a surface of the corresponding dummy data line, and the second portion is connected to the common voltage line through a via in the passivation layer, the planarization layer, and the gate insulating layer exposing a surface of the common voltage line; and the display substrate further comprises a common electrode on a side of the plurality of active data lines away from the base substrate; and a portion of the common electrode serves as the first conductive connection structure (Figs. 5-7; display substrate comprising: a gate insulating layer 311, planarization layer 321, passivation layer 325, dummy data line 501, common electrode 330, common voltage line 401, conductive connection structures 601, contact hole 61, and pixel electrode layer PE).
Regarding claim 17, WU in view of LEE and further in view of HAN and KIM discloses the display substrate of claim 14, KIM (Figs. 1-3 and 8-11) discloses wherein the base substrate further comprises a peripheral region surrounding the dummy region, and comprising: a first peripheral sub-region on a side of the first dummy sub-region away from the active display region, wherein a gate driving circuit is arranged in the first peripheral sub-region, and at least one end of each active gate line is connected to at least one corresponding driving signal output terminal in the gate driving circuit through at least one corresponding second conductive connection structure, respectively (Figs. 1-3 and 8-11; arrangement of gate driver 101/102 and gate line GL); the common voltage line comprises: a first common voltage sub-line in the first dummy sub-region, extending along the second direction and between the plurality of active gate lines and the gate driving circuit (Figs. 1-3 and 8-11; arrangement of common voltage line Vcom and connection to dummy data line 501-506, the dummy data line 501-506 act as common voltage sub-line after receiving common voltage Vcom); and a portion of the first common voltage sub-line directly opposite to the end of each active gate line in the first direction is an avoiding portion, and an orthographic projection of each second conductive connection structure on the base substrate does not overlap with an orthographic projection of the corresponding avoiding portion on the base substrate (Wu’s Fig. 3 and HAN’s Figs. 2-3; dummy data lines are arranged in the dummy area, dummy data line has a portion protruding away from the display area, which corresponds to the end of gate line); and wherein the common voltage line is in the same layer as the plurality of active gate lines; and the second conductive connection structure is in the same layer as the plurality of active data lines and the at least one dummy data line (Figs. 1-3 and 8-11; common voltage line Vcom in the same layer as the gate lines GL, conductive connection structure 51-56 in the same layer as dummy data line 501-506) .
10. Claims 19-20 and 22 are under 35 U.S.C. 103 as unpatentable over WU (CN 111599826 A) in view of LEE (US 20060081850 A1) and LIN (US 20190067218 A1) and further in view of DU (US 20160240120 A1).
Regarding claim 19, WU in view of LEE discloses the display substrate of claim 1, LEE (Figs. 1 and 3) discloses wherein the base substrate further comprises a peripheral region surrounding the dummy region, and comprising: a bonding sub-region, first peripheral sub- regions and first corner sub-regions, the bonding sub-region is on one side of the active display region in the second direction, each first peripheral sub-region is on a side of the corresponding first dummy sub-region away from the active display region, and each first corner sub-region is between the bonding sub- region and the corresponding first peripheral sub-region (Figs. 1-2 and 8-10; peripheral region surrounding the dummy region including dummy data lines L1 and L2 and comprising a bonding sub-region, first peripheral sub- regions and first corner sub-regions); LEE does not disclose the arrangement of the electrostatic discharge unit as claimed. However, LIN (Figs. 1-2 and 8-10) discloses the display substrate further comprises a plurality of test terminals in each first corner sub-region and a plurality of test lines in each first peripheral sub- region, and one end of each test line close to the bonding sub-region extends into the first corner sub-region and is connected to the corresponding test terminal; the display substrate further comprises a plurality of first electrostatic discharge units in each first corner sub-region, and a portion of each test line in the first corner sub-region is connected to the corresponding first electrostatic discharge unit through a corresponding third conductive connection structure, and each test terminal and the test line connected to the test terminal share a same first electrostatic discharge unit (Figs. 1-2 and 8-10; two electrostatic discharge circuits ESD1 are arranged in each first corner sub-region and connected to electrical terminals through connection lines SNFL, the bonding sub-region corresponding to DIC circuit). As another reference, Du (Figs. 3-6) discloses the same features as claimed (Figs. 3-6; electrostatic discharge circuits are arranged in first corner sub-region and connected to test terminals through test lines). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from LIN and DU to the display device Wu and LEE, which would provide electrostatic discharge protection of the display device.
Regarding claim 20, WU in view of LEE and further in view of LIN discloses the display substrate of claim 19, LIN (Figs. 1-2 and 8-10) discloses wherein the peripheral region further comprises: a bonding opposite sub- region and second corner sub-regions, wherein the bonding opposite sub-region and the bonding sub-region are on two opposite sides of the active display region in the second direction, respectively, and each second corner sub-region is between the bonding opposite sub-region and the corresponding first peripheral sub-region; the display substrate further comprises a plurality of second electrostatic discharge units in each second corner sub-region, one end of each test line close to the bonding opposite sub-region extends into the corresponding second corner sub-region, and a portion of each test line in the second corner sub-region is connected to the corresponding second electrostatic discharge unit through a corresponding fourth conductive connection structure; and each test terminal and the test line connected to the test terminal share a same second electrostatic discharge unit (Figs. 1-2 and 8-10; two electrostatic discharge circuits ESD1 are arranged in each first corner sub-region and connected to electrical terminals through connection lines SNFL). LIN does not disclose ach first electrostatic discharge unit comprises a first transistor and a second transistor as claimed. However, Du (Figs. 3-6) discloses wherein each first electrostatic discharge unit comprises: a first transistor and a second transistor; a gate electrode of the first transistor and a first electrode of the first transistor are connected to the corresponding third conductive connection structure, and a second electrode of the first transistor is connected to the common voltage line; and a gate electrode of the second transistor and a second electrode of the second transistor are connected to the common voltage line, and a first electrode of the second transistor is connected to the corresponding third conductive connection structure (Fig. 3; first electrostatic discharge protection circuit 17 comprises a first transistor 171 and a second transistor 172, the electrical connection of the first transistor 171 and the second transistor 172 and connection to common voltage line 19 is same as the claimed features). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from LIN and DU to the display device Wu and LEE, which would provide electrostatic discharge protection of the display device.
Regarding claim 22, WU in view of LEE and further in view of LIN and DU discloses the display substrate of claim 20, Du (Figs. 3-6) discloses wherein each second electrostatic discharge unit comprises: a third transistor and a fourth transistor; a gate electrode of the third transistor and a first electrode of the third transistor are connected to the corresponding fourth conductive connection structure, and a second electrode of the third transistor is connected to the common voltage line; and a gate electrode of the fourth transistor and a second electrode of the fourth transistor are connected to the common voltage line, and a first electrode of the fourth transistor is connected to the corresponding fourth conductive connection structure; and wherein the plurality of test lines are in the same layer as the common voltage line; and the third conductive connection structure, the fourth conductive connection structure and the at least one dummy data line are arranged in a same layer (Fig. 3; second electrostatic discharge protection circuit 17 comprises a first transistor 171 and a second transistor 172, the electrical connection of the first transistor 171 and the second transistor 172 and connection to common voltage line 19 is same as the claimed features, test lines 14 are arranged in parallel in the same layer as the common voltage line 19, the third conductive connection line, the fourth conductive connection line and the data line are arranged are arranged in parallel in a same layer). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from LIN and DU to the display device Wu and LEE, which would provide electrostatic discharge protection of the display device.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YUZHEN SHEN whose telephone number is (571)272-1407. The examiner can normally be reached on Monday-Thursday 8:30am-5:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YUZHEN SHEN/Primary Examiner, Art Unit 2623
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