DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pak et al (US 2008/0055225 A1).
Claim 1, Pak (Fig. 1-10) discloses a shift register unit (Fig. 3; Paragraph [0044]; wherein discloses a shift register), comprising:
a pull-up module (410; Fig. 3) connected to an input terminal (IN1; Fig. 3) and a pull-up node (N1; Fig. 3), wherein the pull-up module (410; Fig. 3) is configured to pull up (Paragraph [0047]) the pull-up node (N1; Fig. 3) by a signal (STV or OUT1 of previous stage; Fig. 3) of the input terminal (IN1; Fig. 2 and 3) in response to the signal (STV or OUT1 of previous stage; Fig. 3) of the input terminal (IN1; Fig. 2 and 3);
a cascade control module (430; Fig. 3) connected to a first clock signal terminal (CK1; Fig. 3), the pull-up node (N1; Fig. 3) and a cascade signal output terminal (OUT1; Fig. 3), wherein the cascade control module (430; Fig. 3) is configured to transmit a signal (CKV or CKVB; Fig. 2) of the first clock signal terminal (CK1; Fig. 2) to the cascade signal output terminal (OUT1; Fig. 2 and 3) in response to a signal (Paragraph [0049]) of the pull-up node (N1; Fig. 3); and
a gate control module (450; Fig. 3) connected to the pull-up node (N1; Fig. 3), a second clock signal terminal (CK2; Fig. 3) and a gate signal output terminal (OUT2; Fig. 3), wherein the gate control module (450; Fig. 3) is configured to transmit a signal (CKV_P or CKVB_P; Fig. 2) of the second clock signal terminal (CK2; Fig. 2) to the gate signal output terminal (OUT2; Fig. 3) in response to the signal (Paragraph [0050]) of the pull-up node (N1; Fig. 3).
Claim 2, Pak (Fig. 1-10) discloses wherein the cascade control module (430; Fig. 3) and the gate control module (450; Fig. 3) are both one or more (Fig. 3; wherein figure shows one of each module), and a number of the gate control modules (450; Fig. 3; wherein figure shows one module) is k times (k=1) a number of the cascade control modules (430; Fig. 3; wherein figure shows one module), and k is a positive integer greater than or equal to 1 (Fig. 3; wherein Pak’s figure 3 reads at least on Applicant’s figure 6 which shows a 1 to 1 of elements 200 and 300).
Claim 9, Pak (Fig. 1-10) discloses wherein a pulse width of a conducting level (CKV or CKVB; Fig. 4; wherein figure shows a high level pulse width of the clock signals CKV and CKVB) output by the first clock signal terminal (CK1; Fig. 2 and 3) is greater than or equal to a pulse width of a conducting level (CKV_P or CKVB_P; Fig. 4; wherein figure shows a high level pulse width of the clock signals CKV_P and CKVB_P which is the equal to the clock signals CKV and CKVB; Paragraph [0058]; wherein states “s illustrated in FIG. 4, in a display section I, CKV_P alternately repeats high level and low level with a same phase as CKV, and CKVB_P alternately repeats high level and low level with a same phase as CKVB”) output by the second clock signal terminal (CK2; Fig. 2 and 3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10, and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Pak et al (US 2008/0055225 A1) in view of Umezaki (US 2011/0193836 A1).
Claim 10, Pak (Fig. 1-10) discloses wherein the shift register unit (Fig. 3) further comprises:
a first reset module (420; Fig. 3) connected to a reset signal terminal (IN2; Fig. 3), the pull-up node (N1; Fig. 3) and receiving a first level signal (VSS; Fig. 3), wherein the first reset module (420; Fig. 3) is configured to reset (Paragraph [0048]) the pull-up node (N1; Fig. 3) by the first level signal (VSS; Fig. 3) in response to a signal (R2-Rn+1; Fig. 2) of the reset signal terminal (IN2; Fig. 2);
a pull-down module (T8; Fig. 3) connected to the pull-up node (N1; Fig. 3) and a pull-down node (N2; Fig. 3) and receiving the first level signal (VSS; Fig. 3), wherein the pull-down module (T8; Fig. 3) is configured to pull down (Paragraph [0061]) the pull-down node (N2; Fig. 3) by the first level signal (VSS; Fig. 3) in response to the signal (Paragraph [0061]) of the pull-up node (N1; Fig. 3);
a second reset module (T9; Fig. 3) connected to the cascade signal output terminal (OUT1; Fig. 3), the pull-down node (N2; Fig. 3) and receiving the first level signal (VSS; Fig. 3), wherein the second reset module (T9; Fig. 3) is configured to reset (Paragraph [0063]) the cascade signal output terminal (OUT1; Fig. 3) by the first level signal (VSS; Fig. 3) in response to a signal (Paragraph [0063]) of the pull-down node (N2; Fig. 3);
a third reset module (T10; Fig. 3) connected to the gate signal output terminal (OUT2; Fig. 3), the pull-down node (N2; Fig. 3) and receiving a second level signal (VSS; Fig. 3), wherein the third reset module (T10; Fig. 3) is configured to reset (Paragraph [0063]) the gate signal output terminal (OUT2; Fig. 3) by the second level signal (VSS; Fig. 3) in response to the signal (Paragraph [0063]) of the pull-down node (N2; Fig. 3);
a first coupling module (C1; Fig. 3) connected to the pull-up node (N1; Fig. 3) and the cascade signal output terminal (OUT1; Fig. 3), wherein the first coupling module (C1; Fig. 3) is configured to couple a signal (Paragraph [0068]) of the cascade signal output terminal (OUT1; Fig. 3) to the pull-up node (N1; Fig. 3); and
a second coupling module (C2; Fig. 3) connected to the pull-up node (N1; Fig. 3) and the gate signal output terminal (OUT2; Fig. 3), wherein the second coupling module (C2; Fig. 3) is configured to couple a signal (Paragraph [0068]) of the gate signal output terminal (OUT2; Fig. 3) to the pull-up node (N1; Fig. 3).
Pak does not expressly disclose a pull-down control module connected to a first power supply terminal and the pull-down node, wherein the pull-down control module is configured to pull up the pull-down node by a signal of the first power supply terminal in response to the signal of the first power supply terminal.
Umezaki (Fig. 1A-28H) discloses a pull-down control module (302; Fig. 17B) connected to a first power supply terminal (118; Fig. 17B; Paragraph [0140]) and the pull-down node (N2; Fig. 17B and 6), wherein the pull-down control module (302; Fig. 17B) is configured to pull up the pull-down node (N2; Fig. 17B) by a signal of the first power supply terminal (118; Fig. 17B) in response to the signal of the first power supply terminal (118; Fig. 17B).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Pak’s shift register unit by applying a pull-down control module, as taught by Umezaki, so to use a shift register unit with a pull-down control module for providing a display device in which partial driving can be performed with a simplified configuration of a circuit including a wiring (Paragraph [0006]).
Claim 12, Pak (Fig. 1-10) discloses wherein the pull-up module (410; Fig. 3) comprises:
a first transistor (T3; Fig. 3), wherein a first electrode and a gate electrode of the first transistor (T3; Fig. 3) are both connected to the input terminal (IN1; Fig. 3), a second electrode of the first transistor (T3; Fig. 3) is connected to the pull-up node (N1; Fig. 3), the first transistor (T3; Fig. 3) is configured to pull up (Paragraph [0047]) the pull-up node (N1; Fig. 3) by the signal (STV or C1-Cn; Fig. 2) of the input terminal (IN1; Fig. 2) in response to the signal (STV or C1-Cn; Fig. 2) of the input terminal (IN1; Fig. 2);
the cascade control module (430; Fig. 3) comprises:
a seventh transistor (T1; Fig. 3), wherein a first electrode of the seventh transistor (T1; Fig. 3) is connected to the first clock signal terminal (CK1; Fig. 3), a second electrode of the seventh transistor (T1; Fig. 3) is connected to the cascade signal output terminal (OUT1; Fig. 3), a gate electrode of the seventh transistor (T1; Fig. 3) is connected to the pull-up node (N1; Fig. 3), the seventh transistor (T1; Fig. 3) is configured to transmit (Paragraph [0049]) the signal (CKV or CKVB; Fig. 2) of the first clock signal terminal (CK1; Fig. 2 and 3) to the cascade signal output terminal (OUT1; Fig. 2 and 3) in response to the signal of the pull-up node (N1; Fig. 3);
the gate control module (450; Fig. 3) comprises:
a third transistor (T2; Fig. 3), wherein a first electrode of the third transistor (T2; Fig. 3) is connected to the second clock signal terminal (CK2; Fig. 3), a second electrode of the third transistor (T2; Fig. 3) is connected to the gate signal output terminal (OUT2; Fig. 3), a gate electrode of the third transistor (T2; Fig. 3) is connected to the pull-up node (N1; Fig. 3), and the third transistor (T2; Fig. 3) is configured to transmit (Paragraph [0050]) the signal (CKV_P or CKVB_P; Fig. 2) of the second clock signal terminal (CK2; Fig. 2 and 3) to the gate signal output terminal (OUT2; Fig. 3) in response to the signal of the pull-up node (N1; Fig. 3);
the first reset module (420; Fig. 3) comprises:
a second transistor (T4; Fig. 3), wherein a first electrode of the second transistor (T4; Fig. 3) is connected to the pull-up node (N1; Fig. 3), a second electrode of the second transistor (T4; Fig. 3) receives the first level signal (VSS; Fig. 3), a gate of the second transistor (T4; Fig. 3) is connected to the reset signal terminal (IN2; Fig. 3), and the second transistor (T4; Fig. 3) is configured to reset (Paragraph [0048]) the pull-up node (N1; Fig. 3) by the first level signal (VSS; Fig. 3) in response to the signal (R2-Rn+1; Fig. 2) of the reset signal terminal (IN2; Fig. 2 and 3);
the pull-down module (T8; Fig. 3) comprises:
a sixth transistor (T8; Fig. 3), a first electrode of the sixth transistor (T8; Fig. 3) is connected to the pull-down node (N2; Fig. 3), a second electrode of the sixth transistor (T8; Fig. 3) receives the first level signal (VSS; Fig. 3), a gate electrode of the sixth transistor (T8; Fig. 3) is connected to the pull-up node (N1; Fig. 3), and the sixth transistor (T8; Fig. 3) is configured to pull down (Paragraph [0061]) the pull-down node (N2; Fig. 3) by the first level signal (VSS; Fig. 3) in response to the signal (Paragraph [0061]) of the pull-up node (N1; Fig. 3);
the second reset module (T9; Fig. 3) comprises:
an eighth transistor (T9; Fig. 3), wherein a first electrode of the eighth transistor (T9; Fig. 3) is connected to the cascade signal output terminal (OUT1; Fig. 3), a second electrode of the eighth transistor (T9; Fig. 3) receives the first level signal (VSS; Fig. 3), a gate electrode of the eighth transistor (T9; Fig. 3) is connected to the pull-down node (N2; Fig. 8), and the eighth transistor (T9; Fig. 3) is configured to reset (Paragraph [0063]) the cascade signal output terminal (OUT1; Fig. 3) by the first level signal (VSS; Fig. 3) in response to the signal (Paragraph [0063]) of the pull-down node (N2; Fig. 3);
the third reset module (T10; Fig. 3) comprises:
a fourth transistor (T10; Fig. 3), wherein a first electrode of the fourth transistor (T10; Fig. 3) is connected to the gate signal output terminal (OUT2; Fig. 3), a second electrode of the fourth transistor (T10; Fig. 3) receives the second level signal (VSS; Fig. 3), a gate electrode of the fourth transistor (T10; Fig. 3) is connected to the pull-down node (N2; fig. 3), and the fourth transistor (T10; Fig. 3) is configured to reset (Paragraph [0063]) the gate signal output terminal (OUT2; Fig. 3) by the second level signal (VSS; Fig. 3) in response to the signal (Paragraph [0063]) of the pull-down node (N2; Fig. 3);
the first coupling module (C1; Fig. 3) comprises:
a first capacitor (C1; Fig. 3), wherein one terminal of the first capacitor (C1; Fig. 3) is connected to the pull-up node (N1; Fig. 3) and another terminal (C1; Fig. 3) is connected to the cascade signal output terminal (OUT1; Fig. 3), and the first capacitor (C1; Fig. 3) is configured to couple the signal (Paragraph [0068]) of the cascade signal output terminal (OUT1; Fig. 3) to the pull-up node (N1; Fig. 3);
the second coupling module (C2; Fig. 3) comprises:
a second capacitor (C2; Fig. 3), wherein one terminal of the second capacitor (C2; Fig. 3) is connected to the pull-up node (N1; Fig. 3) and another terminal (C2; Fig. 3) is connected to the gate signal output terminal (OUT2; Fig. 3), and the first capacitor (C2; Fig. 3) is configured to couple the signal (Paragraph [0068]) of the gate signal output terminal (OUT2; Fig. 3) to the pull-up node (N1; Fig. 3).
Umezaki (Fig. 1A-28H) discloses the pull-down control module (302; Fig. 17B) comprises:
a fifth transistor (302; Fig. 17B), wherein a first electrode and a gate electrode of the fifth transistor (302; Fig. 17B) are both connected to the first power supply terminal (118; Fig. 17B; Paragraph [0140]), a second electrode of the fifth transistor (302; Fig. 17B) is connected to the pull-down node (N2; Fig. 17B and 13A), the fifth transistor (302; Fig. 17B) is configured to pull up the pull-down node (N2; Fig. 17B) by the signal of the first power supply terminal (118; Fig. 17B; Paragraph [0140]) in response to the signal of the first power supply terminal (118; Fig. 17B; Paragraph [0140]);
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Pak’s shift register unit by applying a pull-down control module, as taught by Umezaki, so to use a shift register unit with a pull-down control module for providing a display device in which partial driving can be performed with a simplified configuration of a circuit including a wiring (Paragraph [0006]).
Claim 13, Umezaki (Fig. 1A-28H) discloses wherein polarities of the conducting levels of the first transistor to the eighth transistor are same (204, 102, 101, 205, 202, and 201; Fig. 13A; 302 and 303; Fig. 17B; Claim 10; wherein states “wherein the first to eighth transistors have the same conductivity type”).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Pak’s shift register unit by applying a pull-down control module, as taught by Umezaki, so to use a shift register unit with a pull-down control module for providing a display device in which partial driving can be performed with a simplified configuration of a circuit including a wiring (Paragraph [0006]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Pak et al (US 2008/0055225 A1) in view of Umezaki (US 2011/0193836 A1) as applied to claim 10 above, and further in view of Tseng et al (US 2013/0135284 A1).
Claim 11, Pak (Fig. 1-10) discloses wherein when the cascade control module (430; Fig. 3) and the gate control module (450; Fig. 3) are both single (Fig. 3; wherein figure shows both units contain a single transistor), the cascade control module (430; Fig. 3) and the gate control module (450; Fig. 3) share a same pull-up module (410; Fig. 3).
Pak in view of Umezaki does not expressly disclose when there are multiple gate control modules, a number of the pull-up modules and a number of the first reset modules are both a sum of a number of the cascade control modules and a number of the gate control modules, a number of the second reset modules is same as the number of the cascade control modules, and a number of the third reset modules is same as the number of the gate control modules.
Tseng (Fig. 2-11) discloses when there are multiple gate control modules (902; Fig. 9), a number of the pull-up modules (M1 and M11; Fig. 9) and a number of the first reset modules (M2 and M22; Fig. 9) are both a sum of a number of the cascade control modules (901; Fig. 9) and a number of the gate control modules (902; Fig. 11), a number of the second reset modules (M9 and M8; Fig. 9) is same as the number of the cascade control modules (M3 and M4; Fig. 9), and a number of the third reset modules (M71, M72, and M73; Fig. 9) is same as the number of the gate control modules (M33, M44, and M55; Fig. 9).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Pak in view of Umezaki’s shift register unit by applying a divided gate driving circuit, as taught by Tseng, so to use a shift register unit with a divided gate driving circuit for providing to reduce the number of the stages required by the gate driver, and the switches in the gate driver are reverse biased when the switches stop operating, thereby isolating the leakage current path and preventing the leakage current from being generated (Paragraph [0088]).
Claims 14-18, and 20-23 are rejected under 35 U.S.C. 103 as being unpatentable over Pak et al (US 2008/0055225 A1) in view of Lee et al (US 2017/0076683 A1).
Claim 14, Pak (Fig. 1-10) discloses a display panel (100; Fig. 1), comprising a gate driving circuit (400; Fig. 1), wherein the gate driving circuit (400; Fig. 1) comprises a plurality of shift register units (SG1-SGn+1; Fig. 2) according to claim 1 (See rejection to claim 1 above), and the plurality of shift register units (SG1-SGn+1; Fig. 2) are cascaded (Paragraph [0007]; wherein discloses sequentially coupled).
Pak does not expressly disclose a touch display panel.
Lee (Fig. 1-18) discloses a touch display panel (Fig. 1-2B; Paragraph [0044]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Pak’s display panel by applying a touch display panel, as taught by Lee, so to use a display panel with a touch display panel for providing a pixel charging time can be reduced, and an image quality defect such flicker can occur due to pixel coupling and noise which occur when each of the additional functions is performed (Paragraph [0011]).
Claim 15, Pak (Fig. 1-10) discloses wherein the gate driving circuit (400; Fig. 1) comprises:
a plurality of repeating units (SG1-SGn+1; Fig.2), wherein the repeating unit (SG1-SGn+1; Fig.2) comprises a plurality of cascaded shift register units (Paragraph [0007]; wherein discloses sequentially coupled);
at least two first clock signal lines (CKV and CKVB; Fig. 2), wherein the first clock signal line (CKV and CKVB; Fig. 2) is configured to connect the first clock signal terminal (CK1; Fig. 2);
at least two second clock signal lines (CKV_P and CKVB_P; Fig. 2), wherein the second clock signal line (CKV_P and CKVB_P; Fig. 2) is configured to connect the second clock signal terminal (CK2; Fig. 2);
wherein, a number of the first clock signal lines (CKV and CKVB; Fig. 2) is same as a number of the shift register units contained in the repeating unit (SG1 and SG2; Fig. 2), and a number of the second clock signal lines (CKV_P and CKVB_P; Fig. 2) is k times (Fig. 2; wherein k is 1) the number of the first clock signal lines (CKV and CKVB; Fig. 2), wherein k is a positive integer greater than or equal to 1 (Fig. 2; wherein k is 1);
shift register units in a same repeating unit (SG1 and SG2; Fig. 2) are connected to the first clock signal lines (CKV and CKVB; Fig. 2) in one-to-one correspondence (Fig. 2), and shift register units of a same stage in different repeating units (SG1 and SG3; Fig. 2) are connected to a same first clock signal line (CKV; Fig. 2); and
each shift register unit in the same repeating unit (SG1 and SG2; Fig. 2) is connected to k second clock signal lines (CKV_P and CKVB_P; Fig. 2), and shift register units of the same stage in different repeating units (SG1 and SG3; Fig. 2) are connected to same second clock signal lines (CKV_P; Fig. 2).
Claim 16, Lee (Fig. 1-18) discloses a display panel (Fig 1) driving method (Fig. 3C and 5), for driving the touch display panel (Fig. 1-2B) according to claim 14 (See rejection to claim 14 above), wherein the method (Fig. 3C and 5) comprises:
arranging a display phase (Moving image reproduction part; Fig. 3C; Paragraph [0045]; wherein discloses image display period) and a touch phase (Screen non-driving part; Fig. 3C; Paragraph [0045]; wherein discloses touch sensing period; Paragraph [0058]; wherein discloses “an operation of sensing a touch, operations which are easily performed in a state where the scan signal is not output to the gate line may be performed a plurality of times during one frame period”) adjacent to each other in time sequence (Fig. 3C; Paragraph [0058]; wherein discloses “an operation of sensing a touch, operations which are easily performed in a state where the scan signal is not output to the gate line may be performed a plurality of times during one frame period”),
in the display phase (Fig. 5; wherein figure shows a period in which REUSE is low level), determining a target shift register unit (start to stop; Fig. 7; 260; Fig. 4), a cascade control module (Fig. 12; wherein figure shows a transistor connected between a clock signal CLK(n) and Carry Out(N)) and a gate control module (Fig. 12; wherein figure shows a transistor connected between transistor T41 and Gate Out(N)) in the target shift register unit (Fig. 12) both have output a conducting level in the display phase (Gout1 and Carry1; Fig. 5), and a gate control module (Fig. 12; wherein figure shows a transistor connected between transistor T41 and Gate Out(N)) in a shift register unit (Fig. 12) of a next stage of the target shift register unit (Fig. 4) does not output a conducting level in the display phase (Fig. 5; wherein figure shows a delay from the start of the conducting level of adjacent gate out signals);
in the touch phase (Fig. 5; wherein figure shows a period in which REUSE is high level), controlling a cascade signal output terminal (Carry Out(N); Fig. 12) of the target shift register unit (Fig. 12) to output the conducting level (Carry7; Fig. 5) by controlling (Enable; Fig. 12) the second clock signal terminal (T41; Fig. 12) to output a non-conducting level (Ground and T51; Fig. 12) to the target shift register unit (Fig. 12), and controlling the first clock signal terminal (CLK(n); Fig. 12) to output the conducting level (CLK 7; Fig. 5) to the target shift register unit (Fig. 12) for at least part of time (Fig. 5; wherein figure shows a period in which REUSE is high level).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Pak’s display panel by applying a touch display panel, as taught by Lee, so to use a display panel with a touch display panel for providing a pixel charging time can be reduced, and an image quality defect such flicker can occur due to pixel coupling and noise which occur when each of the additional functions is performed (Paragraph [0011]).
Claim 17, Lee (Fig. 1-18) discloses wherein in the touch phase (Screen non-driving part; Fig. 3C; Paragraph [0045]; wherein discloses touch sensing period; Paragraph [0058]; wherein discloses “an operation of sensing a touch, operations which are easily performed in a state where the scan signal is not output to the gate line may be performed a plurality of times during one frame period”), a number of conducting levels output by the first clock signal terminal (CLK7; Fig. 5) to the target shift register unit (Fig. 12) is one or more (Fig. 5; wherein figure shows one pulse being output during a period in which REUSE is high level).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Pak’s display panel by applying a touch display panel, as taught by Lee, so to use a display panel with a touch display panel for providing a pixel charging time can be reduced, and an image quality defect such flicker can occur due to pixel coupling and noise which occur when each of the additional functions is performed (Paragraph [0011]).
Claim 18, Pak (Fig. 1-10) discloses wherein a cascade signal output terminal (OUT1; Fig. 2) of a shift register unit of a Nth stage (SGn; Fig. 2) is connected to an input terminal (IN1; Fig. 2) of a shift register unit of a (N+k)th stage (SGn-1; Fig. 2), and N is a natural number (Fig. 2; wherein figure shows a plurality of stages).
Claim 20, Lee (Fig. 1-18) discloses wherein the shift register unit (Fig. 12) is configured to output a gate driving signal (Gate out(N); Fig. 12) to drive the touch display panel (Fig. 1), and the touch display panel (Fig. 3C) alternately operates in a display phase (Moving image reproduction part; Fig. 3C; Paragraph [0045]; wherein discloses image display period) and a touch phase (Screen non-driving part; Fig. 3C; Paragraph [0045]; wherein discloses touch sensing period; Paragraph [0058]; wherein discloses “an operation of sensing a touch, operations which are easily performed in a state where the scan signal is not output to the gate line may be performed a plurality of times during one frame period”);
when the touch display panel (Fig. 5C) operates in the touch phase (Screen non-driving part; Fig. 3C; Paragraph [0045]; wherein discloses touch sensing period; Paragraph [0058]; wherein discloses “an operation of sensing a touch, operations which are easily performed in a state where the scan signal is not output to the gate line may be performed a plurality of times during one frame period”), the second clock signal terminal (T41; Fig. 12) is configured to output a non-conducting level (Ground and T5i; Fig. 12) to a target shift register unit (Fig. 12), and the first clock signal terminal (CLK(n); Fig. 12) is configured to output a conducting level (Fig. 5) to the target shift register unit (Fig. 12) for at least part of time (Fig. 5), wherein a cascade control module (Fig. 12; wherein figure shows a transistor connected between a clock signal CLK(n) and Carry Out(N)) and a gate control module (Fig. 12; wherein figure shows a transistor connected between transistor T41 and Gate Out(N)) in the target shift register unit (Fig. 12) have both output a conducting level (Gout1 and Carry1; Fig. 5) before the touch phase (Fig. 5; when signal REUSE is high level), and a gate control module (Fig. 12; wherein figure shows a transistor connected between transistor T41 and Gate Out(N)) in a shift register unit (Fig. 12) of a next stage of the target shift register unit (Fig. 4) does not output a conducting level (Fig. 5; wherein figure shows a delay from the start of the conducting level of adjacent gate out signals) before the touch phase (Fig. 5; when signal REUSE is high level).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Pak’s display panel by applying a touch display panel, as taught by Lee, so to use a display panel with a touch display panel for providing a pixel charging time can be reduced, and an image quality defect such flicker can occur due to pixel coupling and noise which occur when each of the additional functions is performed (Paragraph [0011]).
Claim 21, Lee (Fig. 1-18) discloses wherein a pulse width of the conducting level output (CLK 7; Fig. 5) by the first clock signal terminal (CLK(n); Fig. 12) in the touch phase (Fig. 5; when signal REUSE is high level) is greater than or equal (Fig. 5; wherein figure shows equal clock signals) to a pulse width of the conducting level (CLK 7; Fig. 5) output by the first clock signal terminal (CLK(n); Fig. 12) in the display phase (Fig. 5; when signal REUSE is low level).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Pak’s display panel by applying a touch display panel, as taught by Lee, so to use a display panel with a touch display panel for providing a pixel charging time can be reduced, and an image quality defect such flicker can occur due to pixel coupling and noise which occur when each of the additional functions is performed (Paragraph [0011]).
Claim 22, Lee (Fig. 1-18) discloses wherein the pulse width of the conducting level (CLK 7; Fig. 7) output by the first clock signal terminal (CLK(n); Fig. 12) in the touch phase (Fig. 5; when signal REUSE is high level) is greater than or equal to effective charging time of a row of pixels (Paragraph [0056]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Pak’s display panel by applying a touch display panel, as taught by Lee, so to use a display panel with a touch display panel for providing a pixel charging time can be reduced, and an image quality defect such flicker can occur due to pixel coupling and noise which occur when each of the additional functions is performed (Paragraph [0011]).
Claim 23, Lee (Fig. 1-18) discloses wherein, in the touch phase (Fig. 5; when signal REUSE is high level), a number of the conducting levels (CLK 7; Fig. 5) output by the first clock signal terminal (CLK(n); Fig. 12) to the target shift register unit (Fig. 12) is one or more (Fig. 5; wherein figure shows one pulse).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Pak’s display panel by applying a touch display panel, as taught by Lee, so to use a display panel with a touch display panel for providing a pixel charging time can be reduced, and an image quality defect such flicker can occur due to pixel coupling and noise which occur when each of the additional functions is performed (Paragraph [0011]).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Pak et al (US 2008/0055225 A1) in view of Lee et al (US 2017/0076683 A1) as applied to claim 18 above, and further in view of Feng et al (WO 2021/063322 A1; See US 2022/0051618 A1 for official translation and rejection citations).
Claim 19, Pak (Fig. 1-10) discloses wherein when k is 1 (Fig. 2; wherein figure shows a first stage output OUT1 connected to input IN1 of the next stage), a cascade signal output terminal (OUT1; Fig. 2) of a shift register unit of a (N+1)th stage (SG2; Fig. 2) is connected to a reset signal terminal (IN2; Fig. 2) of a shift register unit of a Nth stage (SG1; Fig. 2).
Pak in view of Lee does not expressly disclose when k is greater than or equal to 2, a cascade signal output terminal of a shift register unit of a (N+m)th stage is connected to a reset signal terminal of a shift register unit of a Nth stage, N is a natural number, m is a positive integer greater than k, and an output signal of a first clock signal terminal connected to the shift register unit of the (N+m)th stage is different from an output signal of a first clock signal terminal connected to the shift register unit of the Nth stage.
Feng (Fig. 1-12) discloses when k is greater than or equal to 2 (Fig. 12; wherein figure shows output O1 from stage RS(1) is connected to input IN1/IN2 of stage RS(3); therefore reading of k=2), a cascade signal output terminal (O1; Fig. 12) of a shift register unit of a (N+m)th stage (RS(4); Fig. 12) is connected to a reset signal terminal (RST1; Fig. 12) of a shift register unit of a Nth stage (RS(1); Fig. 12), N is a natural number (Fig. 12; wherein figure shows at least six stages), m is a positive integer (Fig. 12; wherein figure shows m=3) greater than k (Fig. 12; wherein figure shows output O1 from stage RS(1) is connected to input IN1/IN2 of stage RS(3); therefore reading of k=2), and an output signal (CLKD4; Fig. 12) of a first clock signal terminal (CLKD; Fig. 12 and 8B) and connected to the shift register unit of the (N+m)th stage (RS(4); Fig. 12) is different from an output signal (CLKD1; Fig. 12) of a first clock signal terminal (CLKD; Fig. 12 and 8B) connected to the shift register unit of the Nth stage (RS(1); Fig. 12).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Pak in view of Lee’s display panel by applying a gate driving connection method, as taught by Feng, so to use a display panel with a gate driving connection method for preventing an electrical signal remaining on the first node N1 within duration of a previous frame from affecting an image of a current frame, or preventing an electrical signal remaining on the first node N1 within duration of the current frame from affecting an image of a next frame (Paragraph [0146]).
Conclusion
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/Adam J Snyder/ Primary Examiner, Art Unit 2623 06/26/2026
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