DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1-20 are pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the Examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the Examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2024/0119900) in view of Choi (US 2023/0189590). All reference is to Kim unless otherwise indicated.
Regarding Claims 1 (Original) and 18 (Currently Amended), Kim teaches a display panel and a display, comprising
multiple pixel driving circuits [fig. 7 @PCA1-PCA3] arranged in an array along a first direction [fig. 7 @DR1] and a second direction [fig. 7 @DR2], wherein
the multiple pixel driving circuits comprise first pixel driving circuits [fig. 7 @PCA1] and second pixel driving circuits [fig. 7 @PCA2] distributed at intervals along the second direction [fig. 7 @DR2],
the second direction [fig. 7 @DR2] intersects [fig. 7 illustrates] with the first direction [fig. 7 @DR1], and the display panel further comprises:
a base substrate [fig. 9 @SUB];
a pixel column [fig. 7 @PCA1-PCA3] corresponds to one of the first data signal lines [fig. 7 @DL1 (n+1] and one of the second data signal lines [fig. 7 @DL2 (n+1)], and
the first data signal line [fig. 5 @DL1] and the second data signal line [fig. 5 @DL2] are arranged on both sides of the pixel column that the first data signal line and the second data signal line correspond to [fig. 7 illustrates DL1(n+1) and DL2(n+1) bounding a pixel column defined by PCA1, PCA2 and PCA3], and wherein
the first data signal line [fig. 5 @DL1(n)] is connected [¶0115, “… Contacts of the first data lines DL1 … and may be electrically connected to the first pixel circuits”], to the first pixel driving circuits [fig. @PCA1], and the second data signal line [fig. 5 @DL2(n)] is connected [¶0116, “… The second data lines DL2 may provide the second data voltage Vdata2 to the second pixel circuits”] to the second pixel driving circuits [fig. 7 @PCA2]; and wherein
at least some of the data signal lines [fig. 3 @DL1(n) and DL1(n+3)] far away from a middle area of the display panel [construed as fig. 3 @DL] are connected to the fan-out transposition lines [fig. 3 @FL], and
[¶0088, “The fan-out lines FL may extend from the display driver 200 to the display area DA. The fan-out lines FL may provide the data voltage received from the display driver 200 to the data lines DL”]
Kim does not teach a first metal layer located on a side of the base substrate, wherein the first metal layer comprises multiple fan-out transposition lines, and orthographic projections on the base substrate of the multiple fan-out transposition lines extend along the first direction; and a second metal layer located on a side of the first metal layer away from the base substrate, wherein the second metal layer comprises multiple data signal lines and multiple data fan-out lines, orthographic projections on the base substrate of the multiple data signal lines extend along the second direction and are distributed at intervals along the first direction, and orthographic projections on the base substrate of the multiple data fan-out lines extend along the second direction and are distributed at intervals along the first direction; wherein the multiple data signal lines comprise multiple first data signal lines and multiple second data signal lines alternately distributed along the first direction
Choi teaches a first metal layer [fig. 27 @DTL2] located on a side [top] of the base substrate [fig. 3 @SUB],
wherein the first metal layer [fig. 27 @DTL2] comprises multiple fan-out transposition lines [figs. 25 @DCL2], and
orthographic projections on the base substrate of the multiple fan-out transposition lines [figs. 4 @DCL2] extend along the first direction [fig. 4 @DR1];
and a second metal layer [figs. 26 and 27 @DTL3] located on a side [fig. 29 illustrates] of the first metal layer away [fig. 27 @DTL2] from the base substrate [fig. 3 @SUB], wherein
the second metal layer [figs. 26 and 27 @DTL3] comprises multiple data signal lines [fig. 26 @DL] and multiple data fan-out lines [fig. 27 @DCL1],
orthographic projections on the base substrate of the multiple data signal lines [fig. 25 @DL] extend along the second direction [fig. 25 @DR2] and are distributed at intervals along the first direction [fig. 25 @DR1], and
orthographic projections on the base substrate of the multiple data fan-out lines [fig. 25 @DCL1] extend along the second direction [fig. 25 @DR2] and are distributed at intervals along the first direction [fig. 25 @DR1]; wherein
the multiple data signal lines [fig. 4 @DL] comprise multiple first data signal lines [fig. 4 @DL1] and multiple second data signal lines [fig. 4 @DL2] alternately distributed along the first direction [fig. 4 @DR1],
a first metal layer [fig. 27 @DTL2] located on a side [top] of the base substrate [fig. 3 @SUB],
wherein the first metal layer [fig. 31 @GTL1] comprises multiple fan-out transposition lines [figs. 25 @DCL2], and
orthographic projections on the base substrate of the multiple fan-out transposition lines [figs. 4 @DCL2] extend along the first direction [fig. 4 @DR1];
and a second metal layer [figs. 26 and 27 @DTL3] located on a side [fig. 29 illustrates] of the first metal layer away [fig. 27 @DTL2] from the base substrate [fig. 9 @SUB], wherein
the second metal layer [figs. 26 and 27 @DTL3] comprises multiple data signal lines [fig. 26 @DL2] and multiple data fan-out lines [fig. 27 @DCL1],
orthographic projections on the base substrate of the multiple data signal lines [fig. 25 @DL2] extend along the second direction [fig. 25 @DR2] and are distributed at intervals along the first direction [fig. 25 @DR1], and
orthographic projections on the base substrate of the multiple data fan-out lines [fig. 25 @DCL1] extend along the second direction [fig. 25 @DR2] and are distributed at intervals along the first direction [fig. 25 @DR1]; wherein
the multiple data signal lines [fig. 4 @DL] comprise multiple first data signal lines [fig. 4 @DL1] and multiple second data signal lines [fig. 4 @DL2] alternately distributed along the first direction [fig. 4 @DR1],
the fan-out transposition lines [fig. 9 @DCL2] are further connected [fig. 9 @CH1] to the data fan-out lines [fig. 9 @DCL1] close to the middle area of the display panel [fig. 4 illustrates several connections between DCL1 and DCL2 near the centerline of the display panel]
Before the application was filed it would have been obvious to one of ordinary skill in the art to incorporate data connection lines extending in the vertical and horizontal direction, as taught by Choi, into the display panel taught by Kim to reduce the number of fan-out lines required to supply data signals from a display driving circuit and thereby reduce the non-display space required for fan-out lines.
Claims 2 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Choi and Roh (US 2024/0046873). All reference is to Kim unless otherwise indicated.
Regarding Claim 2 (Original), Kim in view of Choi teaches the display panel according to Claim 1, wherein
the first direction [fig. 7 @DR1] is a row direction, the second direction [fig. 7 @DR2] is a column direction, and the display panel further comprises:
an active layer [Choi: fig. 27 @ACT] located between the base substrate [Choi: fig. 27 @SUB] and the first metal layer [Choi: fig. 27 @DTL2],
an orthographic projection on the base substrate [Choi: fig. 27 @SUB] of a data fan-out line [Choi: fig. 27 @DCL1] is located on an orthographic projection on the base substrate [Choi: fig. 27 @SUB] of a semiconductor unit [Choi: fig. 27 @ACT] in a pixel column that the data fan-out line corresponds to [Choi: fig. 7 illustrates DCL1 in pixel column formed between DL1 and DL2]
Kim in view of Choi does not teach the active layer comprises multiple semiconductor units arranged in an array along the row direction and the column direction, and one of the semiconductor units corresponds to one of the pixel driving circuits
Roh teaches an active layer comprises multiple semiconductor units [fig. 13A @SMT illustrates pixel circuit semiconductor unit] arranged in an array along a row direction and a column direction [fig. 5 illustrates pixel circuits in row and column array], and
one of the semiconductor units [fig. 13A @SMT] corresponds to one of the pixel driving circuits [fig. 13A @PC]
Before the application was filed it would have been obvious to one of ordinary skill in the art to incorporate identical semiconductor units in each pixel circuit, as taught by Roh, into the display panel taught by Kim in view of Choi in order to standardize the layout of the panel semiconductor material reducing the probability of a layout error.
Regarding Claim 12 (Original), Kim in view of Choi teaches the display panel according to Claim 1, wherein
the first direction [fig. 7 @DR1] is a row direction, the second direction [fig. 7 @DR2] is a column direction, and the display panel further comprises:
an active layer [Choi: fig. 27 @ACT] located between the base substrate [Choi: fig. 27 @SUB] and the first metal layer [Choi: fig. 27 @DTL2], wherein
an orthographic projection on the base substrate [Choi: fig. 27 @SUB] of a data fan-out line [Choi: figs. 4 and 27 @DCL1] is located between orthographic projections on the base substrate of two adjacent columns of pixel circuits semiconductor units [fig. 4 illustrates DCL1 extends in the same pixel column]
Kim in view of Choi does not teach the active layer comprises multiple semiconductor units arranged in an array along the row direction and the column direction, and one of the semiconductor units corresponds to one of the pixel driving circuits
Roh teaches an active layer comprises multiple semiconductor units [fig. 13A @SMT illustrates pixel circuit semiconductor unit] arranged in an array along a row direction and a column direction [fig. 5 illustrates pixel circuits in row and column array], and
one of the semiconductor units [fig. 13A @SMT] corresponds to one of the pixel driving circuits [fig. 13A @PC]
Before the application was filed it would have been obvious to one of ordinary skill in the art to incorporate identical semiconductor units in each pixel circuit, as taught by Roh, into the display panel taught by Kim in view of Choi in order to standardize the layout of the panel semiconductor material reducing the probability of a layout error.
Claims 3-4, 13, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Choi, Roh and Kim (US 2023/0230533) hereinafter Kim ‘533. All reference is to Kim unless otherwise indicated.
Regarding Claim 3 (Currently Amended), Kim in view of Choi and Roh teaches the display panel according to Claim 2, further comprising:
multiple light-emitting devices [fig. 8 @ED], wherein
second electrodes of the multiple light-emitting devices are connected to a second power supply terminal [fig. 8 @VSSL]; and wherein the second metal layer [figs. 26 and 27 @DTL3] further comprises:
multiple second power transposition lines [fig. 9 @ANE, fig. 7 illustrates eight], wherein
orthographic projections on the base substrate of the multiple second power transposition lines [Choi: figs. 4 and 8 @VPL1, ¶0133, “… A first power supply voltage may be applied to each of the first power supply lines PL1, and a second power supply voltage higher than the first power supply voltage may be applied to each of the second power supply lines PL2”] extend along the column direction [Choi: figs. 4 and 8 @DR2] and are distributed at intervals along the row direction [Choi: ¶0128, “… The first vertical power supply lines VPL1 may extend in the second direction DR2 and may be arranged in the first direction DR1”], and
some of the second power transposition lines [Choi: fig. 4 @ VPL1] and some of the data fan-out lines [Choi: fig. 4 @DCL1] are located in the same pixel columns and are not connected with the data fan-out lines [Choi: fig. 4 illustrates VPL1 and DCL1 located in same column and VPL1 is not connected to DCL1],
and some of the second power transposition lines [Choi: fig. 4 @ VPL1] and some of the data fan-out lines are located in different pixel columns [Choi: fig. 4 @DCL1]; and wherein
the second power transposition lines [Choi: fig. 4 @DCL1] are connected to a second power line [Choi: fig. 4 @PL1] in a non-display area of the display panel [Choi: fig. 4 illustrates claimed structure], and
the second power line is used to provide the second power supply terminal [Choi: ¶0133]
Kim in view of Choi and Roh does not teach an orthographic projection on the base substrate of a second power transposition line is located on an orthographic projection on the base substrate of a semiconductor unit in a pixel column that the second power transposition line corresponds to
Kim ‘533 teaches an orthographic projection on the base substrate of a second power transposition line [fig. 6 @VDCE, fig. 6 is an orthographic projection of components in fig. 6 on the substrate] is located on [fig. 6 illustrates claimed alignment] an orthographic projection on the base substrate of a semiconductor unit [figs. 6 and 7 @AP1] in a pixel column that the second power transposition line corresponds to
Before the application was filed it would have been obvious to one of ordinary skill in the art to place second power transposition lines over a semiconductor unit, as taught by Kim ‘533 into the display panel taught by Kim in view of Choi and Roh, in order to reduce resistance between the light emitting element anode and the second power supply thereby reducing I2R losses when current flows through the light emitting element (Kim ’533: ¶0168).
Regarding Claim 4 (Original), Kim in view of Choi, Roh and Kim ‘553 teaches the display panel according to Claim 3, wherein
the first metal layer [fig. 9 @SDL1] is a first source-drain metal layer [¶0146, “… the first source metal layer SDL1”], and
the second metal layer [fig. 9 @SDL2] is a second source-drain metal layer [¶0147, “a second source metal layer SDL2]; and wherein
a column of semiconductor units [Roh teaches a semiconductor unit (fig. 13A @SMT) corresponds to a pixel circuit (Roh: fig. 13A @PC, Choi (fig. 4) teaches data fan-out lines correspond to pixel circuits] corresponds to one of the data fan-out lines [Choi: fig. 4 @DCL1] and/or one of the second power transposition lines [alternate limitation not addressed
Regarding Claim 13 (Currently Amended), Kim in view of Choi and Roh teaches the display panel according to Claim 12, further comprising:
multiple light-emitting devices [fig. 8 @ED], wherein
second electrodes of the multiple light-emitting devices are connected to a second power supply terminal [fig. 8 @VSSL]; and wherein the second metal layer [figs. 26 and 27 @DTL3] further comprises:
multiple second power transposition lines [fig. 9 @ANE, fig. 7 illustrates eight], wherein
orthographic projections on the base substrate of the multiple second power transposition lines [Choi: figs. 4 and 8 @VPL1, ¶0133, “… A first power supply voltage may be applied to each of the first power supply lines PL1, and a second power supply voltage higher than the first power supply voltage may be applied to each of the second power supply lines PL2”] extend along the column direction [Choi: figs. 4 and 8 @DR2] and are distributed at intervals along the row direction [Choi: ¶0128, “… The first vertical power supply lines VPL1 may extend in the second direction DR2 and may be arranged in the first direction DR1”], and
some of the second power transposition lines [Choi: fig. 4 @ VPL1] and some of the data fan-out lines [Choi: fig. 4 @DCL1] are located in the same pixel columns and are not connected with the data fan-out lines [Choi: fig. 4 illustrates VPL1 and DCL1 located in same column and VPL1 is not connected to DCL1],
and some of the second power transposition lines [Choi: fig. 4 @ VPL1] and some of the data fan-out lines are located in different pixel columns [Choi: fig. 4 @DCL1]; and wherein
the second power transposition lines [Choi: fig. 4 @DCL1] are connected to a second power line [Choi: fig. 4 @PL1] in a non-display area of the display panel [Choi: fig. 4 illustrates claimed structure], and
the second power line is used to provide the second power supply terminal [Choi: ¶0133]
Kim in view of Choi and Roh does not teach an orthographic projection on the base substrate of a second power transposition line is located between the orthographic projections on the base substrate of two adjacent columns of semiconductor units
Kim ‘533 teaches an orthographic projection on the base substrate of a second power transposition line [fig. 6 @VDCE, fig. 6 is an orthographic projection of components in fig. 6 on the substrate] is located [fig. 7 teaches a second power transposition line (fig. 6 @VDCE) is within the pixel circuit of a center pixel column therefore the orthographic projection on the middle semiconductor unit is between the orthographic projections of semiconductor units in adjacent columns] between the orthographic projections on the base substrate of two adjacent columns of semiconductor units [figs. 6 and 7 @AP1 illustrates a center column]
Before the application was filed it would have been obvious to one of ordinary skill in the art to place second power transposition lines over a semiconductor unit, as taught by Kim ‘533 into the display panel taught by Kim in view of Choi and Roh, in order to reduce resistance between the light emitting element anode and the second power supply thereby reducing I2R losses when current flows through the light emitting element (Kim ’533: ¶0168).
Regarding Claim 17 (Currently Amended), Kim in view of Choi, Roh and Kim ‘533 teaches the display panel according to Claim 4, wherein the semiconductor unit comprises:
a third active part [Roh: fig. 13A @A1] used to form a channel region of a driving transistor [Roh: fig. 7 @T1];
a fourth active part [Roh: fig. 13A @A2] used to form a channel region of a fourth transistor [Roh: fig. 7 @T2]; and
a fourteenth active part [Roh: fig. 13A @S2] connected to a side of the fourth active part, and used to form a first electrode of the fourth transistor [Roh: figs. 7 and 13A @T2]; wherein the first metal layer [Roh: fig. 13E @EPT2] further comprises:
a data transposition part [Roh: ¶0094, “lines connecting the data lines DLr, DLb, and DLg and the pixel circuits PC1, PC2, and PC3 may be defined as the second connection lines CL2”] connected to the fourteenth active part [Roh: ¶0214, “The data line DL may be connected to the second transistor T2. As an example, the data line DL may be connected to the second source area S2 of the second transistor T2 via a second-first contact hole CH2-1”]; and wherein
a fourth active part [Roh: fig. 13A @A2] located in at least one of the first pixel driving circuits [Roh: fig. 5 @PC1] and a fourth active part [Roh: fig. 13A @A2] located in at least one of the second pixel driving circuits [Roh: fig. 5 @PC2] are located on both sides of the third active part [Roh: fig. 13A @A1] along the row direction [Roh: fig. 5 @DR2],
the first data signal line [Roh: fig. 5 @DLr] is connected to the data transposition part [Roh: ¶0094] in the first pixel driving circuit [Roh: fig. 5 @PC1], and the second data signal line [Roh: fig. 5 @DLg] is connected to the data transposition part [Roh: ¶0094] in the second pixel driving circuit [Roh: fig. 5 @PC2].
Allowable Subject Matter
Claims 5-11,14-16, and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Douglas Wilson whose telephone number is (571)272-5640. The Examiner can normally be reached 1000-1700 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Patrick Edouard can be reached at 571-272-7603. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Douglas Wilson/Primary Examiner, Art Unit 2622