DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 03/10/2026 have been fully considered but they are not persuasive.
As per claim 1, Applicant argues that the previously cited prior art does not teach wherein the test circuit forms a loop structure with the second control assembly via the electrical connection at the first ends of the two first test lines.
The Office respectfully disagrees and submits that the previously cited Wu et al. teach the test circuit (Wu, Fig. 1, second test point 31) forms a loop structure with the second control assembly (Gu, Fig. 1, source drivers 103/Wu, Fig. 1, source drivers 50) via the electrical connection at the first ends of the two first test lines (Wu, Fig. 1, first test points, paragraph 20, "the first test point and the second test point are coupled to an external test apparatus to measure a waveform and a sequence of the control signal in real time"; paragraph 30, "The sequence controller 11 ... transmits the coded control signal from the first circuit board 10 to the source driving circuit 50 through the second circuit board 30. Meanwhile, the sequence controller 11 also outputs the uncoded control signal to the first test point 13"; paragraph 33, "the uncoded control signal through the first circuit board 10 and the decoded control signal through the second circuit board 30 are compared to determine the phase delay relationship of the two", in other words, a test apparatus closes the circuit to form a loop between first and second test points so as to measure a phase delay, and the second control assembly (Gu, Fig. 1, source drivers 103/Wu, Fig. 1, source drivers 50) is disposed within said loop between the first and second test points).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 10, 11, 13, 14 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0206821 to Gu et al.; in view of US 2005/0285832 to Shin et al.; further in view of US 2017/0084236 to Wu et al.
As per claim 1, Gu et al., teach a display device, comprising: a display panel (Fig. 1, 102), a first control assembly (Fig. 1, 101), a connection circuit (Fig. 1, paragraph 40, see mini-LVDS interface withing timing controller 101), and a second control assembly (Fig. 1, source drivers 103), wherein
the display panel (Fig. 1, 102) is connected to the first control assembly (Fig. 1, timing controller 101), one end of the connection circuit is connected to the first control assembly (paragraph 39, “The timing controller 101 may convert the received image signal into a mini-LVDS signal (mini-low voltage differential signal), then supply the mini-LVDS signal to the source driver 103”), and another end of the connection circuit is connected to the second control assembly (Fig. 1, LLV and RLV lines are connected between LVDS interface a source driver 102).
the connection circuit (Fig. 1, mini-LVDS interface) comprises a signal transmission line disposed on the connection circuit, and the signal transmission line is configured to transmit signals between the first control assembly (Fig. 1, 101) and the second control assembly (Fig. 1, source driver 103, notice that lines connecting the drivers 103 and the mini-LVDS interface must be at least partially disposed on said mini-LVDS interface); and
determine a length of the connection circuit in a first direction (paragraph 75, “a length of a line from the timing controller to each source driver is different … Therefore … the source drivers may perform phase correction on the display data signals”, a length dependent correction implies knowledge/determination of the line length), and determine a phase of a sampling clock based on the length of the connection circuit in the first direction (paragraph 40, “Each group of signal pairs is accompanied by a clock signal pair; the clock signal pair is a differential signal pair just like the video data signal, and signals are transmitted on both a rising edge and a falling edge of the clock signal”; paragraph 75, “a length of a line from the timing controller to each source driver is different, phase difference information of pixel data signals arriving at different source drivers is different. Therefore, after converting the pixel data signals into the display data signals by the source drivers and before sending the display data signals to the display panel, the source drivers may perform phase correction on the display data signals again, to reduce the second phase difference of the display data signals supplied to the display panel”, in other words, the phase correction process requires, at least indirectly, a determination of the length of the connection circuit, among other factors affecting phase delay differences).
Gu et al. do not explicitly teach wherein the connection circuit is a board comprising a board body.
Shin et al. suggest wherein the connection circuit is board comprising a board body (Fig. 5, paragraph 49, “the LVDS transmitter 12a can be formed as a single chip set or as separate chip sets”).
It would have been obvious to one of ordinary skill in the art, to modify the device of Gu et al., so that the connection circuit is a board comprising a board body, such as taught by Shin et al., for the purpose of interfacing the timing controller and source driver.
Gu and Shin et al. do not explicitly teach wherein the connection circuit board comprises a test circuit, wherein the test circuit comprises two first test lines extending in a first direction, first ends of the two first test lines are electrically connected and are disposed on a side of the connection circuit board proximate to the first control assembly, second ends of the two first test lines are disposed on a side of the connection circuit board proximate to the second control assembly and are connected to the second control assembly, the test circuit forms a loop structure with the second control assembly via the electrical connection at the first ends of the two first test lines, the first direction being parallel to the signal transmission line; the second control assembly is configured to: transmit a test signal to a second end of one first test line in the two first test lines and receive the test signal from a second end of another first test line in the two first test lines, determine the length based on a transmitting moment and a receiving moment of the test signal, and determine the phase of the sampling clock based on the length.
Wu et al. suggest wherein the connection circuit board comprises a test circuit (Fig. 1, second test point 31 is analogous to an LVDS receiver chip test at the source driver side of the circuit of Gu and Shin), wherein the test circuit comprises two first test lines (paragraph 31, “In this preferred embodiment, the control signal comprises a data source row latch signal (TP) and a signal (POL) controlling polarity reversal of a pixel voltage. Correspondingly, the amount of the first test points 13 is two”) extending in a first direction (Fig. 1 lines extend in a direction between the source driving circuit and the sequence controller) first ends of the two first test lines are electrically connected and are disposed on a side of the connection circuit board proximate to the first control assembly (Fig. 1, two first test points are disposed on the timing controller/”first circuit board” side), second ends of the two first test lines are disposed on a side of the connection circuit board proximate to the second control assembly and are connected to the second control assembly (Fig. 1, two second test points are disposed on the source driver side), the test circuit (Wu, Fig. 1, second test point 31) forms a loop structure with the second control assembly (Gu, Fig. 1, source drivers 103/Wu, Fig. 1, source drivers 50) via the electrical connection at the first ends of the two first test lines (Wu, Fig. 1, first test points, paragraph 20, "the first test point and the second test point are coupled to an external test apparatus to measure a waveform and a sequence of the control signal in real time"; paragraph 30, "The sequence controller 11 ... transmits the coded control signal from the first circuit board 10 to the source driving circuit 50 through the second circuit board 30. Meanwhile, the sequence controller 11 also outputs the uncoded control signal to the first test point 13"; paragraph 33, "the uncoded control signal through the first circuit board 10 and the decoded control signal through the second circuit board 30 are compared to determine the phase delay relationship of the two", in other words, a test apparatus closes the circuit to form a loop between first and second test points so as to measure a phase delay, and the second control assembly (Gu, Fig. 1, source drivers 103/Wu, Fig. 1, source drivers 50) is disposed within said loop between the first and second test points), the first direction being parallel to the signal transmission line (Fig. 1, at least part of the test lines extends in the same direction as the signal transmission line, i.e., line between sequence controller 11 and source driving circuit 50);
the second control assembly is configured to: transmit a test signal (Fig. 1, paragraphs 7 and 31, a decoded signal transmitted to first-second test point 31 and second-second test point 31 will be construed as the claimed test signal) to a second end of one first test line in the two first test lines (Fig. 1, the test signal is at least partially transmitted to first-second test point 31) and receive the test signal from a second end of another first test line in the two first test lines (Fig. 1, the test signal is at least partially received at second-second test point 31), determine the length based on a transmitting moment and a receiving moment of the test signal, and determine the phase of the sampling clock based on the length (paragraph 7, “The source driving circuit receives the control signal and decodes the same, and outputs the decoded control signal through the second circuit board; after the uncoded control signal through the first circuit board and the decoded control signal through the second circuit board are compared to determine the phase delay relationship of the two, the control signal received by the source driving circuit is restored in real time according to the phase delay relationship, or the control signal subsequently outputted by the sequence controller is adjusted according to the phase delay relationship.”, notice that the phase delay calculation requires the length of the lines to be determined at least indirectly, given that said delay is at least indirectly dependent on said line length, among other factors).
It would have been obvious to one of ordinary skill in the art, to modify the device of Gu and Shin et al. so that the connection circuit board comprises a test circuit, wherein the test circuit comprises two first test lines extending in a first direction, first ends of the two first test lines are electrically connected and are disposed on a side of the connection circuit board proximate to the first control assembly, second ends of the two first test lines are disposed on a side of the connection circuit board proximate to the second control assembly and are connected to the second control assembly, the test circuit forms a loop structure with the second control assembly via the electrical connection at the first ends of the two first test lines, the first direction being parallel to the signal transmission line; the second control assembly is configured to: transmit a test signal to a second end of one first test line in the two first test lines and receive the test signal from a second end of another first test line in the two first test lines, determine the length based on a transmitting moment and a receiving moment of the test signal, and determine the phase of the sampling clock based on the length, such as taught by Wu et al., for the purpose of ensuring display quality and uniformity by performing impedance and RC delay matching so as to compensate for line length and capacitive load variations.
As per claim 10, Gu, Shin and Wu et al. teach the display device according to claim 1, wherein the second control assembly (Gu et al., Fig. 1, source drivers 103) comprises a second circuit board (Wu, Fig. 1, the combination of source driving circuit 50 and ”second board 30” will be construed as the claimed second circuit board), and connection lines (Wu, Fig. 1, (implied) connection between the lines into the source driving circuit and the lines out of the source driving circuit going into the second test points) and a second controller (Wu, source driver 50; Gu, Fig. 1, individual source drivers 101) disposed on the second circuit board, the second controller being electrically connected to the second ends of the two first test lines via the connection lines; wherein the connection lines are further connected to the first ends of the two first test lines (Wu, Fig. 1).
As per claim 11, Gu, Shin and Wu et al. teach the display device according to claim 10, wherein the second circuit board (Wu, Fig. 1, the combination of source driving circuit 50 and ”second board 30”) is provided with an edge region connected to the connection circuit board, the second controller being disposed in the edge region (Wu, source driver 50; Gu, Fig. 1, individual source drivers 101, the location of the source drivers will be construed as the claimed “edge region”).
As per claim 13, Gu, Shin and Wu et al. teach a method for controlling a display device, applicable to the second control assembly in the display device as defined in any one of claims 1, the method comprising:
transmitting the test signal to the second end of one first test line in the two first test lines in the display device; receiving the test signal from the second end of another first test line in the two first test lines (Fig. 1, two second test points are disposed on the source driver side);
determining the length of the connection circuit board in the first direction based on the transmitting moment and the receiving moment of the test signal; and determining the phase of the sampling clock based on the length of the connection circuit board in the first direction (Wu, paragraph 7, “The source driving circuit receives the control signal and decodes the same, and outputs the decoded control signal through the second circuit board; after the uncoded control signal through the first circuit board and the decoded control signal through the second circuit board are compared to determine the phase delay relationship of the two, the control signal received by the source driving circuit is restored in real time according to the phase delay relationship, or the control signal subsequently outputted by the sequence controller is adjusted according to the phase delay relationship.”, notice that the phase delay calculation requires the length of the lines to be determined at least indirectly, given that said delay is at least indirectly dependent on said line length, among other factors).
As per claim 14, Gu, Shin and Wu et al. teach the method according to claim 13, wherein determining the length of the connection circuit board in the first direction based on the transmitting moment and the receiving moment of the test signal comprises: determining a transmission duration of the test signal in the test circuit based on the transmitting moment and the receiving moment of the test signal (Wu, paragraph 7, “determine the phase delay relationship of the two”, notice that the phase delay is a measurement of the duration between transmission and reception of a signal); and determining the length of the connection circuit board in the first direction based on the transmission duration and a transmission speed of the test signal in the test circuit (paragraph 40, “Each group of signal pairs is accompanied by a clock signal pair; the clock signal pair is a differential signal pair just like the video data signal, and signals are transmitted on both a rising edge and a falling edge of the clock signal”; paragraph 75, “a length of a line from the timing controller to each source driver is different, phase difference information of pixel data signals arriving at different source drivers is different. Therefore, after converting the pixel data signals into the display data signals by the source drivers and before sending the display data signals to the display panel, the source drivers may perform phase correction on the display data signals again, to reduce the second phase difference of the display data signals supplied to the display panel”, in other words, the phase correction process requires, at least indirectly, a determination of the length of the connection circuit, said length is further based in the transmission speed and duration of the tested signal).
As per claim 17, Gu, Shin and Wu et al. teach the method according to claim 13, wherein receiving the test signal from the second end of another first test line in the two first test lines comprises: acquiring the test signal by sampling the second end of another first test line in the two first test lines by a sampling clock of a preset frequency (Gu, paragraph 43, “bits of pixel data signals are sampled in each clock cycle through clock dual-edge sampling, so the frequency of the clock signal is 3 times the frequency of the pixel data signal”).
Claims 9 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0206821 to Gu et al.; in view of US 2005/0285832 to Shin et al.; further in view of US 2017/0084236 to Wu et al.; further in view of US 2002/0008682 to Park.
As per claim 9, Gu, Shin and Wu et al. teach the display device according to claim 1.
Gu, Shin and Wu et al. do not teach wherein the first control assembly comprises a first circuit board the first control assembly comprising a fifth connection structure, and a plurality of first controllers, the fifth connection structure being disposed on the first circuit board and the plurality of first controllers being electrically connected to the first circuit board; wherein the fifth connection structure is connected to the first ends of the two first test lines.
Park suggests wherein the first control assembly (Fig. 1, 24/22a/22b are analogous to the first control assembly of Gu, Shin and Wu et al.) comprises a first circuit board (Fig. 1, 24), a fifth connection structure (Fig. 1, 26), and a plurality of first controllers (Fig. 1, timing controllers 22a/22b), the fifth connection structure being disposed on the first circuit board and the plurality of first controllers being electrically connected to the first circuit board; wherein the fifth connection structure (Fig. 1, 26) is connected to the first ends of the two first test lines (Fig. 1, notice that the distribution block 26, when used to modify the timing controller of Gu, Shin and Wu et al., also provides the data for the mini-LVDS block and is at least indirectly connected to the test lines).
It would have been obvious to one of ordinary skill in the art, to modify the device of Gu, Shin and Wu et al., so that the first control assembly comprises a first circuit board the first control assembly comprising a fifth connection structure, and a plurality of first controllers, the fifth connection structure being disposed on the first circuit board and the plurality of first controllers being electrically connected to the first circuit board; wherein the fifth connection structure is connected to the first ends of the two first test lines, such as taught by Park, for the purpose of effectively driving large sized displays.
As per claim 12, Gu, Shin and Wu et al. teach the display device according to claim 1, wherein the first control assembly is a source driver control assembly (Fig. 1, timing controller 101 controls the source drivers) and the second controller second control assembly is a timing control assembly (Fig. 1, source drivers 103 receive timing signals from the timing controller).
Gu, Shin and Wu et al. do not explicitly teach wherein the connection circuit board comprises a flexible circuit board.
Park teaches wherein the connection circuit board comprises a flexible circuit board (paragraph 25).
It would have been obvious to one of ordinary skill in the art, to modify the device of Gu, Shin and Wu et al., so that the connection circuit board comprises a flexible circuit board, such as taught by Park, for the purpose of effectively driving large sized displays.
Allowable Subject Matter
Claims 2-8, 15, 16, 19 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JOSE R SOTO LOPEZ/Primary Examiner, Art Unit 2622
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