Prosecution Insights
Last updated: July 17, 2026
Application No. 18/993,727

RECORDING AND RECOVERY OF SIGNALS DURING STIMULATION

Non-Final OA §102§103§112
Filed
Jan 13, 2025
Priority
Jul 22, 2022 — provisional 63/391,562 +1 more
Examiner
KUO, JONATHAN T
Art Unit
Tech Center
Assignee
Emory University
OA Round
1 (Non-Final)
72%
Grant Probability
Favorable
1-2
OA Rounds
1y 5m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allowance Rate
342 granted / 474 resolved
+12.2% vs TC avg
Strong +28% interview lift
Without
With
+28.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
37 currently pending
Career history
507
Total Applications
across all art units

Statute-Specific Performance

§101
1.1%
-38.9% vs TC avg
§103
87.4%
+47.4% vs TC avg
§102
5.5%
-34.5% vs TC avg
§112
3.0%
-37.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 474 resolved cases

Office Action

§102 §103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 16 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 16 recites the limitation "further comprises a ground port" in line 2. However, claim 10 on which the instant claim depends from already recites “a ground port” in line 4. It is unclear and thus indefinite whether there are two separate ground ports or if claim 16’s instance of “ground port” refers to the same element as claim 10’s “ground port”. For examination purposes below, it will be assumed they are the same element. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 2, 6-8, 10, 11, 15-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wilder (US 20210346700 A1; 11/11/2021). Regarding claim 1, Wilder teaches a device for recording a signal at a stimulating electrode (Abstract; Fig. 1), the device comprising: a stimulator port operably connected to a stimulator decoupler stage (Fig. 2A-4; Fig. 8); an input port operably connected to the stimulator decoupler stage and a current limiter stage, wherein the current limiter stage is configured to limit a current flowing from the input port to a recording port and wherein the stimulator decoupler stage is configured to prevent a loading effect on an input port of a recording amplifier (Fig. 2A-4; Fig. 8; Fig. 12; [0040] “Interface control subsystem 410 may preset a low impedance and low noise path to the recording circuit when stimulation signals are not present”; [0041] “specific impedance may be selected to match the amplitude of the stimulation currents”; [0068]); and a voltage range limiter stage operably connected to the current limiter stage and the recording port and configured to limit a voltage output to a predetermined recording amplifier range (Fig. 12; [0023] “limit voltage”; [0030]; [0039]; [0054] “voltage between the electrode terminal and the recording terminal is limited”; [0057]). Regarding claim 2, Wilder teaches wherein the stimulator decoupler stage comprises a pair of antiparallel diodes connected in parallel (Fig. 12, 1228; [0063]). Regarding claim 6, Wilder teaches wherein the voltage range limiter stage comprises a pair of antiparallel diodes connected in parallel (Fig. 12, 1228; [0063]). Regarding claim 7, Wilder teaches wherein the device further comprises a ground port, and the voltage range limiter stage is operably connected between the ground port and the recording port (Fig. 2A-4; Fig. 8; Fig. 12). Regarding claim 8, Wilder teaches wherein the device is configured to receive an electrophysiology signal (Abstract; Fig. 1; [0026]). Regarding claim 10, Wilder teaches a system for simultaneously stimulating and recording data using an electrode (Abstract; Fig. 1), the system comprising: a stimulator port operably connected to a stimulator decoupler stage (Fig. 2A-4; Fig. 8); a ground port (Fig. 2A-4; Fig. 8; Fig. 12); an input port operably connected to the stimulator decoupler stage and a current limiter stage, wherein the current limiter stage is configured to limit a current flowing from the input port to a recording port and wherein the stimulator decoupler stage is configured to prevent a loading effect on an input port of a recording amplifier wherein the recording amplifier is operably connected to the recording port and the ground port (Fig. 2A-4; Fig. 8; Fig. 12; [0040] “Interface control subsystem 410 may preset a low impedance and low noise path to the recording circuit when stimulation signals are not present”; [0041] “specific impedance may be selected to match the amplitude of the stimulation currents”; [0068]); a probe comprising one or more electrodes operably connected to the input port (Fig. 1; [0024] “implant”; [0026]-[0027]); a voltage range limiter stage operably connected to the current limiter stage and the recording port and configured to limit a voltage output to a predetermined recording amplifier range (Fig. 12; [0023] “limit voltage”; [0030]; [0039]; [0054] “voltage between the electrode terminal and the recording terminal is limited”; [0057]); and a stimulator operably connected to the stimulator port (Fig. 1; [0028]-[0030]). Regarding claim 11, Wilder teaches wherein the stimulator decoupler stage comprises a pair of antiparallel diodes connected in parallel (Fig. 12, 1228; [0063]). Regarding claim 15, Wilder teaches wherein the voltage range limiter stage comprises a pair of antiparallel diodes connected in parallel. (Fig. 12, 1228; [0063]). Regarding claim 16, Wilder teaches wherein the system further comprises a ground port, and the voltage range limiter stage is operably connected between the ground port and the recording port (Fig. 2A-4; Fig. 8; Fig. 12). Regarding claim 17, Wilder teaches wherein the stimulator and recording amplifier are a combined stimulator and recording amplifier ([0029]). Regarding claim 18, Wilder teaches herein the stimulator, recording amplifier, voltage range limiter stage, current limiter stage, and stimulator decoupler stage are part of a single device (Fig. 2A-4; Fig. 8; Fig. 12). Regarding claim 19, Wilder teaches wherein the system is configured to receive an electrophysiology signal (Abstract; Fig. 1; [0026]). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 3, 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wilder as applied to claim(s) 1, 10 above. Regarding claim 3, Wilder does not teach wherein the stimulator decoupler stage comprises a plurality of antiparallel diodes connected in series. However, Wilder does teach plurality of antiparallel diodes ((Fig. 12, 1228; [0063]). It would have been obvious to connect multiple antiparallel diodes in series in order to achieve the intended effect as taught in [0063] since this is an obvious duplication of parts and/or rearrangement of parts; MPEP 2144.04. Regarding claim 12, Wilder does not teach wherein the stimulator decoupler stage comprises a first pair of antiparallel diodes that are connected in parallel, and a second pair of antiparallel diodes connected in parallel, and wherein the first and second pair of antiparallel diodes are connected in series. However, Wilder does teach plurality of antiparallel diodes ((Fig. 12, 1228; [0063]). It would have been obvious to connect multiple antiparallel diodes as needed in order to achieve the intended effect as taught in [0063] since this is an obvious duplication of parts and/or rearrangement of parts; MPEP 2144.04. Claim(s) 4-5, 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wilder as applied to claim(s) 1, 10 above evidenced by Cadence (Differences Between JFET, MESFET, MOSFET, and HEMT; https://resources.pcb.cadence.com/blog/differences-between-jfet-mesfet-mosfet-and-hemt); see MPEP 2124. Regarding claim 4, Wilder does not teach wherein the current limiter stage comprises a Junction Field Effect (JFET) constant current source, wherein the JFET constant current source comprises a JFET transistor and a resistor. However, Wilder does teach MOSFET constant current source (Fig. 5; Fig. 12; [0029] “constant current”; [0050]), wherein the MOSFET constant current source comprises a MOSFET transistor and a resistor (Fig. 6-7; Fig. 12; [0050]; [0055]-[0058]). Cadence evidences that it is known in the field that “JFETs are comparable to MOSFETs in most respects and can be a suitable replacement for a MOSFET” (p. 4 JFETs). Thus it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the teaching of Wilder to substitute JFET for MOSFET because this is a simple substitution with predictable results; MPEP 2144.06 and MPEP 2144.07. Regarding claim 5, Wilder does not teach wherein the current limiter stage comprises a plurality of JFET constant current sources. However, this would be an obvious duplication of parts as Wilder already teaches multiple constant current output drivers ([0029]); MPEP 2144.04. Regarding claim 13, Wilder does not teach wherein the current limiter stage comprises a JFET constant current source, wherein the JFET constant current source comprises a transistor and a resistor. However, Wilder does teach MOSFET constant current source (Fig. 5; Fig. 12; [0029] “constant current”; [0050]), wherein the MOSFET constant current source comprises a MOSFET transistor and a resistor (Fig. 6-7; Fig. 12; [0050]; [0055]-[0058]). Cadence evidences that it is known in the field that “JFETs are comparable to MOSFETs in most respects and can be a suitable replacement for a MOSFET” (p. 4 JFETs). Thus it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the teaching of Wilder to substitute JFET for MOSFET because this is a simple substitution with predictable results; MPEP 2144.06 and MPEP 2144.07. Regarding claim 14, Wilder does not teach wherein the current limiter stage comprises a plurality of JFET constant current sources However, this would be an obvious duplication of parts as Wilder already teaches multiple constant current output drivers ([0029]); MPEP 2144.04. Claim(s) 9, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wilder as applied to claim(s) 1, 10 above, in view of Venkatesan (US 20150165206 A1; 6/18/2015). Regarding claim 9, Wilder teaches wherein the device is configured amplify neural activity during stimulation (Fig. 1; Fig. 12; [0029] “amplification subsystem may be used to amplify signals”). Wilder does not teach during deep brain stimulation. Note that Wilder teaches a variety of applications with neural stimulation and recording such as prosthetic control ([0024]). However, Venkatesan teaches in the same field of endeavor (Abstract) during deep brain stimulation ([0043]). Thus it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the teaching of Wilder to include this feature as taught by Venkatesan because this enables monitoring for effectiveness of deep brain stimulation ([0043]). Regarding claim 20, Wilder teaches wherein the device is configured amplify neural activity during stimulation (Fig. 1; Fig. 12; [0029] “amplification subsystem may be used to amplify signals”). Wilder does not teach during deep brain stimulation. Note that Wilder teaches a variety of applications with neural stimulation and recording such as prosthetic control ([0024]). However, Venkatesan teaches in the same field of endeavor (Abstract) during deep brain stimulation ([0043]). Thus it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the teaching of Wilder to include this feature as taught by Venkatesan because this enables monitoring for effectiveness of deep brain stimulation ([0043]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jonathan T Kuo whose telephone number is (408)918-7534. The examiner can normally be reached M-F 10 a.m. - 6 p.m. PT. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Niketa Patel can be reached at 571-272-4156. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JONATHAN T KUO/Primary Examiner, Art Unit 3792
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Prosecution Timeline

Jan 13, 2025
Application Filed
Jun 23, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
72%
Grant Probability
99%
With Interview (+28.0%)
2y 11m (~1y 5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 474 resolved cases by this examiner. Grant probability derived from career allowance rate.

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