DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu, US Pub. No. 2019/0237022.
Regarding claim 1, Liu teaches a display panel (fig. 1, display panel 100), comprising a display area (fig. 1, display area AA) and pixel circuits arranged in the display area (fig. 1, pixel unit 3), wherein the display panel further comprises a drive module (fig. 1, GOA circuits 11-13) and a drive integrated circuit (IC) (fig. 1, drive chip 2); the drive module comprises a plurality of drive circuits (fig. 1, GOA circuits 11-13), and the drive circuits are configured to provide drive signals for the pixel circuits (fig. 1, pixel unit 3); the drive IC is configured to provide drive control signals for the drive circuits via gate on array (GOA) signal lines (fig. 1, drive chip 2); the GOA signal lines comprise first GOA signal lines arranged between the display area and the drive IC (fig. 1, drive signal 23); at least part of the drive circuits comprised in the drive module are arranged in the display area (fig. 1, GOA circuit 13); the at least part of the drive circuits arranged in the display area and comprised in the drive module is electrically connected to the drive IC via the first GOA signal lines (fig. 1, GOA circuit 13 connecting to drive pin 23), for receiving the drive control signals from the drive IC (fig. 1, drive chip 2); the first GOA signal lines extend in a first direction (fig. 1, GOA circuit 13 extending vertically); and the display panel further comprises data lines (fig. 2, Vdata), and the data lines are configured to provide data voltage for the pixel circuits (fig. 2, Vdata, pixel 31); the data lines extend in substantially a same direction as the first direction (fig. 2, Vdata extending vertically).
Regarding claim 2, Liu teaches wherein the at least part of the drive circuits comprised in the drive module are arranged in the middle of the display area, and the at least part of the drive circuits are aligned in the first direction (fig. 1, GOA circuits 11-13).
Regarding claim 3, Liu teaches wherein the at least part of the drive circuits comprised in the drive module are first drive circuits (fig. 1, GOA circuit 13); a plurality of drive circuits other than the first drive circuits comprised in the drive module are second drive circuits (fig. 1, GOA circuits 11 and 12); the drive IC and the first GOA signal lines are arranged on a first side of the display area (fig. 1, driver chip 2); and a plurality of second drive circuits comprised in the drive circuits are arranged on a second side and/or a third side of the display area (fig. 1, GOA circuits 11 and 12); the second side and the third side are opposite sides (fig. 1, GOA circuits 11 and 12 are on opposite sides).
Regarding claim 4, Liu teaches wherein the GOA signal lines further comprise second GOA signal lines extending in a second direction (fig. 1, driver chip 2); the first direction intersects the second direction (fig. 1, GOA 13 intersecting with driver chip 2); the first GOA signal lines are electrically connected to the second GOA signal lines (fig. 1, GOA 13 signal lines connected to driver chip 2); the second GOA signal lines are electrically connected to the drive IC (fig. 1, driver chip 2); and the second GOA signal lines are configured to receive and pass the drive control signals from the drive IC (fig. 1, driver chip 2).
Regarding claim 5, Liu teaches wherein a fan-out area, a bending area, a box-forming testing area (fig. 1, driver chip 2), and an area where the drive IC is arranged are sequentially arranged at the first side of the display area in a direction away from the display area (fig. 1, bottom area of display); and the second GOA signal lines are arranged between the bending area and the box-forming testing area (fig. 1, signal lines from driver chip 2).
Regarding claim 6, Liu teaches wherein at least part of the first GOA signal lines are directly electrically connected to the drive IC, for receiving the drive control signals from the drive IC (fig. 1, GOA signal lines 21-23 connected to driver chip 2).
Regarding claim 7, Liu teaches wherein the GOA signal lines further comprise second GOA signal lines extending in a second direction (fig. 1, GOA signal lines 21 and 22); the first direction intersects the second direction (fig. 1, driver chip 2); part of the first GOA signal lines are electrically connected to the second GOA signal lines (fig. 1, GOA signal lines 23); and the second GOA signal lines are directly electrically connected to the second drive circuits, for providing the drive control signals to the second drive circuits (fig. 1, GOA circuits 11 and 12).
Regarding claim 8, Liu teaches wherein the first GOA signal lines are electrically connected to a port located in the middle of the drive IC (fig. 1, signal pin 23).
Regarding claim 9, Liu teaches wherein the GOA signal lines further comprise second GOA signal lines, the second GOA signal lines extending in a second direction (fig. 1, GOA signal lines 21 and 22); the first direction intersects the second direction (fig. 1, driver chip 2); the first GOA signal lines are directly connected to the second GOA signal lines (fig. 1, GOA signal lines 21-23); a fan-out area, a bending area, a box-forming testing area, and an area where the drive IC is arranged are sequentially arranged at the first side of the display area in a direction away from the display area (fig. 1, driver chip 2); the second GOA signal lines are arranged in the fan-out area (fig. 1, GOA signal lines 21 and 22); and the second GOA signal lines are electrically connected to the drive IC (fig. 1, driver chip 2).
Regarding claim 10, Liu teaches wherein the plurality of second drive circuits are arranged on the second side and the third side of the display area (fig. 1, GOA circuits 11 and 12); a first end portion of the second GOA signal line is electrically connected to a second drive circuit arranged on the second side of the display area and a first port of the drive IC (fig. 1, signal pin 21); and a second end portion of the second GOA signal line is electrically connected to a second drive circuit arranged on the third side of the display area and a second port of the drive IC (fig. 1, signal pin 22).
Regarding claim 11, Liu teaches wherein the plurality of second drive circuits are arranged on the second side of the display area (fig. 1, GOA circuits 11 and 12); a first end portion of the second GOA signal line is electrically connected to a second drive circuit arranged on the second side of the display area and a first port of the drive IC (fig. 1, pin 21); or, the plurality of second drive circuits are arranged on the third side of the display area; a second end portion of the second GOA signal line is electrically connected to a drive circuit arranged on the third side of the display area and a second port of the drive IC (fig. 1, pin 22).
Regarding claim 12, Liu teaches wherein the circuit board is arranged on a side of the drive IC away from the display area (fig. 1, driver chip 2); and the circuit board is electrically connected to the first drive circuit and the second drive circuit (fig. 1, GOA circuits 11-13), for providing direct current (DC) voltage signals to the first drive circuit and the second drive circuit (fig. 2, Vdata).
Regarding claim 13, Liu teaches wherein the circuit board is further electrically connected to the drive IC, for providing DC voltage signals to the drive IC; and the drive IC is configured to generate the drive control signals according to the DC voltage signals, and provide the drive control signals to the first drive circuit and the second drive circuit (figs. 1, 2, [0024]).
Regarding claim 14, Liu teaches wherein all the drive circuits comprised in the drive module are arranged in the display area (figs. 4-5); and the first GOA signal lines are directly electrically connected to the drive IC, for receiving the drive control signals from the drive IC (fig. 1, drive chip 2).
Regarding claim 15, Liu teaches wherein the voltage signal lines are electrically connected to the drive circuits, for providing DC voltage signals to the drive circuits (fig. 2).
Regarding claim 16, Liu teaches wherein the voltage signal lines are electrically connected to the drive IC for providing DC voltage signals to the drive IC (fig. 2); and the drive IC is configured to generate the drive control signals according to the DC voltage signals, and provide the drive control signals to the drive circuits (fig. 1, GOA circuits 11-13, drive chip 2).
Regarding claim 17, Liu teaches a circuit board arranged on the drive IC away from the display area (fig. 1, drive chip 2); and the circuit board is electrically connected to the voltage signal lines, for providing the DC voltage signals to the voltage signal lines (fig. 1, signal lines 21-23).
Regarding claim 18, it is a display device of claim 1 and is rejected on the same grounds presented above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Jia et al. (US Pub. No. 2026/0057841) teaches gate drive circuits in display area to achieve a borderless display.
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/KENNETH B LEE JR/Primary Examiner, Art Unit 2625
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