DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5, 6, 8, and 20 are rejected under 35 U.S.C. 102(a) as being anticipated by Kim (US Doc. No. 20230157073).
Regarding claim 1, Kim discloses a display substrate (see Figure 1), comprising:
a base substrate (Figure 7, ‘SUB’), and power supply lines (Figure 2, VDD), data lines (‘DLj’) and a plurality of sub-pixels that are arranged on the base substrate, wherein the sub-pixel comprises a sub-pixel driving circuit (PX) and a light-emitting element coupled to each other (LD), and the sub-pixel driving circuit comprises a driving transistor (T1), a data writing transistor (T2), a first capacitor (C1) and a second capacitor (C2);
a first plate of the first capacitor is coupled to a gate electrode of the driving transistor (as shown in Figure 2 – note that the first plate of C1 is connected to the gate of T1), a second plate of the first capacitor is coupled to a second electrode of the data writing transistor (as shown in Figure 2 – note that the second plate of C1 connected to T2), and a first electrode of the data writing transistor is coupled to a corresponding one of the data lines (as shown in Figure 2 – note that T2 is also connected to DLj);
a first plate of the second capacitor is coupled to the second plate of the first capacitor (note that one leg of C1 is connected to one leg of C2), and a second plate of the second capacitor is coupled to a corresponding one of the power supply lines (note that the other leg of C2 is connected to VDD);
among sub-pixel driving circuits located in a same row along a first direction, second plates of second capacitors comprised in the sub-pixel driving circuits are arranged in sequence along the first direction, there is a spacing region between second plates of adjacent second capacitors and an orthographic projection of the data line onto the base substrate at least partially overlaps an orthographic projection of the spacing region onto the base substrate (as shown in Figure 6A – note that both plates of C2 [C2_E1 and C2_E2] are spaced apart and can be considered a ‘spacing region’ as applicable to the current terminology – note that the data lines DL do not overlap any portion of the second capacitor).
Regarding claim 5, Kim discloses all of the limitations of claim 1 as discussed in the claim 1 rejection above and further that the display substrate further comprises a plurality of first reference signal connection lines (Figure 2, VREF) and a plurality of second reference signal connection lines (Vbs), and the first reference signal connection lines and the second reference signal connection lines are alternately arranged along the first direction (as shown in Figure 6A); an orthographic projection of at least portion of the data line onto the base substrate is located between orthographic projections of the first reference signal connection line and the second reference signal connection line that are adjacent onto the base substrate (see paragraph 0211); the data line and the first reference signal connection line are arranged in different layers (see paragraph 0209); and/or the data line and the second reference signal connection line are arranged in different layers (see alternative form rejected above).
Regarding claim 6, Kim discloses all of the limitations of claim 5 as discussed in the claim 5 rejection above and further that the display substrate further comprises a plurality of first reference signal lines; the sub-pixel driving circuit further comprises a second reset transistor, a first electrode of the second reset transistor is coupled to a corresponding one of the first reference signal lines, and a second electrode of the second reset transistor is coupled to the second plate of the first capacitor; and the first reference signal connection lines are respectively coupled to the plurality of first reference signal lines (see Figure 2, elements T5 and VREF).
Regarding claim 8, Kim discloses all of the limitations of claim 5 as discussed in the claim 5 rejection above and further that the display substrate further comprises a plurality of first initialization signal connection lines and a plurality of second initialization signal connection lines, and the first initialization signal connection lines and the second initialization signal connection lines are alternately arranged along the first direction (see Figure 2, elements Vinit and Vaint; see also Figure 6E, elements VL_int and VL_aint); an orthographic projection of at least portion of the data line onto the base substrate is located between orthographic projections of a first initialization signal connection line and a second initialization signal connection line that are adjacent onto the base substrate, the data line and the first initialization signal connection line are arranged in different layers(see paragraph 0211 – note that data lines DL may extend in direction DR2; see also Figure 6F – note that the data line and the first/second initialization lines are alternated); and/or, the data line and the second initialization signal connection line are arranged in different layers (see paragraph 0209 – note VL_int and VL_aint are on a different layer than data line DL [which is on layer SD2]).
Regarding claim 20, Kim discloses a display device (see Figure 1),
comprising the display substrate according to claim 1 (see rejection of claim 1 above).
Allowable Subject Matter
Claims 2-4, 7, 9-15, 17, 19, and 21-22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM R GIESY whose telephone number is (571)272-7555. The examiner can normally be reached Mon-Fri 8-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Patrick Edouard can be reached at 5712727603. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ADAM R. GIESY/Primary Examiner, Art Unit 2622
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