DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to Application 18/944,046 filed on 1/13/2025.
Claims 1-15 and 17-21 have been examined and are pending in this application. As per the Preliminary Amendment filed on 1/13/2025, claims 3-6, 8, 9, 12, 14, 15, 18-21 have been amended; claims 16 and 22-26 have been canceled. Claims 1-15 and 17-21 are pending in this application.
The examiner notes IDS(s) filed on 1/28/2025, 8/22/2025, 9/5/2025, 10/9/2025, 10/27/2025, 12/11/2025, 3/12/2026 and 7/16/2026 has been considered.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,562,920. Although the claims at issue are not identical, they are not patentably distinct from each other because:
Instant Application 18/994,046
U.S. Patent No. 12,562,920
Claim 1: A logic circuitry package comprising an interface to communicate with a controller, and a logic circuit comprising:
a memory arrangement storing a first digital signature, a second digital signature, and a third digital signature signed over the first digital signature and the second digital signature; wherein the logic circuit is configured to: receive at least one request from the controller; and transmit the first digital signature, the second digital signature, and the third digital signature to the controller in response to the at least one request.
Claim 1: A logic circuitry package comprising: an interface to communicate with a controller; and a logic circuit comprising a memory arrangement storing a first digital signature, a second digital signature, and a third digital signature signed over both the first digital signature and the second digital signature, wherein the third digital signature provides hierarchical authentication of both the first and second digital signatures, wherein successful verification of the third digital signature using a corresponding public key automatically authenticates both the first and second digital signatures through a single verification operation;
wherein the logic circuit is configured to: receive at least one request from the controller; and
transmit the first digital signature, the second digital signature, and the third digital signature to the controller in response to the at least one request to allow the controller to verify the authenticity of both the first and second digital signatures through verification of the third digital signature.
The examiner notes that the features emphasized above anticipate what is claimed in the limitations of Claim 1 of the Instant Application.
Therefore, the claims are rejected under nonstatutory double patenting.
Claim 9 and 17 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 and 10 of copending Application No. 18/994,047 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because:
Instant Application 18/994,046
Application No. 18/994,047
Claim 9: Logic circuitry comprising an interface to communicate with a host, and a logic circuit comprising: a memory arrangement storing part number signature metadata to facilitate verification of associated signed data, the part number signature metadata comprising: a schema identifier field storing a schema version number for the host to determine which schema to use; a key identifier field storing an identifier of a signing key for the host to use a correct key for the verification; a plurality of data block address fields, each data block address field of the plurality of data block address fields storing an address corresponding to a data block of a plurality of data blocks over which a part number signature is originally computed; and a plurality of data block length fields corresponding to the plurality of data blocks, each data block length field of the plurality of data block length fields storing data indicating a length of the corresponding data block, wherein the logic circuit is configured to :receive a read request from the host; and transmit the part number signature metadata to the host in response to the read request.
Claim 1: A logic circuitry package comprising an interface to communicate with a host, and a logic circuit comprising: a memory arrangement accessible by the logic circuit, the logic circuit being configured to cause digital signature metadata to be provided to the host to facilitate verification of associated signed data upon receiving a suitable request from the host, the digital signature metadata comprising: a schema identifier field feature to indicate a schema version number for the host to determine which schema to use; a key identifier field feature to indicate an identifier of a signing key for the host to use a correct key for the verification; a plurality of data block address fields, each data block address field of the plurality of data block address fields feature to indicate an address corresponding to a data block of a plurality of data blocks over which a digital signature is originally computed; and a plurality of data block length fields corresponding to the plurality of data blocks, each data block length field of the plurality of data block length fields feature to indicate data indicating a length of the corresponding data block, wherein the logic circuit is configured to: receive a read request from the host; and transmit the digital signature metadata to the host in response to the read request.
Claim 17: A method for provisioning a logic circuitry package comprising a memory arrangement, the method comprising: retrieving, via a processing system: a signing key identifier; and signing data comprising a device type identifier corresponding to the logic circuitry package and data to be stored in a plurality of data blocks of a general use memory portion of the memory arrangement of the logic circuitry package as specified by part number signature metadata; concatenating, via the processing system, the signing data; computing, via the processing system, a part number signature over the concatenated signing data using a signing private key corresponding to the signing key identifier; and writing the part number signature to the general use memory portion of the memory arrangement of the logic circuitry package.
Claim 10:A method for provisioning a logic circuitry package comprising a memory arrangement, the method comprising: retrieving, via a processing system: a signing key identifier; and signing data comprising: a device type identifier corresponding to the logic circuitry package; a logic circuit identifier for the logic circuitry package for a host to differentiate the logic circuitry package from other logic circuitry packages; a partition map to define partitions of a general use memory portion of the memory arrangement of the logic circuitry package; and data to be stored in a plurality of data blocks of the general use memory portion of the memory arrangement of the logic circuitry package as specified by digital signature metadata; concatenating, via the processing system, the signing data; computing, via the processing system, a digital signature over the concatenated signing data using a signing private key corresponding to the signing key identifier; and configuring the logic circuitry package to provide, via the processing system, the digital signature in response to a suitable host request from the general use memory portion of the memory arrangement of the logic circuitry package.
The examiner notes that the features emphasized above anticipate what is claimed in the limitations of Claim 9 and 17 of the Instant Application.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim 9 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1, and similar representative claim(s) 8 and 15, of copending Application No. 19/197,952 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because:
Instant Application 18/994,046
Application No. 19/197,952
Claim 9: Logic circuitry comprising an interface to communicate with a host, and a logic circuit comprising: a memory arrangement storing part number signature metadata to facilitate verification of associated signed data, the part number signature metadata comprising: a schema identifier field storing a schema version number for the host to determine which schema to use; a key identifier field storing an identifier of a signing key for the host to use a correct key for the verification; a plurality of data block address fields, each data block address field of the plurality of data block address fields storing an address corresponding to a data block of a plurality of data blocks over which a part number signature is originally computed; and a plurality of data block length fields corresponding to the plurality of data blocks, each data block length field of the plurality of data block length fields storing data indicating a length of the corresponding data block, wherein the logic circuit is configured to: receive a read request from the host; and transmit the part number signature metadata to the host in response to the read request.
Claim 1, and similar representative claim(s) 8 and 15: A logic circuitry package for a print cartridge comprising: an interface to communicate with a host print apparatus; a memory arrangement storing digital signature metadata to facilitate verification of associated signed data by the host print apparatus, the digital signature metadata comprising: a schema identifier field storing a schema version number for the host print apparatus to determine which schema to use; a key identifier field storing an identifier of a signing key for the host print apparatus to use for verification; a plurality of data block address fields, each storing an address corresponding to a data block of a plurality of data blocks over which a digital signature is originally computed, wherein the plurality of data blocks include print apparatus operational parameters; and a plurality of data block length fields corresponding to the plurality of data blocks, each storing data indicating a length of the corresponding data block; and a logic circuit configured to: receive a read request from the host print apparatus; and transmit the digital signature metadata to the host print apparatus in response to the read request to allow the host print apparatus to selectively access and verify individual data blocks of the plurality of data blocks without requiring verification of all data blocks.
The examiner notes that the features emphasized above anticipate what is claimed in the limitations of Claim 9 of the Instant Application.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim 17 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 23, of copending Application No. 18/994,042 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because:
Instant Application 18/994,046
Application No. 18/994,042
Claim 17: A method for provisioning a logic circuitry package comprising a memory arrangement, the method comprising: retrieving, via a processing system: a signing key identifier; and signing data comprising a device type identifier corresponding to the logic circuitry package and data to be stored in a plurality of data blocks of a general use memory portion of the memory arrangement of the logic circuitry package as specified by part number signature metadata; concatenating, via the processing system, the signing data; computing, via the processing system, a part number signature over the concatenated signing data using a signing private key corresponding to the signing key identifier; and writing the part number signature to the general use memory portion of the memory arrangement of the logic circuitry package.
Claim 23: A method for provisioning a logic circuitry package comprising a memory arrangement, the method comprising: receiving, by a logic circuit of the logic circuitry package, a command to generate a manufacturing digital signature; reading, by the logic circuit in response to the command, a signing key identifier and at least one indication of indicated data stored in a memory arrangement of the logic circuitry package; reading, by the logic circuit, a signing key corresponding to the signing key identifier; reading, by the logic circuit, the indicated data based on the at least one indication; computing, by the logic circuit, a manufacturing digital signature based on the indicated data using the signing key; and writing, by the logic circuit, the manufacturing digital signature to the memory arrangement.
The examiner notes that the features emphasized above anticipate what is claimed in the limitations of 17 of the Instant Application.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim 17 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 15, of copending Application No. 19/197,948 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because:
Instant Application 18/994,046
Application No. 19/197,948
Claim 17: A method for provisioning a logic circuitry package comprising a memory arrangement, the method comprising: retrieving, via a processing system: a signing key identifier; and signing data comprising a device type identifier corresponding to the logic circuitry package and data to be stored in a plurality of data blocks of a general use memory portion of the memory arrangement of the logic circuitry package as specified by part number signature metadata; concatenating, via the processing system, the signing data; computing, via the processing system, a part number signature over the concatenated signing data using a signing private key corresponding to the signing key identifier; and writing the part number signature to the general use memory portion of the memory arrangement of the logic circuitry package.
Claim 15: A method for provisioning a logic circuitry package, comprising: receiving a command to generate a manufacturing digital signature; reading a signing key identifier and at least one indication of indicated data stored in a memory arrangement, wherein the indicated data comprises multiple digital signatures arranged in a hierarchical structure a hierarchical signature structure including a part-specific digital signature signed over device-specific data and a part number digital signature signed over common manufacturing data, wherein the manufacturing digital signature is computed over both the part-specific digital signature and the part number digital signature; reading a signing key corresponding to the signing key identifier; reading the indicated data based on the at least one indication; computing a manufacturing digital signature based on the indicated data using the signing key; and writing the manufacturing digital signature to the memory arrangement.
The examiner notes that the features emphasized above anticipate what is claimed in the limitations of 17 of the Instant Application.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pollard et al. (US 2017/0330046 A1).
Regarding Claim 1;
Pollard discloses a logic circuitry package comprising an interface to communicate with a controller ([0023] and [0026] ]-[0028] - In an example, the imaging device is configured to extract a signature from the image. A processor is provided (locally and/or remote from the imaging device) to execute the program code 140 which compares the extracted signature to a reference signature and authenticates the extracted signature against the reference signature. In an example, the program code may operate according to any of a plurality of different authentication protocols. Example protocols include at least a hierarchical signatures protocol, a revisable selection of signatures protocol, a multiple agents protocol, and a multiple modalities protocol, each of which are described in more detail below) and a logic circuit comprising:
a memory arrangement storing a first digital signature, a second digital signature, and a third digital signature signed over the first digital signature and the second digital signature ([0013] - These signatures may be discrete areas of the image, or may include portions of multiple areas. For example, an image having areas A, B, C, and D (each covering a quarter of the area) may include signatures A, B, C, and D. But additional signatures may be E incorporating aspects of signature A, along with aspects of signature B, and so forth. Also multiple signatures can be extracted from the same physical area, using separate signature extraction techniques and [0026] - For purposes of illustration, the authentication server 122 may provide remote processing, such as but not limited to, executing the program code 140 to process and/or store reference signatures and processing an extracted signature for authentication (at least in part, as processing may also occur at the user device 112) and [0027] - At least one of the computing devices in the user domain 110 (e.g., user device 112) includes a capture device such as an electronic imaging device (e.g., a camera or low-cost microscope) capable of electronically receiving data for (or “capturing”) an image. Image processing program code 140 may also be provided in conjunction with the imaging device to process the captured image data and [0047] - According to an example hierarchical signatures protocol, digital signature authentication includes extracting and comparing a hierarchy of signatures. For example, a first order signature 410 in the hierarchy may be used for authentication. If the first order signature does not provide sufficient confidence in the authenticity, then a second order signature 420 is compared, and so forth. Any number of signatures may be provided according to the hierarchy and [0050]-[0051]);
wherein the logic circuit is configured to:
receive at least one request from the controller ([0023] and [0026]-[0028] and [0071] - Operation 620 includes receiving authentication instructions. Authentication instructions may be coordinates or other information for identifying a location of a signature within an image. In an example, the authentication instructions may be embedded in the image and are retrieved or extracted from the image, e.g., using an image processor.); and
transmit the first digital signature, the second digital signature, and the third digital signature to the controller in response to the at least one request ([0013] - These signatures may be discrete areas of the image, or may include portions of multiple areas. For example, an image having areas A, B, C, and D (each covering a quarter of the area) may include signatures A, B, C, and D. But additional signatures may be E incorporating aspects of signature A, along with aspects of signature B, and so forth. Also multiple signatures can be extracted from the same physical area, using separate signature extraction techniques and [0026] - For purposes of illustration, the authentication server 122 may provide remote processing, such as but not limited to, executing the program code 140 to process and/or store reference signatures and processing an extracted signature for authentication (at least in part, as processing may also occur at the user device 112) and [0027] - At least one of the computing devices in the user domain 110 (e.g., user device 112) includes a capture device such as an electronic imaging device (e.g., a camera or low-cost microscope) capable of electronically receiving data for (or “capturing”) an image. Image processing program code 140 may also be provided in conjunction with the imaging device to process the captured image data and [0028] - In an example, the imaging device is configured to extract a signature from the image. A processor is provided (locally and/or remote from the imaging device) to execute the program code 140 which compares the extracted signature to a reference signature and authenticates the extracted signature against the reference signature. In an example, the program code may operate according to any of a plurality of different authentication protocols. Example protocols include at least a hierarchical signatures protocol, a revisable selection of signatures protocol, a multiple agents protocol, and a multiple modalities protocol, each of which are described in more detail below and [0047] - According to an example hierarchical signatures protocol, digital signature authentication includes extracting and comparing a hierarchy of signatures. For example, a first order signature 410 in the hierarchy may be used for authentication. If the first order signature does not provide sufficient confidence in the authenticity, then a second order signature 420 is compared, and so forth. Any number of signatures may be provided according to the hierarchy and [0050]-[0051] and [0073] - As noted above, less secure signatures and/or signatures needing less processing power to authenticate may be stored on the device itself, and more secure signatures and/or signatures needing more processing power to authenticate may be stored, in a remote database (e.g., handled by a server with more security and/or computing power.).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pollard et al. (US 2017/0330046 A1) in view of Yu et al. (US 2022/0342344 A1).
Regarding Claim 2;
Pollard discloses the logic circuitry package of claim 1.
Pollard further discloses wherein the first digital signature is a... signature;, the second digital signature is a... signature; and the third digital is a... signature. ([0013] - These signatures may be discrete areas of the image, or may include portions of multiple areas. For example, an image having areas A, B, C, and D (each covering a quarter of the area) may include signatures A, B, C, and D. But additional signatures may be E incorporating aspects of signature A, along with aspects of signature B, and so forth. Also multiple signatures can be extracted from the same physical area, using separate signature extraction techniques and [0050]-[0051]).
Pollard fails to explicitly disclose ... is a perso..., ... is a part number..., and ...is a manufacturing....
However, in an analogous art, Yu teaches data that can be construed as ...is a perso... ([0077] - ... consumable serial number, ...consumable ID...), ... is a part number... ([0077] - consumable color characteristic information, consumable capacity information), and is a manufacturing ... ([0077] – authentication information may include.... consumable ID... consumable color characteristic information, consumable capacity information).
Therefore, it would have been obvious to one of ordinarily skill in the art before the effective filing date of the claimed invention to combine the teachings of Yu to the signatures of Pollard to include and further be signatures of ... is a perso..., ... is a part number..., and ...is a manufacturing....
One would have been motivated to combine the teachings of Yu to Pollard to do so as it provides / allows security and reliability of using such authentication... [with the] use of a consumable (Yu, [0005]).
Regarding Claim 3;
Pollard discloses the logic circuitry package of claim 1.
Pollard further discloses wherein the first digital signature is signed over data comprising at least one of: a ... identifier corresponding to the logic circuitry package; a logic circuit identifier for the controller to differentiate the logic circuitry package from other logic circuitry packages; a partition map to define partitions of a general use memory portion of the memory arrangement; and first digital signature specified data stored in the general use memory portion of the memory arrangement ([0028] - In an example, the imaging device is configured to extract a signature from the image. A processor is provided (locally and/or remote from the imaging device) to execute the program code 140 which compares the extracted signature to a reference signature and authenticates the extracted signature against the reference signature. In an example, the program code may operate according to any of a plurality of different authentication protocols. Example protocols include at least a hierarchical signatures protocol, a revisable selection of signatures protocol, a multiple agents protocol, and a multiple modalities protocol, each of which are described in more detail below) and [0078] - It is noted that in this example, the image may give rise to a plurality of signatures and the extracted signature may he selected from the plurality of signatures, as described above with reference to FIG. 3 and [0079] By way of illustration, operations may repeat according to multiple agents protocol, wherein different signatures authenticate different agents. For example, a hospital administrator may need an administrative (e.g., Level 1) signature authentication, and a doctor may need a medical (e.g., Level 2) signature authentication, thereby providing the respective users with the appropriate level of information about a patient).
Pollard fails to explicitly discloses wherein the first ... data comprising at least one of: a device type identifier corresponding to the logic circuitry package; a logic circuit identifier for the controller to differentiate the logic circuitry package from other logic circuitry packages; a partition map to define partitions of a general use memory portion of the memory arrangement; and first digital signature specified data stored in the general use memory portion of the memory arrangement.
However, in an analogous art, Yu teaches wherein the first ... data comprising at least one of: a device type identifier corresponding to the logic circuitry package, a logic circuit identifier for the controller to differentiate the logic circuitry package from other logic circuitry packages; a partition map to define partitions of a general use memory portion of the memory arrangement; and first digital signature specified data stored in the general use memory portion of the memory arrangement ([0077] - ...consumable ID)
Therefore, it would have been obvious to one of ordinarily skill in the art before the effective filing date of the claimed invention to combine the teachings of Yu to the signature/data of Pollard to include be signature/data of first ... data comprising at least one of: a device type identifier corresponding to the logic circuitry package, a logic circuit identifier for the controller to differentiate the logic circuitry package from other logic circuitry packages; a partition map to define partitions of a general use memory portion of the memory arrangement; and first digital signature specified data stored in the general use memory portion of the memory arrangement.
One would have been motivated to combine the teachings of Yu to Pollard to do so as it provides / allows security and reliability of using such authentication... [with the] use of a consumable (Yu, [0005]).
Regarding Claim 4;
Pollard discloses the logic circuitry package of claim 1.
Pollard further discloses wherein the second digital signature is signed over ... data... ([0028] - In an example, the imaging device is configured to extract a signature from the image. A processor is provided (locally and/or remote from the imaging device) to execute the program code 140 which compares the extracted signature to a reference signature and authenticates the extracted signature against the reference signature. In an example, the program code may operate according to any of a plurality of different authentication protocols. Example protocols include at least a hierarchical signatures protocol, a revisable selection of signatures protocol, a multiple agents protocol, and a multiple modalities protocol, each of which are described in more detail below) and [0078] - It is noted that in this example, the image may give rise to a plurality of signatures and the extracted signature may he selected from the plurality of signatures, as described above with reference to FIG. 3 and [0079] By way of illustration, operations may repeat according to multiple agents protocol, wherein different signatures authenticate different agents. For example, a hospital administrator may need an administrative (e.g., Level 1) signature authentication, and a doctor may need a medical (e.g., Level 2) signature authentication, thereby providing the respective users with the appropriate level of information about a patient).
Pollard fails to explicitly discloses ...common manufacturing data comprising at least one of: a color; a fill level; and a region.
However, in an analogous art, Yu further teaches ... common manufacturing data comprising at least one of: a color; a fill level; and a region ([0077] - consumable color characteristic information, consumable capacity information).
Therefore, it would have been obvious to one of ordinarily skill in the art before the effective filing date of the claimed invention to combine the teachings of Yu to the signature/data of Pollard to include be signature/data of ... common manufacturing data comprising at least one of: a color; a fill level; and a region.
One would have been motivated to combine the teachings of Yu to Pollard to do so as it provides / allows security and reliability of using such authentication... [with the] use of a consumable (Yu, [0005]).
Regarding Claim 5;
Pollard discloses the logic circuitry package of claim 1.
Pollard further discloses wherein the third digital signature is signed over ...data... ([0028] - In an example, the imaging device is configured to extract a signature from the image. A processor is provided (locally and/or remote from the imaging device) to execute the program code 140 which compares the extracted signature to a reference signature and authenticates the extracted signature against the reference signature. In an example, the program code may operate according to any of a plurality of different authentication protocols. Example protocols include at least a hierarchical signatures protocol, a revisable selection of signatures protocol, a multiple agents protocol, and a multiple modalities protocol, each of which are described in more detail below) and [0078] - It is noted that in this example, the image may give rise to a plurality of signatures and the extracted signature may he selected from the plurality of signatures, as described above with reference to FIG. 3 and [0079] By way of illustration, operations may repeat according to multiple agents protocol, wherein different signatures authenticate different agents. For example, a hospital administrator may need an administrative (e.g., Level 1) signature authentication, and a doctor may need a medical (e.g., Level 2) signature authentication, thereby providing the respective users with the appropriate level of information about a patient).
Pollard fails to explicitly discloses ...part-specific manufacturing data comprising at least one of: a date of manufacture; a time of manufacture; and a manufacturing line identifier.
However, in an analogous art, Yu further teaches ...part-specific manufacturing data comprising at least one of: a date of manufacture; a time of manufacture; and a manufacturing line identifier ([0077] – authentication information may include.... consumable serial number, consumable production date, consumable ID, consumable production batch number,... consumable color characteristic information, consumable capacity information).
Therefore, it would have been obvious to one of ordinarily skill in the art before the effective filing date of the claimed invention to combine the teachings of Yu to the signature/data of Pollard to include be signature/data of ...part-specific manufacturing data comprising at least one of: a date of manufacture; a time of manufacture; and a manufacturing line identifier
One would have been motivated to combine the teachings of Yu to Pollard to do so as it provides / allows security and reliability of using such authentication... [with the] use of a consumable (Yu, [0005]).
Claim(s) 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pollard et al. (US 2017/0330046 A1) in view of Sofia (US 2020/0233978 A1).
Regarding Claim 6;
Pollard discloses the logic circuitry package of claim 1.
Pollard fails to explicitly disclose wherein the memory arrangement stores first digital signature metadata to facilitate verification of the first digital signature and second digital signature metadata to facilitate verification of the second digital signature.
However, in an analogous art, Sofia teaches wherein the memory arrangement stores first digital signature metadata to facilitate verification of the first digital signature and second digital signature metadata to facilitate verification of the second digital signature ([0045] - At block 505, the processing system 110 can read the first digital signature 304A and the one or more additional digital signatures 304B from the metadata record 302. At block 510, the processing system 110 can perform a validation of the one or more data records 306 to confirm that the one or more data records 306 are unchanged based on at least one of the first digital signature 304A and the one or more additional digital signatures 304B)
Therefore, it would have been obvious to one of ordinarily skill in the art before the effective filing date of the claimed invention to combine the teachings of Sofia to the memory arrangement of Pollard to include wherein the memory arrangement stores first digital signature metadata to facilitate verification of the first digital signature and second digital signature metadata to facilitate verification of the second digital signature
One would have been motivated to combine the teachings of Sofia to Pollard to do so as it provides / allows tamper verification or other security uses can become “more” secure over (Sofia, [0002]).
Regarding Claim 7;
Pollard in view of Sofia discloses the logic circuitry package of claim 6.
Sofia further teaches wherein the first digital signature metadata and the second digital signature metadata are configured based on the same schema ([0032] - In an example, the operating system 122 may associate the tamper detection record 200 with a single event record, such as the event record 130a. For example, the header 210 may include a spatial reference of the event record 130a. The spatial reference may be a memory location of the event record 130a. Alternatively or in addition, the spatial reference may be a spatial relation between the tamper detection record 200 and the corresponding event record 130a. For example, the spatial relation can be a predetermined relation based on the memory locations of the records and [0038] - FIG. 3 depicts a block diagram 300 illustrating options for incorporating a second digital signature into a metadata record that includes a first digital signature. A metadata record 302 can include a first digital signature 304A associated with contents of one or more data records 306. For example, the metadata record 302 can be an instance of the tamper detection record 200 of FIG. 2 stored in the memory system 120 of FIG. 1...and [0045] - Validation can be performed using, for example, either or both of the first signature generator verifier 310A and the second signature generator verifier 310B. The first signature generator verifier 310A and the second signature generator verifier 310B can use public and private key pairs associated with the first digital signature 304A and the one or more additional digital signatures 304B and apply known validation algorithms respectively.) As construed using public and private key pairs associated with the first digital signature 304A and the one or more additional digital signature to validate represent being based on the same schema.
Similar rationale and motivation is noted for the combination of Sofia to Pollard in view of Sofia, as per claim 6, above.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pollard et al. (US 2017/0330046 A1) in view of Walmsley US (2009/0319802 A1).
Regarding Claim 8;
Pollard discloses the logic circuitry package of claim 1.
Pollard discloses wherein the first digital signature and the second digital signature are stored in a ... memory portion of the memory arrangement ..., and wherein the third digital signature is stored in [a] memory portion of the memory arrangement... ([0013] - These signatures may be discrete areas of the image, or may include portions of multiple areas. For example, an image having areas A, B, C, and D (each covering a quarter of the area) may include signatures A, B, C, and D. But additional signatures may be E incorporating aspects of signature A, along with aspects of signature B, and so forth. Also multiple signatures can be extracted from the same physical area, using separate signature extraction techniques and [0026] - For purposes of illustration, the authentication server 122 may provide remote processing, such as but not limited to, executing the program code 140 to process and/or store reference signatures and processing an extracted signature for authentication (at least in part, as processing may also occur at the user device 112) and [0027] - At least one of the computing devices in the user domain 110 (e.g., user device 112) includes a capture device such as an electronic imaging device (e.g., a camera or low-cost microscope) capable of electronically receiving data for (or “capturing”) an image. Image processing program code 140 may also be provided in conjunction with the imaging device to process the captured image data and [0047] - According to an example hierarchical signatures protocol, digital signature authentication includes extracting and comparing a hierarchy of signatures. For example, a first order signature 410 in the hierarchy may be used for authentication. If the first order signature does not provide sufficient confidence in the authenticity, then a second order signature 420 is compared, and so forth. Any number of signatures may be provided according to the hierarchy and [0050]-[0051]);
Pollard fails to explicitly ... stored in a general use memory portion of the memory arrangement configured for general purpose read/write access, and ...stored in an attribute memory portion of the memory arrangement not configured for general purpose read/write access.
However, in an analogous art, Walmsley teaches concepts of ... stored in a general use memory portion of the memory arrangement configured for general purpose read/write access, and ...stored in an attribute memory portion of the memory arrangement not configured for general purpose read/write access ([0222] - Access permission to all of the valid non-DRAM address space (for example the PEP blocks) is supervisor read/write access only (no supervisor execute access, and user mode has no access at all) with the exception that certain GPIO and Timer registers can also be accessed by user code. These registers will require bitwise access permissions. Each peripheral block will determine how the access is restricted. With respect to the DRAM and PEP subsystems of SoPEC, typically we would set user read/write/execute mode permissions to be 1/1/0 only in the region of memory that is used for OEM program data, 1/0/1 for regions of OEM program code, and 0/0/0 elsewhere (including the trap table). By contrast we would typically set supervisor mode read/write/execute permissions for this memory to be 1/1/0 (to avoid accidentally executing user code in supervisor mode)).
Therefore, it would have been obvious to one of ordinarily skill in the art before the effective filing date of the claimed invention to combine the teachings of Walmsley to the memory arrangement of Pollard to include ... stored in a general use memory portion of the memory arrangement configured for general purpose read/write access, and ...stored in an attribute memory portion of the memory arrangement not configured for general purpose read/write access.
One would have been motivated to combine the teachings of Walmsley to Pollard to do so as it provides / allows limiting access to regions of “memory” to avoid “memory” accidents (Walmsley, as gleaned, [0218] and [0222]).
Allowable Subject Matter
Claim(s) 9-15 and 17-21 would be allowable over the prior art of record, however, as allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with (i.e., Double Patenting Rejections). See 37 CFR 1.111(b) and MPEP § 707.07(a).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO-892 attached.
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/KARI L SCHMIDT/Primary Examiner, Art Unit 2439
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