DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment of claims 1 and 20 filed on January 28, 2026 has been entered and considered by examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4-7, 12-13 and 19-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yi et al (U.S. Patent Pub. No. 2020/0082758; already of record) in view of Dong et al (U.S. Patent Pub. No. 2022/0351666).
Regarding claim 1, Yi discloses a display panel (100), (fig. 1, [0050]), comprising:
a base substrate (101), comprising a display region (DA) and a first bezel region (NDA) located on a side (bottom side) of the display region, (fig. 1, [0052-0054]);
a plurality of sub-pixels (PXL) and a plurality of data lines (D11-D12p), located in the display region (DA), wherein the plurality of data lines are connected with the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels, (fig. 9, [0100, 0109 and 0113]); and
a multiplexing circuit (232) located in the first bezel region (NDA) and comprising a plurality of multiplexing units (232a(R), 232a(G) and 232a(B)); wherein at least one multiplexing unit (i.e. 232a(R)) of the plurality of multiplexing units comprises a plurality of multiplexing transistors (SW11(R) and SW12(R)), the at least one multiplexing unit (232a(R)) is electrically connected with a multiplexing data line (O11), a plurality of multiplexing control lines (CS1 and CS2), and a plurality of data lines (D11 and D14), and is configured to provide a data signal transmitted by the multiplexing data line (O11) to the plurality of data lines (D11 and D14) under control of the plurality of multiplexing control lines (CS1 and CS2), (fig. 16, [0160-0161]);
multiplexing transistors (SW11 and SW12) of the plurality of multiplexing units (232a(R), 232a(G) and 232a(B)) are arranged in a plurality of rows and columns, a row of multiplexing transistors (i.e. row of SW11(R) and SW12(R)) comprises a plurality of multiplexing transistors (SW11(R) and SW12(R)) arranged along a first direction (horizontal direction), (fig. 16, [0161]).
However, Yi does not mention the plurality of multiplexing transistors in the same column are completely aligned or partially misaligned in the second direction.
In a similar field of endeavor, Dong teaches
multiplexing transistors of the plurality of multiplexing units (multiplexing sub-circuits 311 and 312) are arranged in a plurality of rows and columns, a row of multiplexing transistors (row of transistors T21 and T22 of ) comprises a plurality of multiplexing transistors (T21 and T22) arranged along a first direction (horizontal direction), a column of multiplexing transistors comprises a plurality of multiplexing transistors (i.e. transistors T21 and T22) arranged along a second direction (vertical direction), and the plurality of multiplexing transistors in the same column (first column) are partially misaligned in the second direction (i.e. transistors T21 and T22 of the first column of pixels P11, P21, P31 and P41 are partially misaligned in the vertical direction), wherein the first direction (horizontal direction) intersects with the second direction (vertical direction), (fig. 5, [0065 and 0103-0107]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Yi, by specifically providing the multiplexing transistors are partially misaligned, as taught by Dong, for the purpose of reducing the number of channel for which data driving IC need to be used and reducing the cost of the display panel, [0080].
Regarding claim 2, Yi discloses wherein a column of multiplexing transistors (SW11) comprises a plurality of multiplexing transistors (SW11(R), SW11(G) and SW11(B)) connected with a same multiplexing control line (CS1), (fig. 16, [0161]).
Regarding claim 4, Yi discloses wherein the multiplexing transistors (SW11 and SW12) of the plurality of multiplexing units (232a(R), 232a(G) and 232a(B) are arranged in three rows, (fig. 16, [0161]).
Regarding claim 5, Yi discloses wherein the at least one multiplexing unit (232a(R)) comprises two multiplexing transistors (SW11(R) and SW12(R)), the two multiplexing transistors are electrically connected with different multiplexing control lines (CS1 and CS2) and electrically connected with a same multiplexing data line (O11); the two multiplexing transistors (SW11(R) and SW12(R)) of the at least one multiplexing unit (232a(R)) are arranged in a same row, (fig. 16, [0161]).
Regarding claim 6, Yi discloses wherein the plurality of multiplexing units (232a(R), 232a(G) and 232a(B)) comprise at least:
a plurality of first multiplexing units (232a(R)), a plurality of second multiplexing units (232a(G)), and a plurality of third multiplexing units (232a(B)); multiplexing transistors (SW11(R) and SW12(R)) of the plurality of first multiplexing units (232a(R)) are arranged in a first row, multiplexing transistors (SW11(G) and SW12(G)) of the plurality of second multiplexing units (232a(G)) are arranged in a second row, and multiplexing transistors (SW11(B) and SW12(B)) of the plurality of third multiplexing units (232a(B)) are arranged in a third row;
among a first multiplexing unit (232a(R)), a second multiplexing unit (232a(G)), and a third multiplexing unit (232a(B)), multiplexing transistors (SW11 and SW12) electrically connected with a same multiplexing control line (CS1 and CS2) are arranged in a same column, (fig. 16, [0161]).
Regarding claim 7, Yi discloses wherein the plurality of sub-pixels (PXL) comprise:
a first sub-pixel (R1 and R2) that emits light of a first color (red), a second sub-pixel (G1 and G1) that emits light of a second color (green), and a third sub-pixel (B1 and B2) that emits light of a third color (blue);
the first multiplexing unit (232a(R)) is configured to provide a data signal to a plurality of first sub-pixels (R1 and R2), the second multiplexing unit (232a(G)) is configured to provide a data signal to a plurality of second sub-pixels (G1 and G2), and the third multiplexing unit (232a(B)) is configured to provide a data signal to a plurality of third sub-pixels (B1 and B2), (fig. 16, [0161]).
Regarding claim 12, Dong discloses wherein the multiplexing transistors (T21-T24 and T11-T12) of the plurality of multiplexing units (311 and 312) are arranged in two rows (i.e. row of T21-T24 and row of T11-T12), (fig. 5, [0103 and 0106]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Yi, by specifically providing the multiplexing transistors, as taught by Dong, for the purpose of reducing the number of channel for which data driving IC need to be used and reducing the cost of the display panel, [0080].
Regarding claim 13, Dong discloses wherein the at least one multiplexing unit (312) comprises two multiplexing transistors (T11 and T12), the two multiplexing transistors are electrically connected with a first multiplexing control line (S1) and a second multiplexing control line (S2), respectively, and are electrically connected with a same multiplexing data line (I1); the two multiplexing transistors (T11 and T12) of the at least one multiplexing unit (312) are arranged in different rows and different columns, (fig. 5, [0103-0105]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Yi, by specifically providing the multiplexing transistors, as taught by Dong, for the purpose of reducing the number of channel for which data driving IC need to be used and reducing the cost of the display panel, [0080].
Regarding claim 19, Yi discloses a display apparatus (display device), comprising a display panel (100) according to claim 1, (fig. 1, [0050]).
Regarding claim 20, please refer to claim 1 for details.
Regarding claim 21, please refer to claim 2 for details.
Claim(s) 8-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yi in view of Dong and in view of Oh et al (U.S. Patent Pub. No. 2022/0068184; already of record).
Regarding claim 8, Yi discloses everything as specified above in claim 4. However, Yi in view of Dong does not mention the at least one multiplexing unit comprises three multiplexing transistors.
In a similar field of endeavor, Oh teaches wherein the at least one multiplexing unit (1:3 DEMUX) comprises three multiplexing transistors (i.e. three transistors), the three multiplexing transistors are electrically connected with different multiplexing control lines (i.e. control signals DEMUX1-DEMUX3) and electrically connected with a same multiplexing data line (CH1); the three multiplexing transistors of the at least one multiplexing unit are arranged in a same column (i.e. column of R1, G1 and B1), (fig. 12, [0140]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Yi in view of Dong, by specifically providing the three multiplexing transistors, as taught by Oh, for the purpose of outputting independent gamma compensation voltage for each color, [0007].
Regarding claim 9, Oh discloses wherein the plurality of sub-pixels comprise:
a first sub-pixel (R1) that emits light of a first color (red), a second sub-pixel (G1) that emits light of a second color (green), and a third sub-pixel (B1) that emits light of a third color (blue);
the three multiplexing transistors of the at least one multiplexing unit (three transistors of 1:3 DEMUX) are configured to provide data signals to the first sub-pixel (R1), the second sub-pixel (G1), and the third sub-pixel (B1), respectively, (fig. 12, [0139-0140]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Yi in view of Dong, by specifically providing the three multiplexing transistors, as taught by Oh, for the purpose of outputting independent gamma compensation voltage for each color, [0007].
Regarding claim 10, Oh discloses wherein the three multiplexing transistors of the at least one multiplexing unit (three transistors of 1:3 DEMUX) are a seventh multiplexing transistor (i.e. transistor connected to control signal DEMUX1), an eighth multiplexing transistor (i.e. transistor connected to control signal DEMUX2), and a ninth multiplexing transistor (i.e. transistor connected to control signal DEMUX3); the seventh multiplexing transistor, the eighth multiplexing transistor, and the ninth multiplexing transistor located in the same column (i.e. first column) are disposed and staggered in the second direction (i.e. staggered into three rows), (fig. 12, [0139-0140]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Yi in view of Dong, by specifically providing the three multiplexing transistors, as taught by Oh, for the purpose of outputting independent gamma compensation voltage for each color, [0007].
Regarding claim 11, Oh discloses wherein a plurality of seventh multiplexing transistors (i.e. transistors connected to control signal DEMUX1) are arranged in a first row, a plurality of eighth multiplexing transistors (i.e. transistors connected to control signal DEMUX2) are arranged in a second row, and a plurality of ninth multiplexing transistors (i.e. transistors connected to control signal DEMUX3) are arranged in a third row, and the first row, the second row, and the third row are sequentially disposed along a direction away from the display region (subpixels R1-B2), (fig. 12, [0139-0140]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Yi in view of Dong, by specifically providing the three multiplexing transistors, as taught by Oh, for the purpose of outputting independent gamma compensation voltage for each color, [0007].
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yi in view of Dong in view of Lu et al (U.S. Patent Pub. No. 2024/0381714; already of record) and in view of Ma (U.S. Patent Pub. No. 2024/0164159; already of record).
Regarding claim 16, Yi in view of Dong discloses everything as specified above in claim 1. However, Yi in view of Dong does not mention a first fanout region and a bending region.
In a similar field of endeavor, Lu teaches wherein the first bezel region (B1) comprises at least:
a first fanout region (B11 and B12) and a bending region (B13 and B14) disposed sequentially along a direction away from the display region (AA); the multiplexing circuit (311) is located in the first fanout region (B11 and B12); the first fanout region (B11 and B12) comprises a plurality of data leading-out lines (333) and a plurality of multiplexing data lines; the bending region (B13 and B14) at least comprises: a plurality of data bending connection lines (341), (figs. 1 and 5, [0089-0092, 0096 and 0114]);
the multiplexing circuit (311) is electrically connected with a plurality of data lines (D) of the display region (AA), and is electrically connected with the plurality of multiplexing data lines, and the plurality of multiplexing data lines are electrically connected with the plurality of data bending connection lines (341), (fig. 5, [0063, 0091-0092]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Yi in view of Dong, by specifically providing the fanout region and a bending region, as taught by Lu, for the purpose of improving the antistatic ability of the display substrate, [0144].
However, Yi in view of Dong and in view of Lu does not mention the multiplexing circuit is electrically connected with a plurality of data lines of the display region through the plurality of data leading-out lines.
In a similar field of endeavor, Ma teaches the multiplexing circuit (10) is electrically connected with a plurality of data lines (DO) of the display region (AA) through the plurality of data leading-out lines (L01), (fig. 1, [0047-0048]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Yi in view of Dong and in view of Lu, by specifically providing the multiplexing circuit is electrically connected with a plurality of data lines of the display region through the plurality of data leading-out lines, as taught by Ma, for the purpose of beneficial for realizing the narrow frame design of the product, [0041].
Allowable Subject Matter
Claims 14-15 and 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
In view of amendment, the reference of Dong has been added for new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Inquiries
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LONG D PHAM whose telephone number is (571)270-5573. The examiner can normally be reached Monday - Friday: 9am-5pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh D Nguyen can be reached at 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LONG D PHAM/ Primary Examiner, Art Unit 2623