DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to because figure 1 includes an error. Figure 1 shows “drive circuit” as being element 10 and element E1. However, element E1 is described as “light-emitting element” in the specification. Examiner suggests correcting figure 1 to include the “light-emitting element” in the box for element E1. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Pub. No. 2021/0407380 by Liu et al. (“Liu”).
As to claim 1, Liu discloses a pixel circuit (Liu, pixel driving circuit with a driving control sub-circuit 10 and a driving duration control sub-circuit 20, Figure 7), comprising:
a light-emitting element (Liu, element D, Figure 7), a drive circuit (Liu, driving transistor T1, Figure 7), a first control circuit (Liu, second driving sub-circuit 202, Figure 7), and a second control circuit (Liu, third control sub-circuit 204, Figure 7) and a third control circuit (Liu, second control sub-circuit 203, Figure 7); wherein
a control terminal of the drive circuit (Liu, driving transistor T1, Figure 7) is electrically connected to a first node (Liu, first node N1, Figure 7), a first terminal of the drive circuit is electrically connected to the light-emitting element (Liu, element D, Figure 7), which is used for driving the light-emitting element under the control of a potential at the first node, As shown in figure 7 of Liu, based on the signal at the first node N1, the driving transistor T1 activated and connects the top electrode to the bottom electrode of the transistor and connects to the element D through the seventh transistor T7.
the second control circuit (Liu, third control sub-circuit 204, Figure 7) is electrically connected to a first first refresh control terminal (Liu, control signal terminal CTR, Figure 7), the first node (Liu, first node N1, Figure 7) and a first terminal of the first control circuit respectively (Liu, second driving sub-circuit 202, Figure 7), which is used for controlling, under the control of a first first refresh control signal of the first first refresh control terminal, the first node to be or not to be conductively connected to the first terminal of the first control circuit; As shown in figure 7 of Liu, based on the control signal terminal CTR, the transistor T13 connects the first node N1 and the top electrode of the transistor T10.
the third control circuit (Liu, second control sub-circuit 203, Figure 7) is electrically connected to a second first refresh control terminal (Liu, enable signal terminal EM, Figure 7), the first terminal of the drive circuit (Liu, driving transistor T1, Figure 7) and a second terminal of the first control circuit respectively (Liu, second driving sub-circuit 202, Figure 7), which is used for controlling, under the control of a second first refresh control signal provided by the second first refresh control terminal, the first terminal of the drive circuit to be or not to be conductively connected to the second terminal of the first control circuit; As shown in figure 7 of Liu, based on the enable signal terminal EM, the transistor T12 connects to the transistor T10 and driving transistor T1 through various intervening components.
a control terminal of the first control circuit (Liu, second driving sub-circuit 202, Figure 7) is electrically connected to a second refresh control terminal (Liu, third node N3, Figure 7), the first control circuit is used for controlling, under the control of a second refresh control signal of the second refresh control terminal, the first terminal of the first control circuit to be or not to be conductively connected to the second terminal of the first control circuit. As shown in figure 7 of Liu, based on the voltage at the third node N3, the transistor activates to connect the top and bottom electrodes of transistor T10.
As to claim 2, Liu discloses the pixel circuit wherein the pixel circuit further comprises a first light-emitting control circuit (Liu, sixth transistor T6, Figure 7);
the first light-emitting control circuit is electrically connected to a first light-emitting control terminal (Liu, enable signal terminal EM, Figure 7), a power supply voltage terminal (Liu, first power supply voltage signal terminal VDD, Figure 7) and the second terminal of the drive circuit respectively (Liu, driving transistor T1, Figure 7), which is used for controlling, under the control of a first light-emitting control signal provided by the first light-emitting control terminal, the power supply voltage terminal to be or not to be conductively connected to the second terminal of the drive circuit. As shown in figure 7 of Liu, based on the EM signal, the transistor T6 connects the VDD to the top electrode of the driving transistor T1.
As to claim 3, Liu discloses the pixel circuit wherein the pixel circuit further comprises a data writing circuit (Liu, fourth transistor T4, Figure 7);
the data writing circuit is electrically connected to a writing control terminal (Liu, scan signal terminal S, Figure 7), a data line (Liu, data signal terminal Data, Figure 7) and the second terminal of the drive circuit respectively (Liu, driving transistor T1, Figure 7), which is used for writing, under the control of a writing control signal provided by the writing control terminal, a data voltage provided by the data line to the second terminal of the drive circuit. As shown in figure 7 of Liu, based on the scan signal terminal S, the transistor T4 connects the data signal terminal to the top electrode of the driving transistor T1.
As to claim 4, Liu discloses the pixel circuit wherein the pixel circuit further comprises an energy storage circuit (Liu, first capacitor C1, Figure 7) and a second light-emitting control circuit (Liu, seventh transistor T7, Figure 7);
the energy storage circuit (Liu, first capacitor C1, Figure 7) is electrically connected to the first node(Liu, first node N1, Figure 7), and is used for maintaining the potential of the first node;
the second light-emitting control circuit (Liu, seventh transistor T7, Figure 7)is electrically connected to a second light-emitting control terminal (Liu, enable signal terminal EM, Figure 7), the first terminal of the drive circuit (Liu, driving transistor T1, Figure 7) and a first electrode of the light-emitting element respectively (Liu, element D, Figure 7), which is used for controlling, under the control of a second light-emitting control signal provided by the second light-emitting control terminal, the first terminal of the drive circuit to be or not to be conductively connected to the first electrode of the light-emitting element; As shown in figure 7 of Liu, based on the enable signal terminal EM, the transistor T7 connects the bottom electrode of the driving transistor T1 and the element D.
a second electrode of the light-emitting element (Liu, element D, Figure 7) is electrically connected to a first voltage terminal (Liu, second power supply voltage signal terminal VSS, Figure 7).
As to claim 5, Liu discloses the pixel circuit wherein the pixel circuit further comprises a first reset circuit (Liu, eight transistor T8, Figure 7);
the first reset circuit is electrically connected to a first reset control terminal (Liu, first reset signal terminal RST1, Figure 7), a first initial voltage terminal (Liu, initial signal terminal Vint, Figure 7) and the first terminal of the drive circuit respectively (Liu, driving transistor T1, Figure 7), which is used for writing, under the control of a first reset control signal provided by the first reset control terminal, a first initial voltage provided by the first initial voltage terminal to the first terminal of the drive circuit. As shown in figure 7 of Liu, based on the first reset signal terminal RST1, the transistor T8 connects the initial signal terminal Vint to the driving transistor T1 through various intervening components.
As to claim 6, Liu discloses the pixel circuit wherein the pixel circuit further comprises a second reset circuit (Liu, ninth transistor T9, Figure 7);
the second reset circuit is electrically connected to a second reset control terminal (Liu, first reset signal terminal RST1, Figure 7), a second initial voltage terminal (Liu, initial signal terminal Vint, Figure 7) and the first electrode of the light-emitting element (Liu, element D, Figure 7) respectively, which is used for writing, under the control of a second reset control signal provided by the second reset control terminal, a second initial voltage provided by the second initial voltage terminal to the first electrode of the light-emitting element. As shown in figure 7 of Liu, based on the first reset signal terminal RST1, the transistor T9 connects the initial signal terminal Vint to the element D.
As to claim 7, Liu discloses the pixel circuit wherein the pixel circuit further comprises a third reset circuit (Liu, fourteenth transistor T14, Figure 7);
the second reset circuit (Liu, ninth transistor T9, Figure 7) is electrically connected to a third reset control terminal (Liu, second reset signal terminal RST2, Figure 7), a third initial voltage terminal (Liu, first voltage signal terminal V1, Figure 7) and the second terminal of the drive circuit respectively (Liu, driving transistor T1, Figure 7), which is used for writing, under the control of a third reset control signal provided by the third reset control terminal, a third initial voltage provided by the third initial voltage terminal to the second terminal of the drive circuit. As shown in figure 7 of Liu, based on the second reset signal terminal RST2, the transistor T14 connects the ninth transistor T9 and driving transistor T1 through various intervening components.
As to claim 8, Liu discloses the pixel circuit wherein the pixel circuit further comprises a third reset circuit (Liu, fourteenth transistor T14, Figure 7);
the third reset circuit (Liu, fourteenth transistor T14, Figure 7) is electrically connected to a third reset control terminal (Liu, second reset signal terminal RST2, Figure 7), a third initial voltage terminal (Liu, first voltage signal terminal V1, Figure 7) and the first terminal of the drive circuit (Liu, driving transistor T1, Figure 7) respectively, which is used for writing, under the control of a third reset control signal provided by the third reset control terminal, a third initial voltage provided by the third initial voltage terminal to the first terminal of the drive circuit. As shown in figure 7 of Liu, based on the second reset signal terminal RST2, the transistor T14 connects the first voltage signal terminal V1 and driving transistor T1 through various intervening components.
As to claim 9, Liu discloses the pixel circuit wherein the drive circuit comprises a drive transistor (Liu, transistor T1, Figure 7), the first control circuit comprises a first transistor (Liu, transistor T10, Figure 7), the second control circuit comprises a second transistor (Liu, transistor T13, Figure 7), and the third control circuit comprises a third transistor (Liu, transistor T12, Figure 7);
a gate of the drive transistor (Liu, gate of transistor T1, Figure 7) is electrically connected to the first node (Liu, first node N1, Figure 7), and a first electrode of the drive transistor (Liu, bottom electrode of transistor T1, Figure 7) is electrically connected to the light-emitting element (Liu, element D, Figure 7);
a gate of the second transistor (Liu, gate of transistor T13, Figure 7) is electrically connected to the first first refresh control terminal (Liu, control signal terminal CTR, Figure 7), a first electrode of the second transistor (Liu, right electrode of transistor T13, Figure 7) is electrically connected to the first node (Liu, first node N1, Figure 7), and a second electrode of the second transistor (Liu, left electrode of transistor T13, Figure 7) is electrically connected to a first electrode of the first transistor (Liu, top electrode of transistor T10, Figure 7);
a gate of the third transistor (Liu, gate of transistor T12, Figure 7) is electrically connected to the second first refresh control terminal (Liu, enable signal terminal EM, Figure 7), a first electrode of the third transistor (Liu, top electrode of transistor T12, Figure 7) is electrically connected to a second electrode of the first transistor (Liu, bottom electrode of transistor T10, Figure 7), and a second electrode of the third transistor (Liu, bottom electrode of transistor T12, Figure 7) is electrically connected to the first electrode of the drive transistor (Liu, bottom electrode of transistor T1, Figure 7); The bottom electrode of transistor T12 connected to the driving transistor T1 through various intervening components.
a gate of the first transistor (Liu, gate of transistor T10, Figure 7) is electrically connected to the second refresh control terminal (Liu, third node N3, Figure 7).
As to claim 10, Liu discloses the pixel circuit wherein the first transistor, the second transistor and the third transistor are oxide transistors. As shown in figure 7 of Liu, each of the transistor are MOSFETs, which are oxide transistors.
As to claim 11, Liu discloses the pixel circuit wherein the first light-emitting control circuit includes a fourth transistor (Liu, sixth transistor T6, Figure 7);
a gate of the fourth transistor (Liu, gate of sixth transistor T6, Figure 7) is electrically connected to the first light-emitting control terminal (Liu, enable signal terminal EM, Figure 7), a first electrode of the fourth transistor (Liu, top electrode of sixth transistor T6, Figure 7) is electrically connected to the power supply voltage terminal (Liu, first power supply voltage signal terminal VDD, Figure 7), and a second electrode of the fourth transistor (Liu, bottom electrode of transistor T6, Figure 7) is electrically connected to the second terminal of the drive circuit (Liu, top electrode of the driving transistor T1, Figure 7).
As to claim 12, Liu discloses the pixel circuit wherein the data writing circuit comprises a fifth transistor (Liu, fourth transistor T4, Figure 7);
a gate of the fifth transistor (Liu, gate of fourth transistor T4, Figure 7) is electrically connected to the writing control terminal (Liu, scan signal terminal S, Figure 7), a first electrode of the fifth transistor (Liu, right electrode of fourth transistor T4, Figure 7) is electrically connected to the data line (Liu, data signal terminal Data, Figure 7), and the second electrode of the fifth transistor (Liu, left electrode of fourth transistor T4, Figure 7) is electrically connected to the second terminal of the drive circuit (Liu, top electrode of the driving transistor T1, Figure 7).
As to claim 13, Liu discloses the pixel circuit wherein the second light-emitting control circuit comprises a sixth transistor (Liu, seventh transistor T7, Figure 7);
a gate of the sixth transistor (Liu, gate of seventh transistor T7, Figure 7) is electrically connected to the second light-emitting control terminal (Liu, enable signal terminal EM, Figure 7), a first electrode of the sixth transistor (Liu, top electrode of seventh transistor T7, Figure 7) is electrically connected to the first terminal of the drive circuit (Liu, bottom electrode of the driving transistor T1, Figure 7), and a second electrode of the sixth transistor (Liu, bottom electrode of seventh transistor T7, Figure 7) is electrically connected to the first electrode of the light-emitting element (Liu, element D, Figure 7).
As to claim 14, Liu discloses the pixel circuit wherein the first reset circuit comprises a seventh transistor (Liu, eight transistor T8, Figure 7);
a gate of the seventh transistor (Liu, gate of eight transistor T8, Figure 7) is electrically connected to the first reset control terminal (Liu, first reset signal terminal RST1, Figure 7), a first electrode of the seventh transistor (Liu, bottom electrode of eight transistor T8, Figure 7) is electrically connected to the first initial voltage terminal (Liu, initial signal terminal Vint, Figure 7), and a second electrode of the seventh transistor (Liu, top electrode of eight transistor T8, Figure 7) is electrically connected to the first terminal of the drive circuit (Liu, gate of driving transistor T1, Figure 7).
As to claim 15, Liu discloses the pixel circuit wherein the second reset circuit comprises an eighth transistor (Liu, ninth transistor T9, Figure 7);
a gate of the eighth transistor (Liu, gate of ninth transistor T9, Figure 7) is electrically connected to the second reset control terminal (Liu, first reset signal terminal RST1, Figure 7), the first electrode of the eighth transistor (Liu, left electrode of ninth transistor T9, Figure 7) is electrically connected to the second initial voltage terminal (Liu, initial signal terminal Vint, Figure 7), and the second electrode of the eighth transistor (Liu, right electrode of ninth transistor T9, Figure 7) is electrically connected to the first electrode of the light-emitting element (Liu, element D, Figure 7).
As to claim 16, Liu discloses the pixel circuit wherein the third reset circuit comprises a ninth transistor (Liu, fourteenth transistor T14, Figure 7);
a gate of the ninth transistor (Liu, gate of fourteenth transistor T14, Figure 7) is electrically connected to the third reset control terminal (Liu, second reset signal terminal RST2, Figure 7), a first electrode of the ninth transistor (Liu, top electrode of fourteenth transistor T14, Figure 7) is electrically connected to the third initial voltage terminal (Liu, first voltage signal terminal V1, Figure 7), and a second electrode of the ninth transistor (Liu, bottom electrode of fourteenth transistor T14, Figure 7) is electrically connected to the second terminal of the drive circuit (Liu, top electrode of the driving transistor T1, Figure 7). Bottom electrode of transistor T14 is connected to the driving transistor T1 through various intervening components.
As to claim 17, Liu discloses the pixel circuit wherein the third reset circuit comprises a ninth transistor (Liu, fourteenth transistor T14, Figure 7);
a gate of the ninth transistor (Liu, gate of fourteenth transistor T14, Figure 7) is electrically connected to the third reset control terminal (Liu, second reset signal terminal RST2, Figure 7), a first electrode of the ninth transistor (Liu, top electrode of of fourteenth transistor T14, Figure 7) is electrically connected to the third initial voltage terminal (Liu, first voltage signal terminal V1, Figure 7), and a second electrode of the ninth transistor (Liu, bottom electrode of fourteenth transistor T14, Figure 7) is electrically connected to the first terminal of the drive circuit (Liu, bottom electrode of the driving transistor T1, Figure 7). Bottom electrode of transistor T14 is connected to the driving transistor T1 through various intervening components.
As to claim 18, Liu discloses a driving method applied to the pixel circuit wherein the driving method comprises:
driving, by the drive circuit (Liu, driving transistor T1, Figure 7), under the control of the potential of the first node (Liu, first node N1, Figure 7), the light-emitting element (Liu, element D, Figure 7); As shown in figure 7 of Liu, based on the signal at the first node N1, the driving transistor T1 activated and connects the top electrode to the bottom electrode of the transistor and connects to the element D through the seventh transistor T7.
controlling, by the second control circuit (Liu, third control sub-circuit 204, Figure 7), under the control of the first first refresh control signal, the first node to be or not to be conductively connected to the first terminal of the first control circuit; As shown in figure 7 of Liu, based on the control signal terminal CTR, the transistor T13 connects the first node N1 and the top electrode of the transistor T10.
controlling, by the third control circuit (Liu, second control sub-circuit 203, Figure 7), under the control of the second first refresh control signal, the first terminal of the drive circuit to be or not to be conductively connected to the second terminal of the first control circuit; As shown in figure 7 of Liu, based on the enable signal terminal EM, the transistor T12 connects to the transistor T10 and driving transistor T1 through various intervening components.
controlling, by the first control circuit (Liu, second driving sub-circuit 202, Figure 7), under the control of the second refresh control signal, the first terminal of the first control circuit to be or not to be conductively connected to the second terminal of the first control circuit. As shown in figure 7 of Liu, based on the voltage at the third node N3, the transistor activates to connect the top and bottom electrodes of transistor T10.
As to claim 19, Liu discloses the driving method wherein the driving method comprises:
in row refresh frames, controlling, by the second control circuit, under the control of the first first refresh control signal, the first node to be conductively connected to the first terminal of the first control circuit; controlling, by the third control circuit, under the control of the second first refresh control signal, the first terminal of the drive circuit to be conductively connected to the second terminal of the first control circuit (Liu, Referring to FIGS. 5 and 13, or, referring to FIGS. 7 and 14, in the operating phase, the fourteenth transistor T14 is turned off, the tenth transistor T10 receives the third voltage signal whose voltage gradually changes, and changes from off to on, and the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 are turned on. The time duration during which the tenth transistor T10 changes from off to on is the luminous duration of the element to be driven D. Figure 14, ¶ [0232]);
in row maintaining frames, controlling, by the second control circuit, under the control of the first first refresh control signal, the first node not to be conductively connected to the first terminal of the first control circuit; controlling, by the third control circuit, under the control of the second first refresh control signal, the first terminal of the drive circuit not to be conductively connected to the second terminal of the first control circuit (Liu, In S2011, in each of the plurality of row scanning phases, the fourteenth transistor T14 is turned on in response to the second reset signal received from the second reset signal terminal RST2, so that the first voltage signal provided from the first voltage signal terminal V1 is written into the second node N2. Figure 14, ¶ [0229]);
in column refresh frames, controlling, by the second control circuit, under the control of the first first refresh control signal, the first node to be conductively connected to the first terminal of the first control circuit (Liu, After the reset phase is over, the driving transistor T1, the fourth transistor T4, and the fifth transistor T5 are turned on, the tenth transistor T10, the fourteenth transistor T14, the fifteenth transistor T15, and the sixteenth transistor T16 remain on, the sixth transistor T6, the seventh transistor T7, the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 remain off, and the eighth transistor T8 and the ninth transistor T9 are turned off. Figure 14, ¶ [0257]);
in column maintaining frames, controlling, by the second control circuit, under the control of the first first refresh control signal, the first node not to be conductively connected to the first terminal of the first control circuit (Liu, each row scanning phase further includes a reset stage. In the reset phase, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the fourteenth transistor T14, the fifteenth transistor T15, and the sixteenth transistor T16 are turned on, and the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 are turned off. Figure 14, ¶ [0257]).
As to claim 20, Liu discloses a display device comprising the pixel circuit according to claim 1 (Liu, pixel driving circuit and driving method thereof, and display panel, Abstract).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Pub. No. 2022/0157238 by Wang et al. teaches a pixel circuit and driving method with a similar pixel circuit (Figure 6) configuration as claimed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRENT D CASTIAUX whose telephone number is (571)272-5143. The examiner can normally be reached Mon-Fri 7:30 AM- 4:00 PM.
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/BRENT D CASTIAUX/Primary Examiner, Art Unit 2623
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