DETAILED ACTION
This action is responsive to the communication filed on 01/14/2026.
Claims 9 and 13-15 have been amended by preliminary amendment.
Claims 16-20 have been added by preliminary amendment.
No claims have been canceled.
Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2 and 8-16 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Farkas et al (EP 3491791 B1 herein after “Farkas”).
As per claim 1, and similarly claims 13 and 15, Farkas discloses a control method, comprising:
configuring and issuing a time gate control list (Farkas, para[0070-0071] the network controller comprises a transmission order information determining module and a transmission order information module, achieving a specific relative transmission order of the first and second packet flow packets using asynchronous, event-based packet gate switching control, see FIG. 2C: determine transmission order information; send transmission order information);
wherein the time gate control list comprises at least one deterministic queue and a plurality of time slices (Farkas, para[0051] time pattern (time points T00 to T99); and in each deterministic queue, a gate corresponding to a periodic time slice of the deterministic queue is open, gates corresponding to periodic time slices of other deterministic queues are closed, and a gate corresponding to a free time slice is open, with the periodic time slice of the deterministic queue being a time slice corresponding to a time when data packets of a deterministic service flow are periodically forwarded in the deterministic queue (Farkas, para[0051-0052] the time gate control list 35 defines, for each of the points in time of a a time pattern, the state of each packet gate of the egress port, i.e. whether the respective packet gate is open or closed; the mask may be a list comprising a binary value for each of the packet gates…the value “1” defines that a respective gate is to be switched in a synchronous manner…according the time-based control list 35), and the free time slice being a time slice other than the periodic time slice of each deterministic queue (Farkas, para[0052] the value “0” defines that a respective associated packet gate is to be switched in an asynchronous manner…in accordance with the asynchronous gate control vector…the mask defines which of the gate control vector 33 and the time-based gate control list 35 determines switching control for the packet gates 32 of egress port 30A).
As per claim 2, Farkas discloses the control method of claim 1, wherein configuring and issuing the time gate control list comprises: configuring a real-phase time gate control list, wherein, in each deterministic queue of the real-phase time gate control list, the gate corresponding to the periodic time slice of the deterministic queue is open, the gates corresponding to the periodic time slices of the other deterministic queues are closed, and the gate corresponding to the free time slice is blank; configuring a virtual-phase time gate control list, wherein, in each deterministic queue of the virtual-phase time gate control list, the gate corresponding to the free time slice is open; and determining the time gate control list according to the real-phase time gate control list and the virtual-phase time gate control list, and issuing the time gate control list (Farkus, para[0051-0054]).
As per claim 8, Farkas discloses the control method of claim 2, wherein determining the time gate control list according to the real-phase time gate control list and the virtual-phase time gate control list and issuing the time gate control list comprises: combining the real-phase time gate control list with the virtual-phase time gate control list according to one-to-one correspondence of time slices and deterministic queues, so as to obtain the time gate control list; and issuing the time gate control list (Farkas, para[0050]).
As per claim 9, Farkas disclose the control method of claim 2, wherein configuring and issuing the time gate control list further comprises: setting a flag bit for the free time slice (Farkas, para[0050-0053]).
As per claim 10, Farkas discloses the control method of claim 9, further comprising: counting data packets of a burst deterministic service flow or a jitter deterministic service flow according to monitoring information reported by a node device (Farkas, para[0064]).
As per claim 11, and similarly claims 14 and 16, Farkas discloses a communication method, comprising:
forwarding data packets of at least one deterministic data stream according to a time gate control list;
wherein, the time gate control list comprises at least one deterministic queue and a plurality of time slices (Farkas, para[0051] time pattern (time points T00 to T99); and in each deterministic queue, a gate corresponding to a periodic time slice of the deterministic queue is open, gates corresponding to periodic time slices of other deterministic queues are closed, and a gate corresponding to a free time slice is open, with the periodic time slice of the deterministic queue being a time slice corresponding to a time when data packets of a deterministic service flow are periodically forwarded in the deterministic queue (Farkas, para[0051-0052] the time gate control list 35 defines, for each of the points in time of a a time pattern, the state of each packet gate of the egress port, i.e. whether the respective packet gate is open or closed; the mask may be a list comprising a binary value for each of the packet gates…the value “1” defines that a respective gate is to be switched in a synchronous manner…according the time-based control list 35), and the free time slice being a time slice other than the periodic time slice of each deterministic queue (Farkas, para[0052] the value “0” defines that a respective associated packet gate is to be switched in an asynchronous manner…in accordance with the asynchronous gate control vector…the mask defines which of the gate control vector 33 and the time-based gate control list 35 determines switching control for the packet gates 32 of egress port 30A).
As per claim 12, Farkas discloses the communication method of claim 11, wherein forwarding the data packets of the at least one deterministic data stream according to the time gate control list comprises: monitoring, according to a flag bit, data packets of a deterministic service flow which are transmitted in the free time slice; and reporting monitoring information to a controller (Farkas, para[0064]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-7 and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Farkas and further in view of Chen et al (CN 111740924 A herein after “Chen”).
As per claim 3, Farkas does not disclose, however, Chen discloses the control method of claim 2, wherein configuring the real-phase time gate control list comprises: calculating a path of a target deterministic service flow; calculating a time gate for a node device on the path to forward data packets of the target deterministic service flow; and configuring the real-phase time gate control list according to the time gate (Chen, para[0016]).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to incorporate Chen’s teaching of configuring the real-phase gate control list according to the time gate into Farkas teaching of configuring a real-phase time gate control list because one of the ordinary skill in the art would have been motivated to perform communication transmission scheduling without affecting deterministic real-time transmission.
As per claim 4, Farkas does not disclose, however, Chen discloses the control method of claim 3, wherein configuring the real-phase time gate control list according to the time gate comprises: in a deterministic queue corresponding to the target deterministic service flow, setting a gate of a time slice corresponding to the time gate to be open; and in other deterministic queues, setting gates of the time slice corresponding to the time gate to be closed (Chen, para[0030-0032]).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to incorporate Chen’s teaching of configuring the real-phase gate control list according to the time gate into Farkas teaching of configuring a real-phase time gate control list because one of the ordinary skill in the art would have been motivated to perform communication transmission scheduling without affecting deterministic real-time transmission.
As per claim 5, Farkas discloses the control method of claim 3, wherein configuring the virtual-phase time gate control list comprises: configuring the virtual-phase time gate control list according to the time gate (Farkas, para[0053]).
As per claim 6, Farkas discloses the control method of claim 5, wherein configuring the virtual-phase time gate control list according to the time gate comprises: determining the free time slice according to the time gate; and setting the gate of the free time slice to be open (Farkas, para[0060]).
As per claim 7, Farkas discloses the control method of claim 5, wherein configuring the virtual-phase time gate control list according to the time gate comprises: removing a gate of a time slice corresponding to the time gate from the virtual-phase time gate control list (Farkas, para[0060]).
As per claim 17, Farkas discloses the control method of claim 3, wherein configuring and issuing the time gate control list further comprises: setting a flag bit for the free time slice (Farkas, para[0050-0053]).
As per claim 18, Farkas discloses the control method of claim 4, wherein configuring and issuing the time gate control list further comprises: setting a flag bit for the free time slice (Farkas, para[0050-0053]).
As per claim 19, Farkas discloses the control method of claim 5, wherein configuring and issuing the time gate control list further comprises: setting a flag bit for the free time slice (Farkas, para[0050-0053]).
As per claim 20, Farkas discloses the control method of claim 6, wherein configuring and issuing the time gate control list further comprises: setting a flag bit for the free time slice (Farkas, para[0050-0053]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. See form 892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Natisha Cox whose telephone number is (571)270-7167. The examiner can normally be reached on Monday to Friday, 10:00 am - 6:00pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Umar Cheema can be reached on (571)270-3037. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8000.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pairdirect.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NATISHA D COX/Primary Examiner, Art Unit 2458
Prosecution Insights