DETAILED ACTION
Status of the Application
1. Applicant’s Preliminary Amendment to the Claims filed January 14, 2025 is received and entered.
2. Claims 5, 8, 15, 21, 23, 25, and 30 are amended. Claims 6 – 7, 9, 16, 22, 24, and 26 – 29 are cancelled. Claims 1 – 5, 8, 10 – 15, 17 – 21, 23, 25, and 30 are pending and are under examination in this action.
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Requirement for Necessary Information
4. The Examiner has become aware of documents that may be material to patentability but have not been included in any IDS submissions even though the Applicant has been aware of these references for a substantial amount of time.
37 CFR 1.56(a) requires that “[e]ach individual associated with the filing and prosecution of a patent application has a duty of candor and good faith in dealing with the Office, which includes a duty to disclose to the Office all information known to that individual to be material to patentability”.
Specifically, Applicant has failed to disclose any prior art cited in co-pending application: 18/686,657. Each of the references cited in these co-pending applications may be material to the patentability of this application for prior art purposes and thus constitute necessary information that must be submitted to the Office.
5. Required Information: 37 CFR 1.105(a)(1)(viii) – In light of the above findings by the Examiner, Applicant is required to submit a list of every reference of which they are aware that may be material to the patentability of the claimed invention, as defined by 37 CFR 1.56(b). This requirement is being made in view of 37 CFR 1.56 and 1.105 in order to ensure that the most relevant prior art is fully considered.
Failure to provide a detailed list of all information that may be material to patentability of the claimed invention as defined by 37 CFR 1.56(b) will be considered non-responsive.
Accordingly, each piece of information referred to above is necessary material that is required to be submitted in order to properly proceed with the examination of this Application.
Double Patenting
6. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
7. Claims 1 – 5, 8, 25, and 30 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 – 12 of U.S. Patent No. 12,592,199.
For Example:
Claim 1 (App. 18/994,140)
Claim 1 (Patent 12,592,199)
1. A driving circuit, comprising a first switching circuit and a scanning signal generation circuit, (lines 1 – 2)
1. A driving circuit, comprising a first switching circuit and a scanning signal generation circuit; (lines 1 – 2)
wherein the first switching circuit is electrically coupled to a first gating control line, a data output end of a source driver and the scanning signal generation circuit, and configured to control to write a data signal provided by the data output end into the scanning signal generation circuit under the control of a first gating control signal provided by the first gating control line; and (lines 3 – 7)
wherein the first switching circuit is electrically connected to a first gating control line, at least two data output terminals of a source driver and the scanning signal generation circuit, and is configured to write a data signal provided by the at least two data output terminals into the scanning signal generation circuit under the control of a first gating control signal provided by the first gating control line; (lines 3 – 10)
the scanning signal generation circuit is configured to generate a scanning signal in accordance with the data signal, and output the scanning signal through a scanning signal output end. (lines 8 – 10)
the scanning signal generation circuit is configured to generate a scanning signal according to the data signal, and output the scanning signal through the scanning signal output terminal; (lines 11 – 14)
Claim 1 of the present application is broader than claim 1 of Patent No. 12,592,199 and is therefore clearly anticipated by claim 1 of Patent No. 12,592,199.
Claim Objections
8. Claims 25 and 30 are objected to under 37 CFR 1.75(c) as being in improper form. Specifically, claim 25 depends from both claims 1 and 10. As set forth in MPEP § 608.01(n)(I)(B)(1), a multiple dependent claim is improper when it “does not refer back in the alternative only”. Additionally, claim 30 depends from claim 25 and is therefore a multiple dependent claim by referring back to claims 1 and 10 simultaneously.
Accordingly, claims 25 and 30 are not being examined on the merits.
Claim Rejections - 35 USC § 112(b)
9. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
10. Claims 8 and 23 are rejected under 35 U.S.C. 112(b) being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Regarding claims 8 and 23, these claims are directed to both an apparatus and method steps of using the apparatus and are therefore indefinite. See IPXL Holdings v. Amazon.com, Inc., 430 F.2d 1377, 1384, 77 USPQ2d 1140, 1145 (Fed. Cir. 2005). See also, Ex parte Lyell, 17 USPQ2d 1548 (Bd. Pat. App. & Inter. 1990).
Claim 8 is directed to both an apparatus and a method by simultaneously including method recitations while depending from the apparatus claim 1.
Claim 23 is directed to both an apparatus and a method by simultaneously including method recitations while depending from the apparatus claim 10.
A recitation claiming both an apparatus and a method simultaneously is indefinite.
Claim Rejections - 35 USC § 101
11. 35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
12. Claims 8 and 23 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter.
Regarding claims 8 and 23, these claims are rejected under 35 USC 101 as being directed to neither a "process" nor a "machine," but rather embracing / overlapping two different statutory classes for at least the reasons stated above with regard to the rejection of this claim under 35 USC 112. See Ex parte Lyell, 17 USPQ2d 1548, 1551 (Bd. Pat. App. & Inter. 1990).
Claim Rejections - 35 USC § 102
13. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
14. Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bai et al. (U.S. Pub. 2021/0134225).
Regarding claim 1, Bai teaches: a driving circuit, comprising a first switching circuit and a scanning signal generation circuit (FIGS. 2, 4; paragraph [0040]; pixel driving sub-circuits 101 [driving circuit] each include a pixel driving sub-circuit 1_1 [first switching circuit] and a pixel driving sub-circuit 2_1 [scanning signal generation circuit]),
wherein the first switching circuit is electrically coupled to a first gating control line, a data output end of a source driver and the scanning signal generation circuit (FIGS. 2, 4; paragraphs [0040]; pixel driving sub-circuit 1_1 [first switching circuit] is electrically coupled to gate line Gate_1 [first gating control line], data line Data_1a [data output end of a source driver], and pixel driving sub-circuit 2_1 [scanning signal generation circuit]), and configured to control to write a data signal provided by the data output end into the scanning signal generation circuit under the control of a first gating control signal provided by the first gating control line (FIGS. 4, 6; paragraph [0052], [0053]; pixel driving sub-circuit 1_1 [first switching circuit] and pixel driving sub-circuit 2_1 [scanning signal generation circuit] both include transistors M3 connected to a common line A. Transistors M3 are under control of gate line Gate_1 and write data signals to common line A. Accordingly, a data signal from data line Data_1a is written into pixel driving sub-circuit 2_1 [scanning signal generation circuit] via common line A); and
the scanning signal generation circuit is configured to generate a scanning signal in accordance with the data signal, and output the scanning signal through a scanning signal output end (FIGS. 4, 6; paragraphs [0052], [0053]; pixel driving sub-circuit 2_1 [scanning signal generation circuit] generates an output to OLED. This output is interpreted as a “scanning signal” that is generated in accordance with the data signal from data line Data_1a which, as set forth above, is input to M3 of pixel driving sub-circuit 2_1 [scanning signal generation circuit] through common line A).
15. Claims 10 – 11 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ji et al. (U.S. Pub. 2022/0189417).
Regarding claim 10, Ji teaches: a pixel circuit, comprising a light-emitting element, a light-emission driving circuit and a control circuit (FIG. 2; paragraph [0041]; pixel P [pixel circuit] includes OLED [light-emitting element], driving transistor DRT [light emission driving circuit], and a “control circuit” including switching transistor SWT and sensing transistor SENT),
wherein the light-emission driving circuit is electrically coupled to a first node (FIG. 2; driving transistor DRT [light emission driving circuit] is electrically coupled to a “first node” that electrically connects data line DL and switching transistor SWT) and a first electrode of the light-emitting element (FIG. 2; driving transistor DRT [light emission driving circuit] is electrically connected to an upper [first] electrode of OLED [light-emitting element]) and configured to generate a driving current for driving the light-emitting element under the control of a potential at the first node (FIG. 2; paragraphs [0042], [0043]; driving transistor DRT [light emission driving circuit] generates a driving current for driving the OLED [light-emitting element] based on a potential at the “first node” which is used to turn on the driving transistor DRT [light emission driving circuit]), and a second electrode of the light-emitting element is electrically coupled to a third voltage end (FIG. 2; a lower [second] electrode of OLED [light-emitting element] is electrically coupled to EVSS); and
the control circuit is electrically coupled to a first gate line, a scanning line, the first node and the first electrode of the light-emitting element (FIG. 2; paragraphs [0045], [0049]; the “control circuit” set forth above is electrically coupled to first gate line GL1, signal line SENSE [scanning line], the “first node” set forth above, and the upper [first] electrode of OLED [light-emitting element]), and configured to control the first node to be electrically coupled to, or electrically decoupled from, the first electrode of the light-emitting element under the control of a first gate driving signal provided by the first gate line and a scanning signal provided by the scanning line (FIG. 2; as illustrated, the “first node” is either coupled to or decoupled from the upper [first] electrode of OLED [light-emitting element] based on the gate driving signal provided by first gate line GL1 to switching transistor SWT. The connections, and signals applied thereto, of the upper [first] electrode of OLED [light-emitting element] are also under control of the scanning signal provided by signal line SENSE [scanning line]).
Regarding claim 11, Ji teaches: wherein the control circuit comprises a first control circuit and a second control circuit (FIG. 2; switching transistor SWT [first control circuit] and sensing transistor SENT [second control circuit]), a first end of the light-emission driving circuit is electrically coupled to a second node (FIG. 2; a first [upper] end of driving transistor DRT [light emission driving circuit] is electrically coupled to “second node” N3), and a second end of the light-emission driving circuit is electrically coupled to a third node and the first electrode of the light-emitting element (FIG. 2; a second [lower] end of driving transistor DRT [light emission driving circuit] is electrically coupled to a “third node” that electrically connects sensing line SL and sensing transistor SENT. The second [lower] end of driving transistor DRT [light emission driving circuit] is also electrically coupled to the upper [first] electrode of OLED [light-emitting element]);
the first control circuit is electrically coupled to the first gate line, the first node and an intermediate node (FIG. 2; switching transistor SWT [first control circuit] is electrically coupled to first gate line GL1, the “first node”, and “intermediate node” N2), and configured to control the first node to be electrically coupled to, or electrically decoupled from, the intermediate node under the control of the first gate driving signal provided by the first gate line (FIG. 2; as illustrated, the “intermediate node” is either coupled to or decoupled from the “first node” based on the gate driving signal provided by first gate line GL1 to switching transistor SWT [first control circuit]); and
the second control circuit is electrically coupled to the scanning line, the intermediate node and the third node (FIG. 2; sensing transistor SENT [second control circuit] is electrically coupled to signal line SENSE [scanning line], “intermediate node” N2, and the “third node”), and configured to control the intermediate node to be electrically coupled to, or electrically decoupled from, the third node under the control of the scanning signal provided by the scanning line (FIG. 2; as illustrated, the “intermediate node” is either coupled to or decoupled from the “third node” based on the signal provided by signal line SENSE to sensing transistor SENSE [second control circuit]).
Regarding claim 17, Ji teaches: wherein the first control circuit comprises a first control transistor (FIG. 2; as set forth above, the “first control circuit” includes switching transistor SWT [first control transistor]), and the second control circuit comprises a second control transistor (FIG. 2; as set forth above, the “second control circuit” includes sensing transistor SENT [second control transistor]);
a gate electrode of the first control transistor is electrically coupled to the first gate line, a first electrode of the first control transistor is electrically coupled to the first node, and a second electrode of the first control transistor is electrically coupled to the intermediate node (FIG. 2; switching transistor SWT [first control transistor] includes a gate electrode electrically coupled to first gate line GL1, a first electrode electrically coupled to the “first node”, and a second electrode electrically coupled to the “intermediate node” N2); and
a gate electrode of the second control transistor is electrically coupled to the scanning line, a first electrode of the second control transistor is electrically coupled to the intermediate node, and a second electrode of the second control transistor is electrically coupled to the third node (FIG. 2; sensing transistor SENT [second control transistor] includes a gate electrode electrically coupled to signal line SENSE [scanning line], a first electrode electrically coupled to the “intermediate node” N2, and a second electrode electrically coupled to the “third node”).
Allowable Subject Matter
16. Claims 12 – 15 and 18 – 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN A LUBIT whose telephone number is (571)270-3389. The examiner can normally be reached M - F, ~6am - 3pm.
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/RYAN A LUBIT/Primary Examiner, Art Unit 2626
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