DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Email Communication
Applicant is encouraged to authorize the Examiner to communicate with applicant via email by filing form PTO/SB/439 either via USPS, Central Fax, or EFS-Web. See MPEP 502.01, 502.03, 502.05.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6-7, 9-14, & 16-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by CN117334480A hereafter referred to as Duan.
In regards to claim 1, Duan discloses
A capacitive device, comprising:
a substrate (7 – fig. 1; [n0031]) having a first side and a second side opposite to each other in a thickness direction thereof;
a capacitor comprising a first polar plate (6 – fig. 1; [n0031]), a dielectric layer (5 – fig. 1; [n0031]), and a second polar plate (1 – fig. 1; [n0031]) stacked on the second side; and
a first electrode layer (8 – fig. 1; [n0031]) provided on the first side and electrically connected to the first polar plate, and the first electrode layer being configured to solder-connect to an external circuit ([n0033]).
In regards to claim 2, Duan discloses
The capacitive device according to claim 1, further comprising a conductive post penetrating tie substrate in a thickness direction of the substrate, wherein one end of the conductive post is electrically connected to the first electrode layer, and the other end of the conductive post is electrically connected to the first polar plate (2 – fig. 1; [n0031] & [n0033]).
In regards to claim 31, Duan discloses
The capacitive device according to claim 2, wherein the capacitive device comprises a plurality of the conductive posts, and the plurality of the conductive posts are arranged at intervals (fig. 1).
In regards to claim 4, Duan discloses
The capacitive device according to claim 3, wherein the conductive posts are provided adjacent to an edge of the substrate (fig. 1).
In regards to claim 6, Duan discloses
The capacitive device according to claim 3, wherein the plurality of conductive posts are arranged in a planar array (fig. 1 – at least 9 by 1 array shown).
In regards to claim 7, Duan discloses
The capacitive device according to claim 2, wherein a support post is provided inside the conductive post, and one end of the support post facing the first polar plate supports the first polar plate; alternatively, the conductive posts are solid columnar structures made of a conductive material ([n0033]).
In regards to claim 9, Duan discloses
The capacitive device according to claim 1, wherein the second polar plate is further away from the substrate than the first polar plate (fig. 1).
In regards to claim 10, Duan discloses
The capacitive device according to claim 9, wherein the capacitive device further comprises a second electrode layer (3 – fig. 1; [n0031]) and an insulation layer (4 – fig. 1; [n0031] & [n0042])); the second electrode layer is located on a side of the second polar plate away from the substrate; the insulation layer is located between the second electrode layer and the second polar plate; the second electrode layer is electrically connected to the second polar plate (fig. 1); the second electrode layer is configured to solder-connect to an external circuit (fig. 1; [n0044] – the second electrode is capable of being soldered).
In regards to claim 11, Duan discloses
The capacitive device according to claim 10, wherein the insulation layer is provided with a second via (2 – fig. 1; [n0031]), and the second electrode layer is electrically connected to the second polar plate through the second via (fig. 1).
In regards to claim 12, Duan discloses
The capacitive device according to claim 10, wherein an edge of the insulation layer extends toward the substrate and covers an edge of the first polar plate, the dielectric layer, and the second polar plate (fig. 1; wherein left and right edges have insulation layer formed thereon (i.e. edges are covered).
In regards to claim 13, Duan discloses
The capacitive device according to claim 12, wherein the insulation layer comprises an organic material (n0042]).
In regards to claim 14, Duan discloses
The capacitive device according to claim 9, wherein the second polar plate is configured to solder-connect to an external circuit (fig. 1; [n0044] – the second electrode is capable of being soldered to an external circuit).
In regards to claim 16, Duan discloses
The capacitive device according to claim 1, wherein a front projection of the first polar plate and/or the second polar plate on the substrate is a polygon, a circle, an ellipse, or an irregular shape (fig. 1 – the plates will have a shape and thus read on said limitation).
In regards to claim 17, Duan discloses
A capacitive device, comprising:
a substrate (7 – fig. 1; [n0031]) having a first side and a second side opposite to each other in a thickness direction thereof;
a capacitor comprising a first polar plate (6 – fig. 1; [n0031]), a dielectric layer (5 – fig. 1; [n0031]), and a second polar plate (1 – fig. 1; [n0031]) stacked on the second side; and
a first electrode layer (8 – fig. 1; [n0031]) provided on the first side and electrically connected to the first polar plate, and the side of the first electrode layer away from the substrate being provided with an anti-oxidation layer made of a conductive material ([n0020] & [n0028]) .
In regards to claim 18, Duan discloses
An electronic apparatus, comprising the capacitive device according to claim 1 ([n0033]).
Claim(s) 1-4, 6-7, 9-12, 14, 16, 18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Devoe et al. (US 7,035,080).
In regards to claim 1, Devoe ‘080 discloses
A capacitive device, comprising:
a substrate (lower ceramic layer between 72 & 76 – fig. 1; C4:L9-30) having a first side and a second side opposite to each other in a thickness direction thereof;
a capacitor comprising a first polar plate (72 – fig. 1; C4:L9-30), a dielectric layer (ceramic layer between 72 & 70 – fig. 1; C4:L9-30), and a second polar plate (70 – fig. 1; C4:L9-30) stacked on the second side; and
a first electrode layer (76 – fig. 1; C4:L9-30) provided on the first side and electrically connected to the first polar plate, and the first electrode layer being configured to solder-connect to an external circuit (fig. 1; C1:L61 to C2:L14 & C4:L45-48 of US 6,753,218 which is incorporated by reference).
In regards to claim 2, Devoe ‘080 discloses
The capacitive device according to claim 1, further comprising a conductive post (82 – fig. 1; C4:L9-30) penetrating tie substrate in a thickness direction of the substrate, wherein one end of the conductive post is electrically connected to the first electrode layer, and the other end of the conductive post is electrically connected to the first polar plate (fig. 1; C4:L9-30).
In regards to claim 3, Devoe ‘080 discloses
The capacitive device according to claim 2, wherein the capacitive device comprises a plurality of the conductive posts, and the plurality of the conductive posts are arranged at intervals (fig. 1 & fig. 6-7 of US 6,753,218).
In regards to claim 4, Devoe ‘080 discloses
The capacitive device according to claim 3, wherein the conductive posts are provided adjacent to an edge of the substrate (fig. 1 & fig. 6-7 of US 6,753,218).
In regards to claim 6, Devoe ‘080 discloses
The capacitive device according to claim 3, wherein the plurality of conductive posts are arranged in a planar array (fig. 1 & fig. 6-7 of US 6,753,218).
In regards to claim 7, Devoe ‘080 discloses
The capacitive device according to claim 2, wherein a support post is provided inside the conductive post, and one end of the support post facing the first polar plate supports the first polar plate; alternatively, the conductive posts are solid columnar structures made of a conductive material (C4:L9-30).
In regards to claim 9, Devoe ‘080 discloses
The capacitive device according to claim 1, wherein the second polar plate is further away from the substrate than the first polar plate (fig. 1)
In regards to claim 10, Devoe ‘080 discloses
The capacitive device according to claim 9, wherein the capacitive device further comprises a second electrode layer (74 – fig. 1; C4:L9-30) and an insulation layer (ceramic layer between 74 & 70 – fig. 1; C4:L9-30); the second electrode layer is located on a side of the second polar plate away from the substrate; the insulation layer is located between the second electrode layer and the second polar plate; the second electrode layer is electrically connected to the second polar plate (fig. 1; C4:L9-30); the second electrode layer is configured to solder-connect to an external circuit (fig. 1; C1:L61 to C2:L14 & C4:L45-48 of US 6,753,218).
In regards to claim 11, Devoe ‘080 discloses
The capacitive device according to claim 10, wherein the insulation layer is provided with a second via (80 – fig. 1; C4:L9-30), and the second electrode layer is electrically connected to the second polar plate through the second via (fig. 1).
In regards to claim 12, Devoe ‘080 discloses
The capacitive device according to claim 10, wherein an edge of the insulation layer extends toward the substrate and covers an edge of the first polar plate, the dielectric layer, and the second polar plate (fig. 1; C4:L9-30).
In regards to claim 14, Devoe ‘080 discloses
The capacitive device according to claim 9, wherein the second polar plate is configured to solder-connect to an external circuit fig. 1; C1:L61 to C2:L14 & C4:L45-48 of US 6,753,218)
In regards to claim 16, Devoe ‘080 discloses
The capacitive device according to claim 1, wherein a front projection of the first polar plate and/or the second polar plate on the substrate is a polygon, a circle, an ellipse, or an irregular shape (fig. 1).
In regards to claim 18, Devoe ‘080 discloses
An electronic apparatus, comprising the capacitive device according to claim 1 (fig. 1).
In regards to claim 19, Devoe ‘080 discloses
The electronic apparatus according to claim 18, wherein the electronic apparatus further comprises a printed circuit board (34 – fig. 1; C4:L9-30 & C1:L61 to C2:L14 & C14:L23-28 of US 6,753,218), a chip (38 – fig. 1; C4:L9-30), and a bond wire (36 – fig. 1; C4:L9-30); the capacitive device and the chip are provided on the same side of the printed circuit board; a surface of the printed circuit board is provided with a pad; a first electrode layer of the capacitive device is soldered on the pad; one end of the bond wire is connected to the chip, and the other end of the bond wire is connected to the capacitive device (fig. 1)
In regards to claim 20, Devoe ‘080 discloses
The electronic apparatus of claim 19, wherein the second polar plate of the capacitive device is further away from the substrate than the first polar plate (fig. 1); the capacitive device further comprises a second electrode layer (74 – fig. 1; C4:L9-30) and an insulation layer (ceramic layer between 74 & 70 – fig. 1; C4:L9-30); the second electrode layer is located on a side of the second polar plate away from the substrate; the insulation layer is located between the second electrode layer and the second polar plate (fig. 1); the second electrode layer is electrically connected to the second polar plate; and the other end of the bond wire is connected to the second electrode layer (fig. 1).
Claim(s) 1-2 & 7-8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kurihara et al. (US 2006/0180938).
In regards to claim 1, Kurihara ‘938 discloses
A capacitive device, comprising:
a substrate (36 – fig. 2; [0082]) having a first side and a second side opposite to each other in a thickness direction thereof;
a capacitor comprising a first polar plate (47 – fig. 2; [0095]), a dielectric layer (48 – fig. 2; [0095]), and a second polar plate (49 – fig. 2; [0095])stacked on the second side; and
a first electrode layer (portion of 41 formed on lower surface – fig. 1; [0082]) provided on the first side and electrically connected to the first polar plate, and the first electrode layer being configured to solder-connect to an external circuit (fig. 1; [0092]).
In regards to claim 2, Kurihara ‘938 discloses
The capacitive device according to claim 1, further comprising a conductive post (portion of 41 formed in 38 – fig. 2; [0088]) penetrating the substrate in a thickness direction of the substrate, wherein one end of the conductive post is electrically connected to the first electrode layer, and the other end of the conductive post is electrically connected to the first polar plate (fig. 2).
In regards to claim 7, Kurihara ‘938 discloses
The capacitive device according to claim 2, wherein a support post (portion of 39 formed in 38 – fig. 2; [0088]) is provided inside the conductive post, and one end of the support post facing the first polar plate supports the first polar plate; alternatively, the conductive posts are solid columnar structures made of a conductive material.
In regards to claim 8, Kurihara ‘938 discloses
The capacitive device according to claim 7, wherein the support post comprises an organic material ([0089]).
Claim(s) 1-2, 7, 9-14, 16-17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamasaki et al. (US 2006/0130303).
In regards to claim 1, Yamasaki ‘303 discloses
A capacitive device, comprising:
a substrate (301 – fig. 1; [0049]) having a first side and a second side opposite to each other in a thickness direction thereof;
a capacitor comprising a first polar plate (201 – fig. 1; [0037]), a dielectric layer (202 – fig. 1; [0037]), and a second polar plate (203 – fig. 1; [0037])stacked on the second side; and
a first electrode layer (304 – fig. 1; [0050]) provided on the first side and electrically connected to the first polar plate, and the first electrode layer being configured to solder-connect to an external circuit ([0088]).
In regards to claim 2, Yamasaki ‘303 discloses
The capacitive device according to claim 1, further comprising a conductive post (302 – fig. 1; [0050]) penetrating tie substrate in a thickness direction of the substrate, wherein one end of the conductive post is electrically connected to the first electrode layer, and the other end of the conductive post is electrically connected to the first polar plate (fig. 1).
In regards to claim 7, Yamasaki ‘303 discloses
The capacitive device according to claim 2, wherein a support post is provided inside the conductive post, and one end of the support post facing the first polar plate supports the first polar plate; alternatively, the conductive posts are solid columnar structures made of a conductive material ([0074]).
In regards to claim 9, Yamasaki ‘303 discloses
The capacitive device according to claim 1, wherein the second polar plate is further away from the substrate than the first polar plate (fig. 1).
In regards to claim 10, Yamasaki ‘303 discloses
The capacitive device according to claim 9, wherein the capacitive device further comprises a second electrode layer (603 – fig. 1; [0046]) and an insulation layer (501 & 601 – fig. 1; [0046]); the second electrode layer is located on a side of the second polar plate away from the substrate (fig. 1); the insulation layer is located between the second electrode layer and the second polar plate; the second electrode layer is electrically connected to the second polar plate (fig. 1); the second electrode layer is configured to solder-connect to an external circuit (fig. 1; [0047]).
In regards to claim 11, Yamasaki ‘303 discloses
The capacitive device according to claim 10, wherein the insulation layer is provided with a second via (602 – fig. 1; [0046]), and the second electrode layer is electrically connected to the second polar plate through the second via (fig. 1).
In regards to claim 12, Yamasaki ‘303 discloses
The capacitive device according to claim 10, wherein an edge of the insulation layer extends toward the substrate and covers an edge of the first polar plate, the dielectric layer, and the second polar plate (fig. 1).
In regards to claim 13, Yamasaki ‘303 discloses
The capacitive device according to claim 12, wherein the insulation layer comprises an organic material ([0076] & [0087]).
In regards to claim 14, Yamasaki ‘303 discloses
The capacitive device according to claim 9, wherein the second polar plate is configured to solder-connect to an external circuit (fig. 1; [0047]).
In regards to claim 16, Yamasaki ‘303 discloses
The capacitive device according to claim 1, wherein a front projection of the first polar plate and/or the second polar plate on the substrate is a polygon, a circle, an ellipse, or an irregular shape (fig. 1; polar plates inherently have a shape and thus read on said limitation).
In regards to claim 17, Yamasaki ‘303 discloses
A capacitive device, comprising:
a substrate (301 – fig. 1; [0049]) having a first side and a second side opposite to each other in a thickness direction thereof;
a capacitor comprising a first polar plate (201 – fig. 1; [0037]), a dielectric layer (202 – fig. 1; [0037]), and a second polar plate (203 – fig. 1; [0037])stacked on the second side; and
a first electrode layer (304 – fig. 1; [0050]) provided on the first side and electrically connected to the first polar plate, and the side of the first electrode layer away from the substrate being provided with an anti-oxidation layer (306 – fig. 1; [0088]) made of a conductive material.
Claim(s) 1 & 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 2019/0066922).
In regards to claim 1, Lee ‘922 discloses
A capacitive device, comprising:
a substrate (113 – fig. 2; [0038]) having a first side and a second side opposite to each other in a thickness direction thereof;
a capacitor comprising a first polar plate (121 – fig. 2; [0038]), a dielectric layer (112 – fig. 2; [0038-0039]), and a second polar plate (122 – fig. 2; [0038]) stacked on the second side; and
a first electrode layer (141 – fig. 2; [0036]) provided on the first side and electrically connected to the first polar plate, and the first electrode layer being configured to solder-connect to an external circuit (fig. 1 – electrode is capable of being soldered).
In regards to claim 15, Lee ‘922 discloses
The capacitive device according to claim 1, wherein the first polar plate comprises a plurality of first sub-polar plates (121 – fig. 2); the second polar plate comprises a plurality of second sub-polar plates (122 – fig. 2); the first sub-polar plates and the second sub-polar plates are staggered (fig. 2); adjacent two first sub-polar plates are electrically connected; and adjacent two second sub-polar plates are electrically connected (fig. 2; [0040]).
Claim(s) 1-5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Stevenson et al. (US 2005/0248907).
In regards to claim 1, Stevenson ‘907 discloses
A capacitive device, comprising:
a substrate (840 – fig. 53-55; [0199]) having a first side and a second side opposite to each other in a thickness direction thereof;
a capacitor (610 – fig. 54; [0200]) comprising a first polar plate (116 and/or 118), a dielectric layer, and a second polar plate (112 and/or 120) stacked on the second side (fig. 1 & fig. 54; [0127] & [0130]); and
a first electrode layer (146 – fig. 53-55; [0199]) provided on the first side and electrically connected to the first polar plate, and the first electrode layer being configured to solder-connect to an external circuit (capable of being soldered).
In regards to claim 2, Stevenson ‘907 discloses
The capacitive device according to claim 1, further comprising a conductive post (136 – fig. 54-55; [0200]) penetrating tie substrate in a thickness direction of the substrate, wherein one end of the conductive post is electrically connected to the first electrode layer, and the other end of the conductive post is electrically connected to the first polar plate (fig. 54).
In regards to claim 3, Stevenson ‘907 discloses
The capacitive device according to claim 2, wherein the capacitive device comprises a plurality of the conductive posts, and the plurality of the conductive posts are arranged at intervals (fig. 54-55).
In regards to claim 4, Stevenson ‘907 discloses
The capacitive device according to claim 3, wherein the conductive posts are provided adjacent to an edge of the substrate (fig. 53-55).
In regards to claim 5, Stevenson ‘907 discloses
The capacitive device according to claim 4, wherein the plurality of conductive posts are arranged in a circular pattern (fig. 53 & 55).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Duan in view of Anderson et al. (US 7,538,006).
In regards to claim 5,
Duan fails to disclose wherein the plurality of conductive posts are arranged in a circular pattern.
Anderson ‘006 discloses wherein the plurality of conductive posts are arranged in a circular pattern (fig. 3-4).
It would have been obvious to one of ordinary skill in the art prior the effective filing date of the claimed invention to form the vias of Duan to have a circular shape as taught by Anderson ‘006 as such a pattern is a design choice as taught by Anderson. Furthermore, it has been held that rearranging parts of an invention involved only routine skill in the art. In re Japikse, 86 USPQ 70 (CCPA 1950).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2019/0306982 – fig. 2; [0049] US 2018/0233553 – fig. 2
US 2017/0309405 – fig. 5 US 2024/0222018 – fig. 2
US 2015/0195905 – fig. 14 US 2011/0024171 – fig. 5
CN105514093B – fig. 10
US 6,410,954 – C3:L5-8 – via pattern is a design choice
Communication
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID M SINCLAIR whose telephone number is (571)270-5068. The examiner can normally be reached M-TH from 8AM-4PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TIMOTHY J DOLE can be reached at (571)272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David M Sinclair/Primary Examiner, Art Unit 2847
