Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Clams 1-14 are pending.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned [or implied] in the description: DLn-2, DLn-1, DLn in place of second set of DL1, DL2, DL3 at right of the figure.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities: paragraph [77] line 14 “FIG. 5” should be “FIG. 6”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 4 and 12 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 4 and 12 recite the limitation "the current controller" in line 2 There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1-5 and 7-13 are rejected under 35 US.C. 103 as being unpatentable over Park et al. (U.S. Patent Application 20160078841 A1, hereinafter “Park”) in view of Liu (U.S. Patent Application Publication 20180293955 A1).
Regarding Claim 1, Park teaches a display drive device (par 0033 Figs 1,2 data driver 300 of a display device 1000) comprising:
first and second buffers that are electrically connected to first and second panel link wires of a display panel (par 0048 Fig 2 first and second buffers BP1, BP2 are coupled to the data lines DL1, DL2 of the display panel 100, par 0040), respectively;
a first bias current transistor configured to supply a first bias current to the first buffer (paras 0090-0091 Figs 5,8 first bias current transistor, e.g. MTx, of BG1 is configured to supply a first bias current, IB1 or a portion thereof, to the first buffer BP1), and
a second bias current transistor configured to supply a second bias current to the second buffer (paras 0090-0091 Figs 6,8 second bias current transistor, e.g. MTx, of BG2 is configured to supply a second bias current, IB2 or a portion thereof, to the second buffer BP2); and
a first current controller configured to supply a gate current to each of the first and second bias current transistors (par 0086 Figs 5,6 first current controller combination of CRS and RT of BG1 and BG2 supplies a gate current to each of the first and second bias current transistors MTx of BG1 and MTx of BG2 respectively).
However, Park appears not to expressly teach wherein
the magnitude of the first bias current and the second bias current is determined based on a length of each of the first panel link wire and the second panel link wire .
Liu teaches wherein
the magnitude of the first bias current and the second bias current is determined based on a length of each of the first panel link wire and the second panel link wire (par 0050 Figs 12 the compensation control circuit can adjust the [bias] currents of the output buffer circuits, so as to adjust the slew rates of the output of the output buffer circuits to compensate [based on] the differences in delay times caused by the differences in the resistances between the data lines of the display panel; par 0004 Fig 1 the data line resistance differences resulting from varying fan-out/link-line lengths; i.e. the bias currents are determined based on lengths of the link wires).
Park and Liu are analogous art as they each pertain to display drive devices. It would have been obvious to a person of ordinary skill in the art to modify the display drive device of Park with the inclusion of the bias current adjustment based on data line lengths of Liu. The motivation would have been in order to provide improved display image uniformity (Liu par 0004).
Regarding Claim 2, Park as modified teaches the display drive device of claim 1, wherein
when the first panel link wire has a shorter length than the second panel link wire, the first bias current has a smaller value than the second bias current (Liu par 0004 when the first fanout line is shorter it has lower resistance causing faster rise times; paras 0026-0027 a smaller resistance fanout line, which uncompensated would have a faster rise time, may be equipped with an output buffer with less bias current such that it has a slower slew rate).
Park and Liu are analogous art as they each pertain to display drive devices. It would have been obvious to a person of ordinary skill in the art to modify the display drive device of Park with the inclusion of the lower bias current adjustment for a shorter data line length of Liu. The motivation would have been in order to provide a slower rise time buffer for a shorter-length, lower resistance link line (Liu par 0026).
Regarding Claim 3, Park as modified teaches the display drive device of claim 1, wherein
when the first panel link wire has a shorter length than the second panel link wire, a gate current input to the first bias current transistor has a smaller value than a gate current input to the second bias current transistor (Liu par 0004 Fig 1 when the first fanout line is shorter it has lower resistance causing faster rise times; paras 0026-0027 a smaller resistance fanout line, which uncompensated would have a faster rise time, may be equipped with an output buffer with less bias current such that it has a slower slew rate; Park par 0090 Fig 8 as each data line has its own BGi with bias transistors, when a BG is to output less bias current, the gate of its bias transistor is biased with a lesser gate current).
Park and Liu are analogous art as they each pertain to display drive devices. It would have been obvious to a person of ordinary skill in the art to modify the display drive device of Park with the inclusion of the lower bias current adjustment for a shorter data line length of Liu. The motivation would have been in order to provide a slower rise time buffer for a shorter-length, lower resistance link line (Liu par 0026).
Regarding Claim 4, Park as modified teaches the display drive device of claim 1, wherein
the first bias transistor is:
connected to the current controller via its gate electrode to receive the gate current input as an input, connected to a ground voltage GND via its source electrode, and connected to the first buffer via its drain electrode (Park par 0090 Fig 8 the first bias current transistor, e.g. MTx of BG1, is connected to the first current controller [combination of CRS and RT of BG1 and BG2] via its gate electrode to receive the gate current input as an input, connected to a ground voltage VSS via its source electrode, and electrically connected to the first buffer via its drain electrode [through switch Sx]).
Regarding Claim 5, Park as modified teaches the display drive device of claim 1, wherein
the source-drain current of the first bias current transistor is input to the first buffer as the first bias current (Park par 0090 Fig 8 the source-drain current of the first bias current transistor, e.g. MTx of BG1, is input to the first buffer BP1 as the first bias current, IB1 or at least a portion thereof).
Regarding Claim 7, Park as modified teaches the display drive device of claim 1, further comprising:
third and fourth buffers electrically connected to third and fourth panel link wires of the display panel, respectively (Park par 0048 Fig 2 third and fourth buffers BP3, BP4 are coupled to the data lines DL3, DL4 of the display panel 100, par 0040);
third and fourth bias current transistors configured to supply bias currents to the third and fourth buffers, respectively (Park paras 0090-0091 Figs 5,8 third bias current transistor, e.g. MTx, of BG3 is configured to supply a third bias current, IB3 or a portion thereof, to the third buffer BP3; fourth bias current transistor, e.g. MTx, of BG4 is configured to supply a fourth bias current, IB4 or a portion thereof, to the fourth buffer BP4); and
a second current controller configured to supply a gate current to each of the third and fourth bias current transistors (Park par 0086 Figs 5,6 second current controller combination of CRS and RT of BG3 and BG4 supplies a gate current to each of the third and fourth bias current transistors MTx of BG3 and MTx of BG4 respectively), wherein
the third and fourth bias current transistors supply the bias currents to the third and fourth buffers connected to the third and fourth panel link wires in proportion to the lengths of the third and fourth panel link wires, respectively (par 0050 Figs 12 the compensation control circuit can adjust the [bias] currents of the output buffer circuits, so as to adjust the slew rates of the output of the output buffer circuits to compensate [based on] the differences in delay times caused by the differences in the resistances between the data lines of the display panel; par 0004 Fig 1 the data line resistance differences resulting from varying fan-out/link-line lengths; i.e. the bias currents are determined based on lengths of the link wires).
Park and Liu are analogous art as they each pertain to display drive devices. It would have been obvious to a person of ordinary skill in the art to modify the display drive device of Park with the inclusion of the bias current adjustment based on data line lengths of Liu. The motivation would have been in order to provide improved display image uniformity (Liu par 0004).
Regarding Claim 8, Park teaches a display device (par 0033 Fig 1 display device 1000) comprising:
first and second data lines connected to pixels and configured to supply source signals (paras 0042,0048 Fig 1 DL1 and DL2 connected to pixels PX and configured to supply data voltage signals);
a data drive device configured to output the source signals to the first and second data lines (par 0033 Figs 1,2 data driver 300 of a display device 1000); and
first and second panel link wires configured to electrically connect the first and second data lines and the data drive device (par 0040 Fig 1 display panel 100 includes data lines DL1 to DLn; examiner construes wire portions between each data line DLi and the data driver 300 as panel link wires), wherein
the data drive device includes:
first and second buffers that are electrically connected to the first and second panel link wires, respectively (par 0048 Fig 2 first and second buffers BP1, BP2 are coupled to the data lines DL1, DL2 of the display panel 100, par 0040);
a first bias current transistor configured to supply a first bias current to the first buffer (paras 0090-0091 Figs 5,8 first bias current transistor, e.g. MTx, of BG1 is configured to supply a first bias current, IB1 or a portion thereof, to the first buffer BP1), and
a second bias current transistor configured to supply a second bias current to the second buffer (paras 0090-0091 Figs 6,8 second bias current transistor, e.g. MTx, of BG2 is configured to supply a second bias current, IB2 or a portion thereof, to the second buffer BP2); and
a first current controller configured to supply a gate current to each of the first and second bias current transistors (par 0086 Figs 5,6 first current controller combination of CRS and RT of BG1 and BG2 supplies a gate current to each of the first and second bias current transistors MTx of BG1 and MTx of BG2 respectively), and wherein
the magnitude of the first bias current and the second bias current is determined based on each length of the first panel link wire and the second panel link wire.
However, Park appears not to expressly teach
the device comprises first and second panel link wires configured to electrically connect the first and second data lines and the data drive device; wherein
the magnitude of the first bias current and the second bias current is determined based on a length of each of the first panel link wire and the second panel link wire.
Liu teaches
the device comprises first and second panel link wires configured to electrically connect the first and second data lines and the data drive device (par 0004 Fig 1 fan-out/link-line lengths vary; Fig 1 suggests e.g. DL1 is longer than DL2); wherein
the magnitude of the first bias current and the second bias current is determined based on a length of each of the first panel link wire and the second panel link wire (par 0050 Figs 12 the compensation control circuit can adjust the [bias] currents of the output buffer circuits, so as to adjust the slew rates of the output of the output buffer circuits to compensate [based on] the differences in delay times caused by the differences in the resistances between the data lines of the display panel; ; i.e. the bias currents are determined based on lengths of the link wires).
Park and Liu are analogous art as they each pertain to display drive devices. It would have been obvious to a person of ordinary skill in the art to modify the display drive device of Park with the inclusion of the bias current adjustment based on data line lengths of Liu. The motivation would have been in order to provide improved display image uniformity (Liu par 0004).
Claim 9 presents the limitations of Claim 2 in a different claim category, and therefore Claim 9 is rejected with a rationale similar to Claim 2, mutatis mutandis.
Claim 10 presents the limitations of Claim 3 in a different claim category, and therefore Claim 10 is rejected with a rationale similar to Claim 3, mutatis mutandis.
Regarding Claim 11, Park as modified teaches the display device of claim 8, wherein
the slew rate of a source signal output from the first buffer to the first data line via the first panel link wire and the slew rate of a source signal output from the second buffer to the second data line via the second panel link wire are substantially the same (Liu par 0026 Figs 12 the output buffer circuits can tend to discharge/charge the panel with a consistent speed).
Park and Liu are analogous art as they each pertain to display drive devices. It would have been obvious to a person of ordinary skill in the art to modify the display drive device of Park with the inclusion of the consistent buffer outputs slew rates of Liu. The motivation would have been in order to provide improved display image uniformity (Liu par 0004).
Claim 12 presents the limitations of Claim 4 in a different claim category, and therefore Claim 12 is rejected with a rationale similar to Claim 4, mutatis mutandis.
Claim 13 presents the limitations of Claim 5 in a different claim category, and therefore Claim 13 is rejected with a rationale similar to Claim 5, mutatis mutandis.
Allowable Subject Matter
Claims 6 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 6 (and similar Claim 14):
While closest prior art Park (20160078841 A1) and Liu (20180293955 A1) teach portions of the limitations of Claim 6, the prior art of record fails to teach or fairly suggest the particular limitations of Claim 6, namely "at least one bias resistor located between the first bias current transistor and the second bias current transistor" in combination with all other limitations of the claim and of claims on which the claim depends.
Conclusion
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/MARK EDWARDS/Primary Examiner, Art Unit 2624
