DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 17 is objected to because of the following informalities: there is no antecedent basis for “the fourth clock signal terminal”. Appropriate correction is required.
Claim 18 is objected to because of the following informalities: “A gate driving circuit, comprising a plurality of gate driving circuit units, wherein each of the gate driving circuits comprises the gate driving circuit unit according to claim 1.” Is there a single gate driving circuit or multiple gate driving circuits? Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 6, 7, 16, 17, and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (US 2015/0229302 A1).
Instant Claim 1: A gate driving circuit unit, (“The write driver & S/A block 380 (fig 8) may include the sense amplifier flip-flop 1 of FIG. 2.” (Kim, paragraph 100) The write driver & S/A block 380 of Kim corresponds to the gate driving circuit unit of the claim.)
comprising: a first input circuit, comprising a control terminal, (“The first inverter 40-1 (fig 2) may include a third PMOS transistor P3” (Kim, paragraph 41) The first inverter 40-1 and gate terminal of transistor P3 of Kim correspond to the first input circuit and control terminal of the claim, respectively.)
an input terminal and an output terminal, (Referring to fig 2 of Kim, the terminal of transistor P3 directly connected to power supply voltage VDD corresponds to the input terminal of the claim. The terminal of transistor N6 directly connected to node ND1 corresponds to the output terminal of the claim.)
wherein the input terminal of the first input circuit is connected with a first power supply voltage; (Referring to fig 2 of Kim, power supply voltage VDD corresponds to the first power supply voltage of the claim.)
a second input circuit, comprising a control terminal, (“the second inverter 40-2 (fig 2) may include a fourth PMOS transistor P4” (Kim, paragraph 41) The second inverter 40-2 and gate terminal of transistor P4 of Kim correspond to the second input circuit and control terminal of the claim, respectively.)
an input terminal and an output terminal; (Referring to fig 2 of Kim, the terminal of transistor P4 directly connected to power supply voltage VDD corresponds to the input terminal of the claim. The terminal of transistor N7 directly connected to node ND2 corresponds to the output terminal of the claim.)
an output circuit, comprising a control terminal, an input terminal and an output terminal, (“The switching circuit 20 (fig 2) may include a fifth NMOS transistor N5 between a ground voltage VSS source and a fifth node ND5.” (Kim, paragraph 39) The switching circuit 20 and gate terminal of transistor N5 of Kim correspond to the output circuit and control terminal of the claim, respectively.
The terminal of transistor N5 directly connected to node ND5 corresponds to the input terminal of the claim.
The terminal of transistor N5 directly connected to ground voltage VSS corresponds to the output terminal of the claim.)
wherein the input terminal of the output circuit is connected with a first clock signal terminal; (Referring to fig 2 of Kim, the terminals of transistor N5 are connected to clock signal CLK. The source terminal of clock signal CLK corresponds to the first clock signal terminal of the claim.)
a pre-charging circuit, comprising a control terminal, an input terminal and an output terminal, (“The pre-charging circuit 10 (fig 2) includes a first PMOS transistor P1 connected between a power supply voltage VDD source and a third node ND3,” (Kim, paragraph 38) The gate terminal of transistor P1 of Kim corresponds to the control terminal of the claim.
The terminal of transistor P1 directly connected to power supply voltage VDD corresponds to the input terminal of the claim.
The terminal of transistor P1 directly connected to node ND3 corresponds to the output terminal of the claim.)
wherein the control terminal of the pre-charging circuit is connected with a second clock signal terminal, (Referring to fig 2 of Kim, the control terminal of transistor P1 is directly connected to clock signal CLK. The source terminal of clock signal CLK corresponds to the second clock signal terminal of the claim.)
and the input terminal of the pre-charging circuit is connected with the first power supply voltage; (Referring to fig 2 of Kim, the “input” terminal of pre-charging circuit 10 is directly connected to power supply voltage VDD.)
and a first pull-down circuit, comprising a control terminal, an input terminal and an output terminal, (“The floating prevention circuit 50 (fig 2) generates third current I3 flowing to the first node ND1 according to the second input signal D2, and fourth current I4 flowing to the second node ND2 according to the first input signal D1.” (Kim, paragraph 34)
“The first current I1 (fig 2) and the fourth current I4 flow through the first node ND1 and the second node ND2, respectively, to drop voltages of the first node ND1 and the second node ND2.” (Kim, paragraph 56) Referring to fig 2 of Kim, the floating prevention circuit 50 containing first input signal D1 corresponds to the first pull-down circuit of the claim.
comprising a control terminal, an input terminal and an output terminal, (Referring to fig 2 of Kim, the gate terminal of transistor N4 corresponds to the control terminal of the claim.
The terminal of transistor N4 directly connected to node ND2 corresponds to the input terminal of the claim.
The terminal of transistor N4 directly connected to node ND5 corresponds to the output terminal of the claim.)
wherein the output terminal of the first input circuit and the input terminal of the second input circuit are connected with a first node, (Referring to fig 2 of Kim, node ND1 corresponds to the first node of the claim.)
the output terminal of the second input circuit and the control terminal of the output circuit are connected with a second node, (Referring to fig 2 of Kim, node ND2 corresponds to the second node of the claim.)
the output terminal of the pre-charging circuit and the control terminal of the second input circuit are connected with a third node, (Referring to fig 2 of Kim, node ND3 corresponds to the third node of the claim.)
the first pull-down circuit is configured to pull down a potential of the second node. (“The first current I1 (fig 2) and the fourth current I4 flow through the first node ND1 and the second node ND2, respectively, to drop voltages of the first node ND1 and the second node ND2.” (Kim, paragraph 56))
Instant Claim 2: The gate driving circuit unit according to claim 1, wherein the control terminal of the first pull-down circuit is connected with a third clock signal terminal, and is configured to pull down the potential of the second node in response to a signal on the third clock signal terminal. (The clock signal CLK of Kim drives the entire circuitry of fig 2.)
Instant Claim 6: The gate driving circuit unit according to claim 1, wherein the input terminal of the first pull-down circuit is connected to the second node, and the output terminal of the first pull-down circuit is connected with a second power supply voltage. (Referring to fig 2 of Kim, power supply voltage VDD corresponds to the second power supply voltage of the claim.)
Instant Claim 7: The gate driving circuit unit according to claim 6, wherein the first pull-down circuit comprises a first pull-down transistor and a second pull-down transistor, the first pull-down transistor comprises a gate electrode, a first electrode, and a second electrode, and the second pull- down transistor comprises a gate electrode, a first electrode, and a second electrode, the first electrode of the first pull-down transistor is connected with the second node, the second electrode of the first pull-down transistor is connected with the first electrode of the second pull-down transistor, and the second electrode of the second pull-down transistor is connected with the second power supply voltage. (“The first current I1 (fig 2) and the fourth current I4 flow through the first node ND1 and the second node ND2, respectively, to drop voltages of the first node ND1 and the second node ND2.” (Kim, paragraph 56) Referring to fig 2 of Kim, transistor N1 and transistor N4 correspond to the first pull-down transistor and second pull-down transistor of the claim, respectively.)
Instant Claim 16: The gate driving circuit unit according to claim 1, wherein the first input circuit comprises a first input transistor, the second input circuit comprises a second input transistor, the first input transistor comprises a gate electrode, a first electrode and a second electrode, and the second input transistor comprises a gate electrode, a first electrode and a second electrode, the first electrode of the first input transistor is connected with the first power supply voltage, the second electrode of the first input transistor is connected with the first electrode of the second input transistor, and the second electrode of the second input transistor is connected with the second node, (Referring to fig 2 of Kim, transistor P3 and transistor P4 correspond to the first input transistor and second input transistor of the claim, respectively.)
and the gate electrode of the first input transistor is connected with a fourth clock signal terminal, and the gate electrode of the second input transistor is connected with the third node. (Referring to fig 2 of Kim, the source terminal of clock signal CLK corresponds to the fourth clock signal terminal of the claim.)
Instant Claim 17: The gate driving circuit unit according to claim 1, wherein the first input circuit comprises a first input transistor and a third input transistor, the second input circuit comprises a second input transistor, the first input transistor comprises a gate electrode, a first electrode and a second electrode, the second input transistor comprises a gate electrode, a first electrode and a second electrode, and the third input transistor comprises a gate electrode, a first electrode and a second electrode, the second electrode of the first input transistor is connected with the first electrode of the third input transistor, (Referring to fig 2 of Kim, transistor P3, transistor N6, and transistor P4 correspond to the first input transistor, third input transistor, and second input transistor of the claim, respectively.)
and the first electrode of the first input transistor, the gate electrode of the first input transistor, and the gate electrode of the third input transistor are connected with the fourth clock signal terminal, the second electrode of the third input transistor and the first electrode of the second input transistor are connected to the first node, and the gate electrode of the second input transistor is connected with the third node. (Referring to fig 2 of Kim, the source terminal of clock signal CLK corresponds to the fourth clock signal terminal of the claim.)
Instant Claim 21: A driving method for a gate driving circuit unit, wherein the gate driving circuit unit comprises the gate driving circuit unit according to claim 1, and the driving method comprises: in a first stage, the pre-charging circuit responds to a signal on the second clock signal terminal, writes a first power supply voltage into the third node, and conducts a second input circuit; in a second stage, the first input circuit responds to a signal on the control terminal of the first input circuit, and pulls up the potential of the second node through the conducted second input circuit; in a third stage, the second node maintains a high level, and the output circuit responds to a signal of the second node, and outputs a signal on the first clock signal terminal as a gate drive signal; and in a fourth stage, the first pull-down circuit uses a second power supply voltage to pull down the potential of the second node. (Whichever point in time that the particular actions of claim 21 are taken in Kim, that point in time may be referred to as the stage corresponding to that in claim 21.)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim.
Instant Claim 18: A gate driving circuit, comprising a plurality of gate driving circuit units, wherein each of the gate driving circuits comprises the gate driving circuit unit according to claim 1. (“The flip-flop 1 (fig 2) may be used to restore data in a high-speed data transmission method.” (Kim, paragraph 36) Kim does not explicitly teach that multiple flip-flops 1 may be used in a circuit. However, according to section 2144.04 of the MPEP, under the heading Duplication of Parts, in the case of In re Harza “Although the reference did not disclose a plurality of ribs, the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced.”
Similarly in the case of Kim, it would be obvious to duplicate flip-flop 1.)
Instant Claim 19: The gate driving circuit according to claim 18, wherein the plurality of gate driving circuit units comprise a plurality of gate driving circuit unit groups, each of the plurality of gate driving circuit unit groups comprises a first gate driving circuit unit, a second gate driving circuit unit, a third gate driving circuit unit and a fourth gate driving circuit unit, (Referring to fig 2 of Kim, any particular electronic element may correspond to the gate driving circuit unit group of the claim.)
the first clock signal terminal of the first gate driving circuit unit is connected with a first clock signal line, the first clock signal terminal of the first gate driving circuit unit is connected with a second clock signal line, the first clock signal terminal of the first gate driving circuit unit is connected with a third clock signal line, and the first clock signal terminal of the first gate driving circuit unit is connected with a fourth clock signal line. (Referring to fig 2 of Kim, there are multiple instances of the use of clock signal CLK. Therefore, there is needed multiple clock signal CLK lines.)
Instant Claim 20: A display device, comprising the gate driving circuit according to claim 20. (“The amplified data output from the sense amplifier may include noise in various formed. For example, one type of noise is based on the type of data being amplified. Another type of noise is based on skew between the input data and clock signal. The noise adversely affects the amplified data output from the sense amplifier.” (Kim, paragraph 5) Although Kim does not explicitly teach that the sense amplifier may be used in a display device, it is obvious that the sense amplifier flip-flop 1 of FIG. 2 may be used for offsetting the noise associated with a display device.)
Allowable Subject Matter
Claims 3-5, 8-13, and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: With respect to claim 3, the prior art of record fails to teach or fairly suggest “a pull-down maintenance circuit, comprising a control terminal, an input terminal and an output terminal, wherein the input terminal of the pull-down maintenance circuit is connected with the third node, and the output terminal of the pull-down maintenance circuit is connected with the second clock signal terminal; and a gating circuit, comprising an input terminal, an output terminal and a plurality of gating sub- circuits connected in parallel between the input terminal and the output terminal of the gating circuit, wherein the input terminal of the gating circuit is connected with the control terminal of the pull-down maintenance circuit, and the output terminal of the gating circuit is connected with the third clock signal terminal”.
Claims 4 and 5 depend on claim 3, and thus, contain the same allowable subject matter as claim 3.
With respect to claim 8, the prior art of record fails to teach or fairly suggest “an inverter module, comprising a control terminal and an output terminal, wherein the control terminal of the inverter module is connected to the second node, and the output terminal of the inverter module is connected to a fourth node; and a first noise reduction circuit, comprising a control terminal, an input terminal and an output terminal, wherein the input terminal of the first noise reduction circuit is connected to the first node, the control terminal of the first noise reduction circuit is connected to the fourth node, and the output terminal of the first noise reduction circuit is connected with a second power supply voltage; and the input terminal of the first pull-down circuit is connected with the first power supply voltage, and the output terminal of the first pull-down circuit is connected to the fourth node”.
With respect to claim 9, the prior art of record fails to teach or fairly suggest “an inverter module, comprising a control terminal and an output terminal, wherein the control terminal of the inverter module is connected to the second node, and the output terminal of the inverter module is connected to a fourth node; and a first noise reduction circuit, comprising a control terminal, an input terminal and an output terminal, wherein the input terminal of the first noise reduction circuit is connected to the first node, the control terminal of the first noise reduction circuit is connected to the fourth node, and the output terminal of the first noise reduction circuit is connected with a second power supply voltage”.
Claims 10-13 and 15 depend on claim 9, and thus, contain the same allowable subject matter as claim 9.
Conclusion
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/YARON COHEN/Examiner, Art Unit 2626
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