DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 recites the limitation "the first wiring layer" in line 5. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination on the merits, “the first wiring layer” is being interpreted as “the fourth wiring layer” as claimed in claim 9 from which claim 10 is dependent.
Claims 11-14 are rejected due to their dependence on claim 10.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
Claims 1, 2, 4-6, 8-11, 13 and 15-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ishiwata et al. (United States Patent Application Publication 2019/0057989), hereinafter referenced as Ishiwata.
Regarding claim 1, Ishiwata discloses an imaging device comprising: a sensor board including a pixel region in which a plurality of pixels that performs photoelectric conversion is arranged side by side (figure 6 exhibits upper structural body 11 which includes a pixel region with a plurality of pixels which include photodiodes 16 as disclosed at paragraph 88); a circuit board bonded to one surface side of the sensor board (figure 6 exhibits lower structural body 12 which is bonded to the lower side of upper structural body 11), the circuit board including circuits that process signals input to the sensor board or signals output from the sensor board (paragraph 91 teaches that the lower structural body 12 is a signal processing substrate and paragraph 146 “a part of the column signal processing unit 25 is arranged in the lower structural body 12”); and a voltage supply terminal that is provided on an opposite side of a surface of the circuit board facing the sensor board and that supplies a power supply voltage or a reference voltage to the circuits (figure 6 exhibits terminals 14 which are power supply terminals as disclosed at paragraph 440), wherein at least a subset of the voltage supply terminal is arranged at a position overlapping the pixel region in a thickness direction of a multilayer board including the sensor board and the circuit board (figure 6 shows that terminal 14 overlaps the pixel region in the thickness direction of the multilayer board formed by the upper structural body 11 and lower structural body 12).
Regarding claim 2, Ishiwata discloses the imaging device according to claim 1, in addition, Ishiwata discloses wherein the circuit board includes: a first semiconductor layer having a first surface facing the sensor board and a second surface located on an opposite side of the first surface (figure 6 exhibits semiconductor substrate 81 as disclosed at paragraph 177), a first wiring layer arranged on the first surface side of the first semiconductor layer (figure 6 exhibits wiring layer 82 as disclosed at paragraph 177), and first vias penetrating between the first surface and the second surface of the first semiconductor layer (figure 6 exhibits vias 88 which go through both surfaces of the semiconductor layer 81 as disclosed at paragraph 176), the first vias are arranged at positions overlapping the pixel region in the thickness direction of the multilayer board (figure 6 shows vias 88 overlapping the pixel region in the thickness direction), and at least a subset of the voltage supply terminal is connected to the first wiring layer via the first vias (figure 6 shows that vias 88 are connected between terminal 14 and wiring layer 82).
Regarding claim 4, Ishiwata discloses the imaging device according to claim 2, in addition, Ishiwata discloses wherein the circuit board includes: a second wiring layer arranged on the second surface side of the first semiconductor layer (figure 6 exhibits rewiring line 90 as disclosed at paragraph 310), and the voltage supply terminal is connected to the first vias via the second wiring layer (figure 6 shows that the terminal 14 is connected to the vias 88 through rewiring line 90 as disclosed at paragraph 310).
Regarding claim 5, Ishiwata discloses the imaging device according to claim 1, addition, Ishiwata discloses signal terminals that are provided on the opposite side of the surface of the circuit board facing the sensor board and that input signals to the circuits or output signals from the circuits (figures 6 and 14 exhibit signal terminals on the side of the lower structural body 12 opposite the upper structural body 11), wherein the sensor board has a peripheral region located around the pixel region (figure 6 exhibits pixel peripheral circuit region 313 as disclosed at paragraph 182), and at least a subset of the signal terminals is arranged at positions overlapping the peripheral region in the thickness direction of the multilayer board (figure 14 exhibits a subset of signal terminals that overlap the peripheral region 313 which is outside of the pixel region as disclosed at paragraph 155; paragraph 183 teaches that terminal 14C may be on the lower side of pixel peripheral circuit, figure 6 shows that the pixel peripheral circuit is located in region 313 which is outside of the pixel area).
Regarding claim 6, Ishiwata discloses the imaging device according to claim 5, in addition, Ishiwata discloses wherein the circuit board includes: a first semiconductor layer having a first surface facing the sensor board and a second surface located on an opposite side of the first surface (figure 6 exhibits semiconductor substrate 81, as disclosed at paragraph 173, with 2 surfaces, one which faces the sensor portion and one opposite the first surface), a first wiring layer arranged on the first surface side of the first semiconductor layer (figure 6 exhibits a plurality of wiring layers 82 as disclosed at paragraph 177), and second vias penetrating between the first surface and the second surface of the first semiconductor layer (figure 14 shows peripheral vias 88 as disclosed at paragraph 178), the second vias are arranged at positions overlapping the peripheral region in the thickness direction of the multilayer board (figure 14 shows the vias located outside the pixel area as disclosed at paragraph 183), and at least a subset of the signal terminals is connected to the first wiring layer via the second vias (figure 14 shows that vias 88 are used to connected the signal terminals 14C to the wiring layers).
Regarding claim 8, Ishiwata discloses imaging device according to claim 2, in addition, Ishiwata discloses wherein the sensor board includes: a second semiconductor layer provided with the plurality of pixels (figure 6 exhibits semiconductor layer 101 which includes a plurality of pixels as disclosed at paragraphs 316 and 317), and a third wiring layer arranged between the second semiconductor layer and the circuit board (figure 6 exhibits wiring layers 102 as disclosed at paragraph 317), and a part of a conductor included in the first wiring layer and a part of a conductor included in the third wiring layer are bonded to each other (figure 8 shows that conductors in the first wiring layer and second wiring layer are bonded to each other as disclosed at paragraphs 194 and 195).
Regarding claim 9, Ishiwata discloses the imaging device according to claim 1, in addition, Ishiwata discloses wherein the sensor board includes: a second semiconductor layer provided with the plurality of pixels (figure 6 exhibits semiconductor layer 101 which includes a plurality of pixels as disclosed at paragraphs 316 and 317), and a third wiring layer arranged between the second semiconductor layer and the circuit board (figure 6 exhibits wiring layers 102 as disclosed at paragraph 317), the circuit board includes: a third semiconductor layer having a third surface facing the sensor board and a fourth surface located on an opposite side of the third surface (figure 6 exhibits semiconductor substrate 81, as disclosed at paragraph 173, with 2 surfaces, one which faces the sensor portion and one opposite the first surface), and a fourth wiring layer arranged on a third surface side of the third semiconductor layer (figure 6 exhibits a plurality of wiring layers 82 as disclosed at paragraph 177), and a part of a conductor included in the fourth wiring layer and a part of a conductor included in the third wiring layer are bonded to each other (figure 8 shows that conductors in the first wiring layer and second wiring layer are bonded to each other as disclosed at paragraphs 194 and 195).
Regarding claim 10, Ishiwata discloses the imaging device according to claim 9, in addition, Ishiwata discloses wherein the circuit board includes a fifth wiring layer arranged on a fourth surface side of the third semiconductor layer (figure 6 exhibits wiring layer 90 arranged on a fourth surface side of the layer 81 as disclosed at paragraph 310), and a part of a conductor included in the fifth wiring layer and a part of a conductor included in the first wiring layer are bonded to each other (figure 6 shows that wiring layer 90 and wiring layer 82 are bonded to each other through via 88).
Regarding claim 11, Ishiwata discloses the imaging device according to claim 10, wherein the circuit board includes third vias penetrating between the third surface and the fourth surface of the third semiconductor layer and connecting the fourth wiring layer and the fifth wiring layer to each other (figure 6 exhibits vias 88 connected the wiring layers 90 and 82), and the third vias are arranged at positions overlapping the pixel region in the thickness direction of the multilayer board (figure 6 shows that the vias overlap the pixel region).
Regarding claim 13, Ishiwata discloses the imaging device according to claim 11, in addition, Ishiwata discloses wherein the circuit board includes fourth vias penetrating between the third surface and the fourth surface of the third semiconductor layer and connecting the fourth wiring layer and the fifth wiring layer to each other (figure 14 exhibits vias 88 which connected the wiring layer 90 and 82), the sensor board has a peripheral region located around the pixel region (figure 14 exhibits peripheral region 313 as disclosed at paragraph 182), and the fourth vias are arranged at positions overlapping the peripheral region in the thickness direction of the multilayer board (figure 14 shows vias which overlap peripheral region 313).
Regarding claim 15, Ishiwata discloses the imaging device according to claim 1, in addition, Ishiwata discloses a plurality of the voltage supply terminals, wherein the plurality of voltage supply terminals is arranged side by side in a first direction and a second direction intersecting the first direction in plan view from the thickness direction of the multilayer board (figure 5 shows an array of supply terminals 14).
Regarding claim 16, Ishiwata discloses the imaging device according to claim 1, in addition, Ishiwata discloses a lens provided on an opposite side of the one surface of the sensor board (figure 6 exhibits microlenses 16 as disclosed at paragraph 90); and a color filter provided between the lens and the sensor board (figure 6 exhibits color filters 15 between the microlenses and pixels).
Regarding claim 17, Ishiwata discloses an electronic apparatus comprising: an imaging device (figure 54 exhibits image pickup device 3002 as disclosed at paragraph 513); and an optical system that causes the imaging device to form an image of image light from a subject (figure 54 exhibits lens group 3001 as disclosed at paragraph 513), wherein the imaging device includes: a sensor substrate having a pixel region in which a plurality of pixels that performs photoelectric conversion is arranged side by side (figure 6 exhibits upper structural body 11 which includes a pixel region with a plurality of pixels which include photodiodes 16 as disclosed at paragraph 88), a circuit board bonded to one surface side of the sensor board (figure 6 exhibits lower structural body 12 which is bonded to the lower side of upper structural body 11), the circuit board including circuits that process signals input to the sensor board or signals output from the sensor board (paragraph 91 teaches that the lower structural body 12 is a signal processing substrate and paragraph 146 “a part of the column signal processing unit 25 is arranged in the lower structural body 12”), and a voltage supply terminal that is provided on an opposite side of a surface of the circuit board facing the sensor board and that supplies a power supply voltage or a reference voltage to the circuits (figure 6 exhibits terminals 14 which are power supply terminals as disclosed at paragraph 440), and at least a subset of the voltage supply terminal is arranged at a position overlapping the pixel region in a thickness direction of a multilayer board including the sensor board and the circuit board (figure 6 shows that terminal 14 overlaps the pixel region in the thickness direction of the multilayer board formed by the upper structural body 11 and lower structural body 12).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Ishiwata in view in Cheng et al. (United States Patent Application Publication 2012/0112279), hereinafter referenced as Cheng.
Regarding claim 3, Ishiwata discloses imaging device according to claim 2, however, Ishiwata fails to disclose wherein diameter of the first vias is larger than or equal to a minimum gate length of transistors included in the circuits and smaller than or equal to 1000 nm.
Cheng is a similar or analogous system to the claimed invention as evidenced Cheng teaches a semiconductor device wherein the motivation of minimizing device size would have prompted a predictable variation of Ishiwata by applying Cheng’s known principal of wherein diameter of the first vias is larger than or equal to a minimum gate length of transistors included in the circuits and smaller than or equal to 1000 nm (paragraph 14 discloses a gate length of 22nm and a via diameter of 30nm).
In view of the motivations such as minimizing device size one of ordinary skill in the art would have implemented the claimed variation of the prior art system of Ishiwata.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention.
Regarding claim 12, Ishiwata discloses the imaging device according to claim 11, however, Ishiwata fails to disclose wherein diameter of the third vias is larger than or equal to a minimum gate length of transistors included in the circuits and smaller than or equal to 1000 nm.
Cheng is a similar or analogous system to the claimed invention as evidenced Cheng teaches a semiconductor device wherein the motivation of minimizing device size would have prompted a predictable variation of Ishiwata by applying Cheng’s known principal of wherein diameter of the first vias is larger than or equal to a minimum gate length of transistors included in the circuits and smaller than or equal to 1000 nm (paragraph 14 discloses a gate length of 22nm and a via diameter of 30nm).
In view of the motivations such as minimizing device size one of ordinary skill in the art would have implemented the claimed variation of the prior art system of Ishiwata.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention.
Claims 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Ishiwata in view of Tseng et al. (United States Patent Application Publication 2011/0024867), hereinafter referenced as Tseng.
Regarding claim 7, Ishiwata discloses the imaging device according to claim 6, in addition, Ishiwata discloses wherein the circuit board includes first vias penetrating between the first surface and the second surface of the first semiconductor layer (figure 6 exhibits vias 88 which go between the surfaces of substrate 81), the first vias are arranged at positions overlapping the pixel region in the thickness direction of the multilayer board (figure 6 shows that these vias overlap the pixel region), at least a subset of the voltage supply terminal is connected to the first wiring layer via the first vias (figure 6 exhibits terminals 14 which are power supply terminals as disclosed at paragraph 440; figure 6 further shows that these terminals connect to the wiring layer through the vias 88). However, Ishiwata fails to disclose the diameter of the second vias is larger than diameter of the first vias.
Ishiwata discloses vias in a peripheral region and vias in a pixel region having an unknown relationship between the diameters (see figures 6 and 14). Tseng teaches that vias in a peripheral region can have a greater diameter than vias in a pixel region (figure 5 exhibits via 115 with a greater diameter than via 102 a disclosed at paragraph 23). Because both Ishiwata and Tseng teach vias for an image sensor, it would have been obvious to a person having ordinary skill in the art to substitute the vias in a peripheral area which have a larger diameter than vias in a pixel area as taught by Tseng for the via diameters taught by Ishiwata to achieve the predictable result of forming vias which can vertically transmit signals and voltages within the image sensor.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention.
Regarding claim 14, Ishiwata discloses the imaging device according to claim 13, however, Ishiwata fails to disclose wherein diameter of the fourth vias is larger than diameter of the third vias.
Ishiwata discloses vias in a peripheral region and vias in a pixel region having an unknown relationship between the diameters (see figures 6 and 14). Tseng teaches that vias in a peripheral region can have a greater diameter than vias in a pixel region (figure 5 exhibits via 115 with a greater diameter than via 102 a disclosed at paragraph 23). Because both Ishiwata and Tseng teach vias for an image sensor, it would have been obvious to a person having ordinary skill in the art to substitute the vias in a peripheral area which have a larger diameter than vias in a pixel area as taught by Tseng for the via diameters taught by Ishiwata to achieve the predictable result of forming vias which can vertically transmit signals and voltages within the image sensor.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention.
Citation of Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Eghbal et al. (United States Patent Application Publication 2018/0203963) discloses via holes sizes for a semiconductor.
Umebayashi et al. (United States Patent Application Publication 2010/0238331) discloses an image sensor.
Yamashita (United States Patent Application Publication 2010/0045837) discloses an image sensor.
Conclusion
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JASON A. FLOHRE
Patent Examiner
Art Unit 2637
/JASON A FLOHRE/ Patent Examiner, Art Unit 2637
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