DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/11/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
Claims 4, 10, 15, and 17 have been cancelled. Claims 18-24 have been added. Claims 1-3, 5-9, 11-14, 16, and 18-24 are currently pending.
Claim Objections
Claims 5 and 13 are objected to because of the following informalities:
“with the sub-registers” in line 2 of claim 5 should read as “with a plurality of sub-registers”.
“to at least one of the devices” in line 2 of claim 13 should read as “to at least one of a plurality of devices”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 11-12 and 14 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Nee (US 2010/0020826).
Regarding claim 11, Nee teaches a frequency conversion module (Fig. 1, System 100 is a module for converting frequency), comprising: a parser (Fig. 1, Multiplication factor system 108 parses channel selection system data 110) and a plurality of frequency multipliers (Fig. 1, Multipliers 106A-N; Paragraph 0013, Multipliers 106A through 106N apply a predetermined multiplication factor to the signal provided by switch 104), wherein each of the frequency multipliers is connected to the parser, respectively (Fig. 1, Parser 108 is coupled to multipliers 106A-N); the parser is configured to parse acquired data to be parsed to acquire a plurality of sets of frequency conversion data (Fig. 1, Channel selection system 110 includes data of channel with conversion factor that is sent to parser 108; Paragraph 0014, channel selection system 110 can present user-selectable channel data, can receive control data that identifies or is correlated to a channel of data in a broadband data signal), each of which comprises an identifier of frequency multiplier and a frequency conversion value (Fig. 1, Parser 108 determines multiplication factor data (i.e. plurality of sets of frequency conversion data) with a channel identifier associated with a multiplier (i.e. identifier of frequency multiplier) and multiplication factor (i.e. frequency conversion value); Paragraph 0015, Multiplication factor system 108 receives channel data from channel selection system 110 or other suitable systems and generates multiplication factor data for multipliers 106A through 106N… multiplication factor system 108 can store a look-up table of multiplication factors associated with predetermined channels), and configured to send, based on the identifier of frequency multiplier in each set of the frequency conversion data, each set of the frequency conversion data to a corresponding frequency multiplier, respectively (Fig. 1, Parser 108 sends multiplication factor data to multipliers 106A-N based on channel selection using identifier; Paragraph 0013, multiplication factor system 108 can provide multiplication factors to multipliers 106A through 106N based on a channel selection received from channel selection system 110… Paragraph 0020, multiplication coefficients for the selected channel are set); and each of the frequency multipliers is configured to multiply an input frequency by a factor which is determined by the received frequency conversion value (Fig. 1, Multipliers 106A-N multiplies input frequency by factor; Paragraph 0015, multiplication factors generated by multiplication factor system 108 can be coordinated with the sampling frequency and the decimation data so as to generate an output signal at a predetermined sample rate… Paragraph 0022, samples are provided to multipliers that utilize the multiplication coefficients).
Regarding claim 12, Nee teaches the module of claim 11. Nee teaches the module further comprising an input device (Fig. 1, Receiver 102), wherein the input device is connected to each of the frequency multipliers (Fig. 1, Receiver 102 is connected to frequency multipliers 106A-N via switch 104), respectively, and is configured to transmit the input frequency to each of the frequency multipliers, respectively (Fig. 1, Signal is sent from 102 to 106A-N; Paragraph 0012, switch 104 receives a series of digital samples from receiver 102, and provides the samples in a predetermined order to multipliers 106A through 106N).
Regarding claim 14, Nee teaches the module of claim 11. Nee teaches a control method applied to the frequency conversion module of claim 11 comprising: sending data to be parsed to the parser, and controlling the parser to parse the data to be parsed to acquire the plurality of sets of frequency conversion data (Fig. 1, Channel selection system 110 includes data of channel with conversion factor that is sent to parser 108; Paragraph 0014, channel selection system 110 can present user-selectable channel data, can receive control data that identifies or is correlated to a channel of data in a broadband data signal), each of which comprises the name of frequency multiplier and the frequency conversion value (Fig. 1, Parser 108 determines multiplication factor data (i.e. plurality of sets of frequency conversion data) with a channel identifier associated with a multiplier (i.e. identifier of frequency multiplier) and multiplication factor (i.e. frequency conversion value); Paragraph 0015, Multiplication factor system 108 receives channel data from channel selection system 110 or other suitable systems and generates multiplication factor data for multipliers 106A through 106N… multiplication factor system 108 can store a look-up table of multiplication factors associated with predetermined channels); controlling the parser to send each set of the frequency conversion data to a matching frequency multiplier, respectively, based on the name of frequency multiplier in each set of the frequency conversion data (Fig. 1, Parser 108 sends multiplication factor data to multipliers 106A-N based on channel selection using identifier; Paragraph 0013, multiplication factor system 108 can provide multiplication factors to multipliers 106A through 106N based on a channel selection received from channel selection system 110… Paragraph 0020, multiplication coefficients for the selected channel are set); and controlling the frequency multiplier to multiply the input frequency by the factor which is determined by the received frequency conversion value (Fig. 1, Multipliers 106A-N multiplies input frequency by factor; Paragraph 0015, multiplication factors generated by multiplication factor system 108 can be coordinated with the sampling frequency and the decimation data so as to generate an output signal at a predetermined sample rate… Paragraph 0022, samples are provided to multipliers that utilize the multiplication coefficients).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 6, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Tang (Machine Translation of Chinese Patent Application CN 218647417 U) in view of Cok (US 2023/0351945).
Regarding claim 1, Tang teaches an input-output module (Fig. 1, Module) having M input pins (Fig. 1, M input pins 123-125; Paragraph 0057, the shift clock signal input pin 123, the storage clock signal input pin 124, the data signal input pin 125), a path switcher (Fig. 1, Serial-to-parallel switcher 12; Paragraph 0036, circuit includes a control module 11 and N series-to-parallel conversion modules 12), a shift register (Fig. 2 same embodiment as Figure 1, Shift register 121; Paragraph 0056, serial-to-parallel conversion module 12 includes a controller 127, a shift register 121) having N output pins (Fig. 1, N output pins 126; Paragraph 0057, multiple chip select signal output pins 126); wherein the M input pins are configured to receive input signals (Fig. 1, Signals 12-125 are received from control module 11; Paragraph 0065, series-to-parallel conversion module 12 between the control module 11 and the sensor array 13), and the M input pins comprise a path pin (Fig. 1, Shift clock signal input pin 123), an instruction pin (Fig. 1, Data signal input pin 125), and a shift pin (Fig. 1, Storage clock signal input pin 124), the N output pins are configured to be connected to a plurality of devices of an apparatus, respectively, output levels of the N output pins (Fig. 1, N output pins output high voltage level; Paragraph 0063, chip select signal output pin 126 corresponding to the channel with data "1" outputs a high level to select the sensor 131 connected to the corresponding pin 126 for communication; the chip select signal output pin 126 corresponding to the channel with data "0" outputs a low level) are configured to control whether to power on the plurality of devices or not (Fig. 1, N output pins 126 are coupled to plurality of devices 131 and used to power the devices; Paragraph 0049, multiple chip select signal output pins 126 (e.g., Q0-Q7)… Paragraph 0063, The high and low voltage levels can be set as needed. For example, the high voltage can be set to approximately 3.3V and the low voltage to approximately 0V), and M and N are positive integers (Fig. 1, M is 3 and N is at least 4); and the path switcher is configured to store, in response to an input signal of the path pin, an enable signal received from the instruction pin into the shift register (Fig. 1, Data signal input 125 (i.e. an enable signal from the instruction pin) is stored in shift register 121 based on shift clock signal (i.e. input signal of the path pin); Paragraph 0053, the series-to-parallel module 12 stores the data signal received through the data signal input pin 125 into the shift register based on the trigger of the shift clock signal), and the shift register is configured to output, in response to a shift signal of the shift pin, the stored enable signal to control the output levels of the N output pins (Fig. 1, Storage clock signal 124 (i.e. shift signal of the shift pin) causes shift register to output signals from N output pins; Paragraph 0054, send the storage clock signal to the series-to-parallel module 12, so that the series-to-parallel module 12 writes the data information in the shift register into the storage register based on the trigger of the received storage clock signal… Paragraph 0058, triggered by the storage clock signal received at the storage clock signal input pin 124, it writes the data signal stored in the shift register 121 into the storage register 122; and controls the output state of the plurality of chip select signal output pins 126 based on the data signal written into the storage register 122).
Tang does not teach an input-output module having a flip-flop to control the output levels of the N output pins.
Cok teaches an input-output module having a flip-flop to control the output levels of the N output pins (Fig. 4A, Memory banks 60 with serial pin and parallel out shift register comprises flip flops to output the parallel out; Paragraph 0048, shift registers comprising flip flops such as a serial shift register, a parallel shift register, or a serial-in/parallel-out shift register).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Tang’s input-output module to incorporate the teachings of Cok and have the serial-in/parallel-out module of Tang include flip-flops to output the signal.
One of ordinary skill in the art would be motivated to make the modifications in order to yield the obvious result of utilizing well-known and commonly used integrated circuitry hardware to implement serial-in/parallel-out circuitry via flip-flops thus enabling a small form-factor that is easily mass manufacturable.
Regarding claim 2, Tang in view of Cok teaches the module of claim 1. Tang teaches the module comprising wherein M is less than N (Fig. 1, M is 3 pins and N is 4 or more).
Regarding claim 6, Tang in view of Cok teaches the module of claim 1. Tang teaches a control method applied to the input-output module according to claim 1, comprising: sending an input signal to the path pin, for controlling the path switcher to store the enable signal received from the instruction pin into the shift register (Fig. 1, Data signal input 125 (i.e. an enable signal from the instruction pin) is stored in shift register 121 based on shift clock signal (i.e. input signal of the path pin); Paragraph 0053, the series-to-parallel module 12 stores the data signal received through the data signal input pin 125 into the shift register based on the trigger of the shift clock signal); and sending a shift signal to the shift pin, for controlling the shift register to output the stored enable signal so as to control the output levels of the N output pins (Fig. 1, Storage clock signal 124 (i.e. shift signal of the shift pin) causes shift register to output signals from N output pins; Paragraph 0054, send the storage clock signal to the series-to-parallel module 12, so that the series-to-parallel module 12 writes the data information in the shift register into the storage register based on the trigger of the received storage clock signal… Paragraph 0058, triggered by the storage clock signal received at the storage clock signal input pin 124, it writes the data signal stored in the shift register 121 into the storage register 122; and controls the output state of the plurality of chip select signal output pins 126 based on the data signal written into the storage register 122).
Cok teaches the control method having a flip-flop to control the output levels of the N output pins (Fig. 4A, Memory banks 60 with serial pin and parallel out shift register comprises flip flops to output the parallel out; Paragraph 0048, shift registers comprising flip flops such as a serial shift register, a parallel shift register, or a serial-in/parallel-out shift register).
Tang and Cok are analogous arts because they are in the same field of endeavor of using shift registers to perform control of peripheral devices.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Tang’s control method to incorporate the teachings of Cok and have the serial-in/parallel-out module of Tang to include flip-flops to output the signal.
One of ordinary skill in the art would be motivated to make the modifications in order to yield the obvious result of utilizing well-known and commonly used integrated circuitry hardware to implement serial-in/parallel-out circuitry via flip-flops thus enabling a small form-factor that is easily mass manufacturable.
Regarding claim 9, Tang in view of Cok teaches the module of claim 1. Tang teaches a chip comprising the input-output module according to claim 1 (Fig. 1, Chip; Paragraph 0041, control module 11 mentioned above can be a controller, a microcontroller (such as an MCU or FPGA), a microprocessor, or other data processing chip).
Claims 13 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Nee (US 2010/0020826) in view of Li (US 2021/0152728).
Regarding claim 13, Nee teaches the module of claim 11. Nee does not teach the module further comprising an enabler, wherein an input terminal of the enabler is connected to at least one of the devices, and an output terminal of the enabler is connected to at least one fill light; and the enabler is configured to enable the fill light.
Li teaches the module further comprising an enabler (Fig. 1, Processor 150), wherein an input terminal of the enabler is connected to at least one of the devices (Fig. 1, Processor 150 receives input from image sensor device 140), and an output terminal of the enabler is connected to at least one fill light (Fig. 1, Processor 150 has output to fill light lamp 110); and the enabler is configured to enable the fill light (Fig. 1, Processor 150 enables fill light lamp 110; Paragraph 0008, When the image sensor starts to generate the fill light frame, the processor may control the optical unit to enable fill light to shine on the image sensor).
Nee and Li are analogous arts because they are in the same field of performing communications through interface and/or wireless transmissions (See Li: Paragraph 0019).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Nee’s control method to incorporate the teachings of Li and include an image sensor, enabler processor, and fill light lamp that can be controlled by the enabler processor.
One of ordinary skill in the art would be motivated to make the modifications in order to provide advanced image collection and development to the network system of Nee (See Li: Paragraphs 0002 and 0003).
Regarding claim 16, Nee teaches the module of claim 11. Nee does not teach a chip comprising the module.
Li teaches a chip comprising the module (Fig. 1, Integrated chip system 100; Paragraph 0085, When a plurality of processors are included, the plurality of processors may be integrated into a same chip, or each of the plurality of processors may be an independent chip. One processor may include one or more physical cores, where the physical core is a smallest processing module).
Nee and Li are analogous arts because they are in the same field of performing communications through interface and/or wireless transmissions (See Li: Paragraph 0019).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Nee’s control method to incorporate the teachings of Li and include the wireless transmission module within a chip.
One of ordinary skill in the art would be motivated to make the modifications in order to yield the obvious result of providing a small form factor that is power efficient, reduces heat dissipation, and is easily mass-manufacturable.
Allowable Subject Matter
Claims 3, 5, and 7-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if the Claim Objection for claim 5 is overcome.
Claims 18-24 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 18, none of the cited references either alone or in combination teaches an input-output module having M input pins and N output pins, wherein the M input pins comprise a path pin, an instruction pin and a shift pin, and the input-output module comprises: a path switcher having an input terminal, a path terminal and N output terminals, a shift register having a shift terminal, N input terminals and N output terminals, and a flip-flop having N input terminals and N output terminals; wherein the input terminal of the path switcher is connected to the instruction pin, the path terminal of the path switcher is connected to the path pin, the N output terminals of the path switcher are connected to the N input terminals of the shift register in one to one correspondence, the path switcher is configured to transmit an enable signal provided by the path pin to one of the N output terminals of the path switcher which is indicated by a path switching signal provided by the instruction pin; the shift terminal of the shift register is connected to the shift pin, the N input terminals of the shift register are connected to the N output terminals of the path switcher in one-to-one correspondence, the N output terminals of the shift register are connected to the N input terminals of the flip-flop in one-to-one correspondence, the N input terminals of the shift register are in one-to-one correspondence with the N output terminals of the shift register, the shift register is configured to: receive at least one enable signal from at least one of the N input terminals of the shift register before a shift signal provided by the shift pin is received, and, send the at least one enable signal to at least one corresponding output terminal of the shift register when the shift signal provided by the shift pin is received; and the N output terminals of the flip-flop are connected to the N output pins in one-to-one correspondence, the N input terminals of the flip-flop are in one-to-one correspondence with the N output terminals of the flip-flop, and the flip-flop is configured to receive at least one enable signal from at least one of the N input terminals of the flip-flop, and flip an output level of at least one corresponding output terminal of the flip-flop.
US PGPUB 2006/0112202 to Thayyoor discloses bus logic circuitry that coupled to shift registers that control power to a plurality of devices. No mention of the shift register is configured to: receive at least one enable signal from at least one of the N input terminals of the shift register before a shift signal provided by the shift pin is received, and, send the at least one enable signal to at least one corresponding output terminal of the shift register when the shift signal provided by the shift pin is received is present.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US PGPUB 2023/0221435 to Griesbach discloses that wireless communication circuits are commonly implemented in integrated circuit chip form factors.
US PGPUB 2009/0175405 to Chen discloses that shift registers are conventionally classified as consisting of flip-flops.
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/H.Z.W./Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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