DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 36-39, 41-43, 46, 53 and 54 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sun et al. (US 2022/0327987).
Regarding claim 36
Sun et al. shows the display panel, comprising:
a shift register unit (see Fig. 10) and a plurality of output control signal lines (CN, G1-G12, see Figs. 1, 2, 6, 8 and 10) coupled to the shift register unit (see Figs. 1, 2, 6, 8 and 10);
the plurality of output control signal lines (CN, G1-G12) being arranged between the shift register unit coupled thereto and a display area (1) of the display panel (see Figs. 1, 2, 6, 8 and 10);
wherein the shift register unit (Fig. 10) comprises:
a shift register (A_1-A_4) configured to output a cascade signal (CN) through a cascade output terminal (CN, see Figs. 1, 2, 6, 8, 10 and 11);
an output circuit (7) coupled to the shift register, and the output circuit being configured to control a driving output terminal to output a gate scanning signal (OUT1/G1) according to a signal of an output control signal terminal (OUT_1) and a signal of a first reference signal terminal (VGL2), wherein the output control signal terminal (OUT_1) is coupled to one of the plurality of output control signal lines (G1-G12).
Regarding claim 37
Sun et al. further shows, wherein the output circuit (6 and 7) comprises:
a first output circuit (6) and a second output circuit (7);
the first output circuit (6) is coupled to the cascade output terminal (CN, see Fig. 11) or a first node (PU) in the shift register and is configured to transmit the signal of the output control signal terminal (CN) to the driving output terminal in response to a signal of the cascade output terminal (CN) or a signal of the first node (PU, see Fig. 11);
the second output circuit (7) is coupled to a second node (PD) in the shift register (see Fig. 11), and is configured to transmit the signal of the first reference signal terminal (VGL2) to the driving output terminal (OUT1-OUT3) in response to a signal of the second node (PD, see Fig. 11).
Regarding claim 38
Sun et al. further shows, wherein the first output circuit (6) comprises:
a first output transistor (T5);
a gate of the first output transistor is coupled to the cascade output terminal or the first node (PU, see Fig. 11), a first electrode of the first output transistor (T5) is coupled to the output control signal terminal (PU), and a second electrode of the first output transistor is coupled to the driving output terminal (PN); or
wherein the second output circuit comprises:
a second output transistor;
a gate of the second output transistor is coupled to the second node, a first electrode of the second output transistor is coupled to the first reference signal terminal, and a second electrode of the second output transistor is coupled to the driving output terminal.
Regarding claim 39
Sun et al. further shows, wherein the shift register comprises:
an input subcircuit (4) configured to provide a signal of an input signal terminal to a third node (Q, see Fig. 11) in response to a signal of a first clock signal terminal (CKB);
a control subcircuit (5 and 9) configured to control signals of the first node (PU) and the second node (PD), and provide a signal of the third node (Q) to the first node (PU, see Fig. 11) or the second node;
a cascade subcircuit (6) configured to enable the cascade output terminal (CN) to output the cascade signal (CN) in response to the signals of the first node (PU) and the second node (PD, see Fig. 11).
Regarding claim 41
Sun et al. further shows, a display panel (see Figs. 1, 2, 4, 6 and 8), comprising:
a base substrate (see para. 0002 and 0077) comprising a display area (1) and a non-display area (2);
wherein the display area comprises:
a plurality of sub-pixels (3);
a plurality of scan lines (G1-G12), wherein a row of sub-pixels in the plurality of sub-pixels is correspondingly coupled to at least one of the plurality of scan lines (G1-G12, see Figs. 1, 2, 4, 6 and 8);
wherein the non-display 2) area includes:
a gate driving circuit (2) comprising a plurality of shift register units in the display panel according to claim 36 (see Figs. 1, 2, 4, 6 and 8 and para. 0080), wherein the driving output terminal of each of the plurality of shift register units is correspondingly coupled to at least one of the plurality of scan lines (G1-G12, see Figs. 1, 2, 4, 6 and 8, and para. 0080 and 0088).
Regarding claim 42
Sun et al. further shows, a plurality of output control signal lines (G1-G12) coupled to the gate driving circuit (2); wherein an extension direction of the plurality of output control signal lines (taken to be the direction of the lines G1-12) is the same as an arrangement direction of the plurality of shift register units (see Figs. 1, 2, 4, 6 and 8).
Regarding claim 43
Sun et al. further shows, wherein the plurality of output control signal lines (G1-G12) are arranged between the gate driving circuit (2) coupled thereto and the display area (1) (see Figs. 1, 2, 4, 6 and 8).
Regarding claim 46
Sun et al. further shows, a plurality of clock signal lines (CK, CKB, CK1-CK3) coupled to the gate driving circuit (2);
wherein an extension direction of the plurality of clock signal lines is the same as an arrangement direction of the plurality of shift register units (taken to be inherent in order to connect each of the shift registers A_1-A-A_6 with the same the clock lines in each row of the shift registers, see Fig. 10).
Regarding claim 53
Sun et al. further shows, a display device, comprising:
the display panel according to claim 41;
a drive control circuit (2) coupled to the display panel, and configured to:
input a first output control signal (CN) to output control signal terminals of the plurality of shift register units in a case of adopting a full-screen driving mode, so that the plurality of shift register units sequentially output gate scanning signals (G1-G12) and drive the scan lines row by row (see Figs. 1, 2, 4, 6 and 8 and para. 0087, 0089 and 0098);
input a second output control signal (G1-G12) to the output control signal terminals of the plurality of shift register units in a case of adopting a local driving mode, so that some of the plurality of shift register units sequentially output gate scanning signals, and a rest of the plurality of shift register units output an invalid scanning signal (taken to be outputting the gate signals (G1-G12), sequentially for each row, see Figs. 2, 5, 7 and 9, and para. 0087, 0089 and 0098) and drive some of the scan lines (G1-G12).
Regarding claim 54
Sun et al. further shows, a driving control method, comprising:
in a case of adopting a full-screen driving mode, inputting a first output control signal (CN) to output control signal terminals of a plurality of shift register units (see Figs. 1, 2, 4, 6 and 8), so that the plurality of shift register units sequentially output gate scanning signals (G1-G12) and drive scan lines row by row (see Figs. 1, 2, 4, 6 and 8); (wherein the driving using the plurality of shift register units to drive corresponding scan lines using valid scanning signals in this scenario corresponds to a full-screen driving mode);
in a case of adopting a local driving mode, inputting a second output control signal (OUT_1) to the output control signal terminals (G1_G12) of the plurality of shift register units, so that some of the plurality of shift register units sequentially output gate scanning signals (see Figs. 1, 2, 4, 6 and 8) and a rest of the plurality of shift register units output an invalid scanning signal (taken to be outputting the gate signals (G1-G12), sequentially for each row, see Figs. 2, 5, 7 and 9, and para. 0087, 0089 and 0098) and drive some of the scan lines (G1-G12) (wherein the driving using some but not all of the plurality of shift register units to drive corresponding scan lines using valid scanning signals in this scenario corresponds to a local driving mode).
Allowable Subject Matter
Claims 40, 44, 45 and 47-52 and 55 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 40
The prior art of record, Sun et al. (US 2022/0327987), taken to be the closest prior art noted above, taken alone or in combination does not teach, suggest or render obvious the display panel, as recited in claim 39, having the further limitations which include:
wherein the input subcircuit comprises:
a first transistor;
a gate of the first transistor is coupled to the first clock signal terminal, a first electrode of the first transistor is coupled to the input signal terminal, and a second electrode of the first transistor is coupled to the third node; or
wherein the control subcircuit comprises:
a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a first capacitor, a second capacitor, a third capacitor and a fourth capacitor;
a gate of the second transistor is coupled to the third node, a first electrode of the second transistor is coupled to the first clock signal terminal, and a second electrode of the second transistor is coupled to a fourth node;
a gate of the third transistor is coupled to a second reference signal terminal, a first electrode of the third transistor is coupled to the fourth node, and a second electrode of the third transistor is coupled to a gate of the fourth transistor;
a first electrode of the fourth transistor is coupled to a second clock signal terminal, and a second electrode of the fourth transistor is coupled to a first electrode of the fifth transistor;
a gate of the fifth transistor is coupled to the second clock signal terminal, and a second electrode of the fifth transistor is coupled to the first node;
a gate of the sixth transistor is coupled to the first clock signal terminal, a first electrode of the sixth transistor is coupled to the input signal terminal, and a second electrode of the sixth transistor is coupled to a first electrode of the seventh transistor;
a gate of the seventh transistor is coupled to the second reference signal terminal, and a second electrode of the seventh transistor is coupled to a fifth node;
a gate of the eighth transistor is coupled to the fifth node, a first electrode of the eighth transistor is coupled to the fifth node, and a second electrode of the eighth transistor is coupled to the second node;
a gate of the ninth transistor is coupled to the first clock signal terminal, a first electrode of the ninth transistor is coupled to the second reference signal terminal, and a second electrode of the ninth transistor is coupled to a gate of the tenth transistor;
a first electrode of the tenth transistor is coupled to a third reference signal terminal, and a second electrode of the tenth transistor is coupled to a sixth node;
a gate of the eleventh transistor is coupled to the fifth node, a first electrode of the eleventh transistor is coupled to the sixth node, and a second electrode of the eleventh transistor is coupled to the second clock signal terminal;
a gate of the twelfth transistor is coupled to a first electrode of the fifteenth transistor, a first electrode of the twelfth transistor is coupled to the first node, and a second electrode of the twelfth transistor is coupled to a fourth reference signal terminal;
a gate of the thirteenth transistor is coupled to a fifth reference signal terminal, a first electrode of the thirteenth transistor is coupled to the fourth reference signal terminal, and a second electrode of the thirteenth transistor is coupled to a first electrode of the fourteenth transistor;
a gate of the fourteenth transistor is coupled to the first reference signal terminal, and a second electrode of the fourteenth transistor is coupled to the first electrode of the fifteenth transistor;
a gate of the fifteenth transistor is coupled to the first reference signal terminal, the first electrode of the fifteenth transistor is coupled to the third node, and a second electrode of the fifteenth transistor is coupled to the second node;
a first electrode of the first capacitor is coupled to the gate of the fourth transistor, and a second electrode of the first capacitor is coupled to the second electrode of the fourth transistor;
a first electrode of the second capacitor is coupled to the sixth node, and a second electrode of the second capacitor is coupled to the second electrode of the seventh transistor;
a first electrode of the third capacitor is coupled to the fourth reference signal terminal, and a second electrode of the third capacitor is coupled to the first node;
a first electrode of the fourth capacitor is coupled to the cascade output terminal, and a second electrode of the fourth capacitor is coupled to the first reference signal terminal; or
wherein the cascade subcircuit (6) comprises: a first cascade transistor (T5) and a second cascade transistor (T6);
a gate of the first cascade transistor (T5) is coupled to the first node (PU), a first electrode of the first cascade transistor is coupled to a fourth reference signal terminal, and a second electrode of the first cascade transistor is coupled to the cascade output terminal;
a gate of the second cascade transistor is coupled to the second node, a first electrode of the second cascade transistor is coupled to the cascade output terminal, and a second electrode of the second cascade transistor is coupled to the first reference signal terminal; or
wherein the input subcircuit comprises: a sixteenth transistor and a seventeenth transistor;
a gate of the sixteenth transistor is coupled to the first clock signal terminal, a first electrode of the sixteenth transistor is coupled to the input signal terminal, and a second electrode of the sixteenth transistor is coupled to a seventh node;
a gate of the seventeenth transistor is coupled to the first clock signal terminal, a first electrode of the seventeenth transistor is coupled to the seventh node, and a second electrode of the seventeenth transistor is coupled to the third node; or
wherein the control subcircuit comprises: an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a fifth capacitor, and a sixth capacitor;
a gate of the eighteenth transistor is coupled to the cascade output terminal, a first electrode of the eighteenth transistor is coupled to a third clock signal terminal, and a second electrode of the eighteenth transistor is coupled to a seventh node;
a gate of the nineteenth transistor is coupled to the input signal terminal, a first electrode of the nineteenth transistor is coupled to the first reference signal terminal, and a second electrode of the nineteenth transistor is coupled to the second node;
a gate of the twentieth transistor is coupled to the second node, a first electrode of the twentieth transistor is coupled to the first reference signal terminal, and a second electrode of the twentieth transistor is coupled to an eighth node;
a gate of the twenty-first transistor is coupled to the second node, a first electrode of the twenty-first transistor is coupled to the eighth node, and a second electrode of the twenty-first transistor is coupled to the third node;
a gate of the twenty-second transistor is coupled to the third node, a first electrode of the twenty-second transistor is coupled to the eighth node, and a second electrode of the twenty-second transistor is coupled to a sixth reference signal terminal;
a gate of the twenty-third transistor is coupled to a fourth clock signal terminal, a first electrode of the twenty-third transistor is coupled to the second node, and a second electrode of the twenty-third transistor is coupled to the sixth reference signal terminal;
a first electrode of the fifth capacitor is coupled to the first reference signal terminal, and a second electrode of the fifth capacitor is coupled to the first electrode of the twenty- third transistor;
a first electrode of the sixth capacitor is coupled to the cascade output terminal, and a second electrode of the sixth capacitor is coupled to the first node; or
wherein the cascade subcircuit comprises: a first cascade transistor and a second cascade transistor;
a gate of the first cascade transistor is coupled to the first node, a first electrode of the first cascade transistor is coupled to the cascade output terminal, and a second electrode of the first cascade transistor is coupled to a third clock signal terminal;
a gate of the second cascade transistor is coupled to the second node, a first electrode of the second cascade transistor is coupled to the first reference signal terminal, and a second electrode of the second cascade transistor is coupled to the cascade output terminal; or
wherein the control subcircuit comprises: a twenty-fourth transistor, a twenty-fifth transistor, a twenty-sixth transistor, a twenty-seventh transistor, a twenty-eighth transistor, a seventh capacitor, and an eighth capacitor;
a gate of the twenty-fourth transistor is coupled to the first clock signal terminal, a first electrode of the twenty-fourth transistor is coupled to a seventh reference signal terminal, and a second electrode of the a transistor is coupled to the second node;
a gate of the twenty-fifth transistor is coupled to the third node, a first electrode of the twenty-fifth transistor is coupled to the second node, and a second electrode of the twenty-fifth transistor is coupled to the first clock signal terminal;
a gate of the twenty-sixth transistor is coupled to the second node, a first electrode of the twenty-sixth transistor is coupled to the first reference signal terminal, and a second electrode of the twenty-sixth transistor is coupled to a first electrode of the twenty-seventh transistor;
a gate of the twenty-seventh transistor is coupled to a third clock signal terminal, and a second electrode of the twenty-seventh transistor is coupled to a first electrode of the twenty-eighth transistor;
a gate of the twenty-eighth transistor is coupled to the seventh reference signal terminal, a first electrode of the twenty-eighth transistor is coupled to the third node, and a second electrode of the twenty-eighth transistor is coupled to the first node;
a first electrode of the seventh capacitor is coupled to the first reference signal terminal, and a second electrode of the seventh capacitor is coupled to the first node;
a first electrode of the eighth capacitor is coupled to the cascade output terminal, and a second electrode of the eighth capacitor is coupled to the first node, as recited in claim 40.
Further, even though Sun et al. shows the invention as claimed, as discussed above in the above rejections, it does not specifically show or render obvious the limitations of claim 40, noted above.
Therefore, it is believed that one of ordinary skilled in the art at the time the invention was filed, would not consider it obvious to modify Sun et al., with any of the prior art of record, to include the limitations as recited in claim 40.
Regarding claim 44
The prior art of record, Sun et al. (US 2022/0327987), taken to be the closest prior art noted above, taken alone or in combination does not teach, suggest or render obvious the display panel, as recited in claim 43, having the further limitations which include:
wherein in two adjacent shift register units among the plurality of shift register units, an input signal terminal of a next shift register unit is coupled to a cascade output terminal of a previous shift register unit;
the plurality of output control signal lines comprise:
a first output control signal line and a second output control signal line;
the first output control signal line is coupled to output control signal terminals of odd-numbered shift register units, and the second output control signal line is coupled to output control signal terminals of even-numbered shift register units, as recited in claim 44.
Further, even though Sun et al. shows the invention as claimed, as discussed above in the above rejections, it does not specifically show or render obvious the limitations of claim 44, noted above.
Therefore, it is believed that one of ordinary skilled in the art at the time the invention was filed, would not consider it obvious to modify Sun et al., with any of the prior art of record, to include the limitations as recited in claim 44.
Regarding claim 45
The prior art of record, Sun et al. (US 2022/0327987), taken to be the closest prior art noted above, taken alone or in combination does not teach, suggest or render obvious the display panel, as recited in claim 42, having the further limitations which include:
a plurality of output control auxiliary signal lines; wherein a first insulating layer is provided between the plurality of output control auxiliary signal lines and the plurality of output control signal lines; the plurality of output control auxiliary signal lines correspond to the plurality of output control signal lines in a one-to-one manner, and the output control auxiliary signal lines and the output control signal lines corresponding to each other are coupled to each other through first through holes penetrating the first insulating layer, as recited in claim 45.
Further, even though Sun et al. shows the invention as claimed, as discussed above in the above rejections, it does not specifically show or render obvious the limitations of claim 45, noted above.
Therefore, it is believed that one of ordinary skilled in the art at the time the invention was filed, would not consider it obvious to modify Sun et al., with any of the prior art of record, to include the limitations as recited in claim 45.
Regarding claim 47
The prior art of record, Sun et al. (US 2022/0327987), taken to be the closest prior art noted above, taken alone or in combination does not teach, suggest or render obvious the display panel, as recited in claim 46, having the further limitations which include:
wherein the plurality of clock signal lines are arranged on a side of the gate driving circuit coupled thereto away from the display area; or
wherein orthographic projections of the plurality of output control signal lines on the base substrate are arranged between orthographic projections of the plurality of clock signal lines on the base substrate and the display area; or
wherein an orthographic projection of the gate driving circuit on the base substrate is arranged between orthographic projections of the plurality of clock signal lines on the base substrate and orthographic projections of the plurality of output control signal lines on the base substrate, and the orthographic projections of the plurality of output control signal lines on the base substrate are arranged between the orthographic projection of the gate driving circuit on the base substrate and the display area, as recited in claim 47.
Further, even though Sun et al. shows the invention as claimed, as discussed above in the above rejections, it does not specifically show or render obvious the limitations of claim 47, noted above.
Therefore, it is believed that one of ordinary skilled in the art at the time the invention was filed, would not consider it obvious to modify Sun et al., with any of the prior art of record, to include the limitations as recited in claim 47.
Regarding claim 48
The prior art of record, Sun et al. (US 2022/0327987), taken to be the closest prior art noted above, taken alone or in combination does not teach, suggest or render obvious the display panel, as recited in claim 41, having the further limitations which include:
wherein an orthographic projection of the first output transistor on the base substrate is between an orthographic projection of the first cascade transistor on the base substrate and the display area, as recited in claim 48.
Further, even though Sun et al. shows the invention as claimed, as discussed above in the above rejections, it does not specifically show or render obvious the limitations of claim 48, noted above.
Therefore, it is believed that one of ordinary skilled in the art at the time the invention was filed, would not consider it obvious to modify Sun et al., with any of the prior art of record, to include the limitations as recited in claim 48.
Regarding claims 49 and 50
The prior art of record, Sun et al. (US 2022/0327987), taken to be the closest prior art noted above, taken alone or in combination does not teach, suggest or render obvious the display panel, as recited in claim 41, having the further limitations which include:
wherein a width of a channel of the first output transistor is greater than a width of a channel of the first cascade transistor, as recited in claims 49 and 50.
Further, even though Sun et al. shows the invention as claimed, as discussed above in the above rejections, it does not specifically show or render obvious the limitations of claims 49 and 50, noted above.
Therefore, it is believed that one of ordinary skilled in the art at the time the invention was filed, would not consider it obvious to modify Sun et al., with any of the prior art of record, to include the limitations as recited in claims 49 and 50.
Regarding claims 51 and 52
The prior art of record, Sun et al. (US 2022/0327987), taken to be the closest prior art noted above, taken alone or in combination does not teach, suggest or render obvious the display panel, as recited in claim 41, having the further limitations which include:
wherein an orthographic projection of the second output transistor on the base substrate is between an orthographic projection of the second cascade transistor on the base substrate and the display area; or wherein a width of a channel of the second output transistor is greater than a width of a channel of the second cascade transistor, as recited in claims 51 and 52.
Further, even though Sun et al. shows the invention as claimed, as discussed above in the above rejections, it does not specifically show or render obvious the limitations of claims 51 and 52, noted above.
Therefore, it is believed that one of ordinary skilled in the art at the time the invention was filed, would not consider it obvious to modify Sun et al., with any of the prior art of record, to include the limitations as recited in claims 51 and 52.
Regarding claim 55
The prior art of record, Sun et al. (US 2022/0327987), taken to be the closest prior art noted above, taken alone or in combination does not teach, suggest or render obvious the driving control method, as recited in claim 54, having the further limitations which include:
wherein the first output control signal is a fixed voltage signal with a first level; or
wherein the second output control signal comprises a fixed voltage signal portion with a first level and a fixed voltage signal portion with a second level, the fixed voltage signal portion with the first level is input into the some of the plurality of shift register units, and the fixed voltage signal portion with the second level is input into the rest of the plurality of shift register units; or
wherein the first output control signal is a clock signal; or
wherein the second output control signal comprises a clock signal portion and a fixed voltage signal portion with a first level;
the clock signal portion of the second output control signal is input to the some of the plurality of the shift register units, and the fixed voltage signal portion with the first level is input to the rest of the plurality of shift register units, as recited in claim 55.
Further, even though Sun et al. shows the invention as claimed, as discussed above in the above rejections, it does not specifically show or render obvious the limitations of claim 55, noted above.
Therefore, it is believed that one of ordinary skilled in the art at the time the invention was filed, would not consider it obvious to modify Sun et al., with any of the prior art of record, to include the limitations as recited in claim 55.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wu et al. (US 2023/0059832), shows a display panel, comprising: a shift register unit (see Figs. 4 and 5) and a plurality of output control signal lines (NEXT and Gout) coupled to the shift register unit; the plurality of output control signal lines being arranged between the shift register unit coupled thereto and a display area of the display panel; and a shift register configured to output a cascade signal through a cascade output terminal (see the abstract, Figs. 1-22, and para. 0040-0073).
Wang et al. (US 2022/0398968), shows a display panel, comprising: a shift register unit and a plurality of output control signal lines coupled to the shift register unit; the plurality of output control signal lines being arranged between the shift register unit coupled thereto and a display area of the display panel; and a shift register configured to output a cascade signal through a cascade output terminal (see the abstract, Figs. 1-12, and para. 0113-0168).
Park et al. (US 2008/0055225), shows a display panel, comprising: a shift register unit and a plurality of output control signal lines coupled to the shift register unit; the plurality of output control signal lines being arranged between the shift register unit coupled thereto and a display area of the display panel; and a shift register configured to output a cascade signal through a cascade output terminal (see the abstract, Figs. 1-9, and para. 0036-0091).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUHAMMAD N EDUN whose telephone number is (571)272-7617. The examiner can normally be reached Mon-Fri 10:00-6:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BENJAMIN C. LEE can be reached on (571) 272-2963. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MUHAMMAD N. EDUN/
Primary Patent Examiner
Art Unit 2629
/MUHAMMAD N EDUN/Primary Examiner, Art Unit 2629