DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 is objected to because of the following informalities: lines 12-13 recite “the light-emitting control signal line” which appears to be “the light-emitting control signal lines”. Appropriate correction is required.
Claim 8 is objected to because of the following informalities: line 12 recite “the conductor portion” which appears to be “the conductor portions”. Claim 15 recites similar limitations. Appropriate corrections are required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shang et al. U.S. Patent Publication No. 2022/0328570 (hereinafter Shang) in view of Yoon et al. U.S. Patent Publication No. 2021/0343234 (hereinafter Yoon).
Consider claim 1, Shang teaches a display substrate, comprising: a base substrate (Figure 1, 10), and a plurality of light-emitting control signal lines, a plurality of power supply lines and a plurality of sub-pixels all arranged on the base substrate (Figure 8 and [0091], EM1-EM2, VDD-VSS, 0221), wherein the sub-pixels comprise a sub-pixel driving circuit and a light-emitting element (Figure 8, 0221); the sub-pixel driving circuit comprise a driving transistor, a power control transistor and a light-emitting control transistor; a first electrode of the power control transistor is coupled to a corresponding power line, and a second electrode of the power control transistor is coupled to a first electrode of the driving transistor (Figure 8, T4, T1 and respective connections); a first electrode of the light-emitting control transistor is coupled to a second electrode of the driving transistor, and a second electrode of the light-emitting control transistor is coupled to the light-emitting element (Figure 8, T5, 0220 and respective connections); in the same sub-pixel driving circuit, a gate of the power control transistor and a gate of the light-emitting control transistor are coupled to different light-emitting control signal lines (Figure 8, EM1, EM2; [0098], the gate electrode of the first light emitting control transistor T4 and the gate electrode of the second light emitting control transistor T5 may also be respectively electrically connected with different signal lines, that is, the gate electrode of the first light emitting control transistor T4 is electrically connected with the first light emitting control signal line EM1, the gate electrode of the second light emitting control transistor T5 is electrically connected with the second light emitting control signal line EM2); the light-emitting control signal line comprise at least two light-emitting control parts arranged along a first direction (Figure 8, EM1-EM2).
Shang does not appear to specifically disclose two adjacent light-emitting control parts are coupled, and two adjacent light-emitting control parts are arranged in different layers.
However, in a related field of endeavor, Yoon teaches a pixel circuit in figure 2 and further teaches two adjacent light-emitting control parts are coupled, and two adjacent light-emitting control parts are arranged in different layers ([0104-0105], lines 136 and 166).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide light-emitting control parts in different layers as taught by Yoon with the benefit that each pixel may have a simple structure. Because each pixel may have a simple structure, a high-resolution organic light-emitting display device may be realized as suggested in [0125].
Consider claim 2, Shang and Yoon teach all the limitations of claim 1. In addition, Shang teaches wherein the plurality of light-emitting control signal lines comprise a plurality of first light-emitting control signal lines and a plurality of second light-emitting control signal lines (Figure 8, EM1-EM2); in the same sub-pixel driving circuit, a gate of the power control transistor is coupled to the corresponding first light-emitting control signal line (Figure 8, EM1 and T4), a gate of the light-emitting control transistor is coupled to the corresponding second light-emitting control signal line (Figure 8, EM2 and T5), and at least part of the first light-emitting control signal line and at least part of the second light-emitting control signal line are located within the layout area of the same sub-pixel driving circuit (Figure 8, EM1 and EM2).
Consider claim 3, Shang and Yoon teach all the limitations of claim 2. In addition, Yoon teaches at least a portion of an orthographic projection of the first light-emitting control signal line on the base substrate (Figure 4, 136) is located between an orthographic projection of the gate of the power control transistor coupled thereto on the base substrate (Figure 4, G5 and 136) and an orthographic projection of the second light-emitting control signal line on the base substrate (Figure 4, part of 166 located in the right side of the pixel), see motivation to combine in claim 1.
Consider claim 8, Shang and Yoon teach all the limitations of claim 2. In addition, Shang teaches wherein the display substrate further comprises a plurality of first scanning lines (Figure 8, Ga1-Ga2); the sub-pixel driving circuit further comprises a compensation transistor, a gate of the compensation transistor is coupled to the corresponding first scanning line, a first electrode of the compensation transistor is coupled to the second electrode of the driving transistor, and the second electrode of the compensation transistor is coupled to the gate of the driving transistor (Figure 8, T3 and respective connections); the compensation transistor comprises a compensation active layer, wherein the compensation active layer comprises two channel portions and conductor portions respectively coupled to the two channel portions [0123]; the sub-pixel driving circuit also comprise a shielding portion and a first conductive connection portion [0123]; an orthographic projection of the shielding portion on the substrate at least partially overlaps with the orthographic projection of the conductor portion on the substrate [0123]; the first conductive connection portion is coupled to the shielding portion and the power line, respectively [0123].
Consider claim 9, Shang and Yoon teach all the limitations of claim 8. In addition, Shang teaches wherein the sub-pixel driving circuit further comprises a storage capacitor, a first plate of the storage capacitor is coupled to the gate of the driving transistor (Figure 8, C and T1); and the first conductive connection portion is further coupled to a second plate of the storage capacitor and /or a first electrode of the power control transistor (Figure 8, C and Vdd; [0123] and [0112], Vdd1).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shang and Yoon as applied to claim 3 above, and further in view of Kim et al. U.S. Patent Publication No. 2020/0143747 (hereinafter Kim).
Consider claim 4, Shang and Yoon teach all the limitations of claim 3. In addition, Shang teaches wherein the display substrate further comprises a plurality of data lines and a plurality of second scanning lines (Figure 8 and [0112], GA1-Ga2, Vd); the sub-pixel driving circuit further comprises a data writing transistor, a gate of the data writing transistor is coupled to the corresponding second scanning line, a first electrode of the data writing transistor is coupled to the corresponding data line, and a second electrode of the data writing transistor is coupled to the first electrode of the driving transistor (Figure 8, T2 and respective connections).
Shang does not appear to specifically disclose in a layout area of a same sub-pixel driving circuit, the first light-emitting control signal line, the second light-emitting control signal line and the second scanning line are arranged in sequence along a second direction, and the second direction intersects with the first direction.
However, in a related field of endeavor, Kim teaches in figure 2, a pixel circuit PXij and further teaches in a layout area of a same sub-pixel driving circuit, the first light-emitting control signal line, the second light-emitting control signal line and the second scanning line are arranged in sequence along a second direction, and the second direction intersects with the first direction (Figure 8 and [0105], Si, Ei and Ei-2).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing of the claimed invention to provide lines in sequence as taught by Kim with the benefit that the pixel circuit set the driving transistor thereof to an on-bias state, thereby preventing unintended light emission and generation of overcurrent and reducing power consumption as suggested in [0107].
Claim(s) 10-11, 15, 16 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shang and Yoon as applied to claim 1 above, and further in view of Gao U.S. Patent Publication No. 2021/0366386 (hereinafter Gao).
Consider claim 10, Shang and Yoon teach all the limitations of claim 1. In addition, Shang teaches wherein the plurality of light emission control signal lines comprise a plurality of third light emission control signal lines (Figure 8, EM1 and EM2 for a plurality of pixels); in the same sub-pixel driving circuit, the gate of the light-emitting control transistor is coupled to the corresponding third light-emitting control signal line (Figure 18, EM2 and T5), at least part of the third light- emitting control signal line is located within the layout area of the same sub-pixel driving circuit (Figure 8 and figure 10, EM).
Shang does not appear to specifically disclose the gate of the power control transistor is coupled to the third light-emitting control signal line coupled to the gate of the light-emitting control transistor in the previous sub-pixel driving circuit adjacent along the second direction.
However, in a related field of endeavor, Gao teaches a pixel circuit in figure 2 and further teaches the gate of the power control transistor is coupled to the third light-emitting control signal line coupled to the gate of the light-emitting control transistor in the previous sub-pixel driving circuit adjacent along the second direction [0102].
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide control sub-pixels as taught by Gao with the benefit that when the pixel circuits 10 are arranged in an array, for a row of pixel units, the first light emitting control signal may be a control signal for controlling the first light emitting control circuits 500 in the pixel circuits 10 of the row of pixel units. Also, this first light emitting control signal further controls the second light emitting control circuit 700 in the previous row of pixel circuits 10; similarly, the second light emitting control signal controls the second light emitting control circuit 700 in this row of pixel circuits 10, and this second light emitting control signal further controls the first light emitting control circuit 500 in the next row of pixel circuits 10. In addition, at the initialization, only the second light emitting control signal may be used as a turn-on signal as suggested in [0101-0102].
Consider claim 11, Shang, Yoon and Gao teach all the limitations of claim 10. In addition, Shang teaches wherein the sub-pixel driving circuit further comprises a second conductive connection portion, a first end of the second conductive connection portion is coupled to a gate of a power control transistor in a current sub-pixel driving circuit (Figure 8, EM1 and T4). In addition, Gao teaches and a second end of the second conductive connection portion is coupled to a third light-emitting control signal line coupled to a previous sub-pixel driving circuit adjacent to the current sub-pixel driving circuit along the second direction [0102], see motivation to combine in claim 10.
Consider claim 15, Shang, Yoon and Gao teach all the limitations of claim 10. In addition, Shang teaches wherein the display substrate further comprises a plurality of first initialization signal lines and a plurality of first scanning lines (Figure 8, Vinit1-2, Vdd and GA1-2); the sub-pixel driving circuit further comprises a compensation transistor, a gate of the compensation transistor is coupled to the corresponding first scanning line, a first electrode of the compensation transistor is coupled to the second electrode of the driving transistor, and the second electrode of the compensation transistor is coupled to the gate of the driving transistor (Figure 8, T3 and respective connections); the compensation transistor comprises a compensation active layer, wherein the compensation active layer comprises two channel portions and conductor portions respectively coupled to the two channel portions [0123]; the sub-pixel driving circuit further comprises a shielding portion, the shielding portion is coupled to the corresponding first initialization signal line [0123]; an orthographic projection of the shielding portion on the base substrate at least partially overlaps with an orthographic projection of the conductor portion on the base substrate [0123].
Consider claim 16, Shang, Yoon and Gao teach all the limitations of claim 10. In addition, Shang teaches wherein the sub-pixel driving circuit further comprises a first conductive connection portion (Figure 8, Vdd) and a storage capacitor; the first plate of the storage capacitor is coupled to the gate of the driving transistor (Figure 8, C and T1); the first conductive connection portion is respectively coupled to the power line, a second plate of the storage capacitor, and the first electrode of the power control transistor (Figure 8, C, Vdd, T4).
Consider claim 20, Shang and Yoon teach all the limitations of claim 2. In addition, Yoon teaches wherein the display substrate comprises a display area (Figure 1, DA and SD) and a peripheral area located around the display area; the display substrate further comprise a plurality of first shift register units all located in the peripheral area (Figure 1, SD); in the same sub-pixel driving circuit, the second light-emitting control signal line coupled to the gate of the light-emitting control transistor is coupled to the corresponding first shift register unit (Figure 2, EM[i] and T6).
Yoon does not appear to specifically disclose the first light-emitting control signal line coupled to the gate of the power control transistor is coupled to the first shift register unit coupled to the gate of the light-emitting control transistor in the sub-pixel driving circuit adjacent along the second direction.
However, Gao teaches the first light-emitting control signal line coupled to the gate of the power control transistor is coupled to the first shift register unit coupled to the gate of the light-emitting control transistor in the sub-pixel driving circuit adjacent along the second direction [0102].
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide control sub-pixels as taught by Gao with the benefit that when the pixel circuits 10 are arranged in an array, for a row of pixel units, the first light emitting control signal may be a control signal for controlling the first light emitting control circuits 500 in the pixel circuits 10 of the row of pixel units. Also, this first light emitting control signal further controls the second light emitting control circuit 700 in the previous row of pixel circuits 10; similarly, the second light emitting control signal controls the second light emitting control circuit 700 in this row of pixel circuits 10, and this second light emitting control signal further controls the first light emitting control circuit 500 in the next row of pixel circuits 10. In addition, at the initialization, only the second light emitting control signal may be used as a turn-on signal as suggested in [0101-0102].
Allowable Subject Matter
Claims 5-7, 12-14 and 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: Prior arts do not appear to disclose the overlaps mentioned in claims 5, 12 in combination to other limitations of the base claims and any intervening claims.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/ROBERTO W FLORES/Primary Examiner, Art Unit 2621
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