Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the application filed 1/15/2025 in which Claims 1-13, 15, 17, 20, 21, 26, 27, 29 are pending where Claims 14, 16, 18, 19, 22-25, 28 are cancelled by preliminary amendment.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 2, 4, 5, 12, 17, 20, 26 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication 2022/0392382 to Park et al (“Park”) in view of U.S. Patent Publication 2024/0346992 to Zhang.
As to Claim 1, Park teaches a display device, comprising: a plurality of sub-pixels arranged in an array comprising rows and columns (The display panel 100 has a display region on which an image is displayed, see ¶ 0064; The display panel 100 includes a plurality of gate lines GWL, GIL and GCL, a plurality of bias lines EBL, a plurality of data lines DL, a plurality of emission lines EL1 and EL2 and a plurality of pixels electrically connected to the gate lines GWL, GIL and GCL, the bias lines EBL, the data lines DL and the emission lines EL1 and EL2. The gate lines GWL, GIL and GCL and the bias lines EBL extend in a first direction D1, the data lines DL extend in a second direction D2 crossing the first direction D1 and the emission lines EL1 and EL2 extend in the first direction D1, see ¶ 0065); and
a driving circuit connected to the plurality of sub-pixels, wherein the driving circuit is configured to: in a case of displaying at a first frequency, take each frame as a refresh frame, generate a driving signal for the refresh frame (a first frame may have a frame rate of 240 Hz in FIG. 13. 240 Hz may be the normal frequency. When the driving frequency is the normal frequency, the display panel 100 may only have the writing frames [refresh frames], see ¶ 0113), and
apply the generated driving signal for the refresh frame and a data signal to the plurality of sub-pixels of the display device, so that the plurality of sub-pixels receive the data signal and emit light, under control of the driving signal for the refresh frame (The first frame is the writing frame, so that the first bias operation of the first pixel switching element T1 may be operated using the initialization voltage VINT and the high power voltage ELVDD, see ¶ 0114; the pixel may operate an initialization operation and a data writing operation in a first duration DRA. In the first duration DRA, the data voltage VDATA may be written to the pixel [receive data signal under control of the driving signal for refresh frame], see ¶ 0150; The pixel may emit a light in a third duration DRC. In the third duration DRC, the light emitting element EE may emit the light corresponding to the data voltage VDATA, see ¶ 0152); and
in a case of displaying at a second frequency, take N consecutive frames comprising a refresh frame and N-1 hold frames as a group, generate, for each group, a driving signal for the refresh frame in the group and a driving signal for each of the N-1 hold frames in the group (a first frame [refresh frame] may have a frame rate of 240 Hz in FIG. 13.240 Hz may be the normal frequency, see ¶ 0113; Second to fifth frames [N-1 hold frames] may have a frame rate of 60 Hz. 60 Hz [second frequency] may be the low driving frequency less than the normal frequency, see ¶ 0115. Examiner construes the group of frames to be first to fifth frames), and
maintain the received data signal and emit light under control of the driving signal for each of the hold frames, wherein N is a ratio of the first frequency to the second frequency, and N is an integer greater than 1 (The second frame is the writing frame, so that the first bias operation of the first pixel switching element T1 may be operated using the initialization voltage VINT and the high power voltage ELVDD in the initialization operation and the second bias operation of the first pixel switching element T1 may be conducted using the bias voltage VBIAS by the eight pixel switching element T8 in the bias operation [maintain received data signal and emit light under control of the driving signal for the hold frames]. In contrast, the third to fifth frames are the holding frames, so that the initialization operation is omitted and only the second bias operation of the first pixel switching element T1 may be operated using the bias voltage VBIAS by the eight pixel switching element T8 in the bias operation, see ¶ 0127 The bias control signal EB for applying the bias voltage VBIAS to the driving switching element T1 may have the first width WW in the writing frame and the first width WW in the holding frame. The bias voltage VBIAS2 of the holding frame may be set greater than the bias voltage VBIAS1 of the writing frame [ratio of the first frequency to the second frequency is greater than 1], see ¶ 0128);
wherein the driving circuit is further configured to adjust the driving signal for each of 1St to n* hold frames in a next group of N consecutive frames relative to the driving signal for the refresh frame in the next group of N consecutive frames, in response to receiving an instruction of switching from the first frequency to the second frequency, wherein 1 <n<N-1 (the width of the bias control signal EB of the writing frame and the width of the bias control signal EB of the holding frame may be set differently in the variable frequency driving method or the bias voltage of the writing frame and the bias voltage of the holding frame may be set differently in the variable frequency driving method so that the difference of the degree of the bias of the writing frame and the degree of the bias of the holding frame may be removed in the variable frequency driving method [adjust driving signal for each of the hold frames in a next group of N consecutive frames in response to switching instruction], see ¶ 0130).
Park does not expressly disclose apply the generated driving signal for the refresh frame and the generated driving signal for each of the hold frames to the plurality of sub-pixels, so that the plurality of sub-pixels receive the data signal and emit light under control of the driving signal for the refresh frame.
Zhang teaches apply the generated driving signal for the refresh frame and the generated driving signal for each of the hold frames to the plurality of sub-pixels, so that the plurality of sub-pixels receive the data signal and emit light under control of the driving signal for the refresh frame (A frame time of the display panel includes a non-light-emitting period and a light-emitting period, where the non-light-emitting period includes a signal conditioning phase. In the signal conditioning phase, the signal conditioning module 12 is configured to provide a preset signal VE [driving signal] for the driving transistor TO. That is, different signal adjustments are performed on the driving transistor TO in different signal conditioning phases in the non-light-emitting period, which can improve the stability of the driving transistor TO generating the driving current, see ¶ 0030. Figure 3 illustrates providing the driving signal in the non-light-emitting period of both the writing frame, i.e. refresh frame, and the holding frame).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Park with Zhang to teach apply the generated driving signal for the refresh frame and the generated driving signal for each of the hold frames to the plurality of sub-pixels, so that the plurality of sub-pixels receive the data signal and emit light under control of the driving signal for the refresh frame. The suggestion/motivation would have been in order to improve the display effect of the display panel (see ¶ 0030).
As to Claim 2, Park and Zhang depending on Claim 1, Zhang teaches wherein the driving circuit is configured to adjust the driving signal for each of the 1St to nth hold frames by: adjusting the driving signal for each of the 1St to nth hold frames according to a current display brightness value of the display device by a factor, wherein the larger the display brightness value, the greater the factor (the gate potential of the driving transistor T0 is refreshed more frequently, and can perform high-brightness dynamic display. When the display panel operates in a driving mode with a low data refresh frequency, the number of the holding frames in a data refresh period is relatively large. In a data refresh period, the gate potential of the driving transistor T0 remains unchanged for a long time, and can perform low-brightness static display. Therefore, in the embodiment of the present disclosure, the data refresh frequencies of the first pixel circuit and the second pixel circuit are set to be different to each other, and the display panel can have different display effects in different areas, see ¶ 0063; The three parameters of the data refresh frequency, the luminance of the display panel and the frame frequency of the image refresh frame are usually positively correlated. That is, a high data refresh rate normally leads to a high luminance and a high frame frequency of the image refresh frame, see ¶ 0164).
As to Claim 4, Park and Zhang depending on Claim 1, Park teaches
wherein the driving signal comprises at least one of a light emitting control signal, a first initial voltage, a second initial voltage, a power supply voltage and a reference voltage (The power voltage generator 700 may generate a high power voltage ELVDD, a low power voltage ELVSS, an initialization voltage VINT, a reference voltage VREF, see ¶ 0082), wherein the light emitting control signal is configured to control the sub-pixels to emit light (A second emission signal EM2 may be applied to the control electrode of the sixth pixel switching element T6, see ¶ 0086; Fig. 2: EM2), the first initial voltage is configured to initialize a voltage of a first electrode of a light emitting element of the sub-pixels (a seventh pixel switching element T7 including a control electrode, an input electrode receiving the initialization voltage VINT and an output electrode connected to the anode electrode of the light emitting element EE, see ¶ 0085; Fig. 2: VINIT connected to light emitting element via T7), the second initial voltage is configured to initialize a voltage of an input terminal of a driving transistor of the sub-pixels for driving the light emitting element (a third pixel switching element T3 including a control electrode, an input electrode connected to the first node G and an output electrode connected to the third node D, see ¶ 0085; Fig. 2: VINIT connected via node G to driving transistor T1), and the power supply voltage and the reference voltage are configured to supply power to the sub-pixels (a fifth pixel switching element T5 including a control electrode, an input electrode receiving the reference voltage VREF and an output electrode connected to the fourth node A, see ¶ 0085; Fig. 2: VREF connected via node A to ELVDD for supplying power).
As to Claim 5, Park and Zhang depending on Claim 4, Zhang teaches
wherein the driving signal comprises a light emitting control signal, and the driving circuit is configured to adjust the driving signal for each of the 1St to nth hold frames by: adjusting a waveform parameter of the light emitting control signal for each of the 1St to n* hold frames relative to a waveform parameter of the light emitting control signal for the refresh frame, so that the waveform parameter of the light emitting control signal for each of the 1St to n* hold frames is adjusted to be smaller than the waveform parameter of the light emitting control signal for the refresh frame, wherein the waveform parameter comprises at least one of an effective level duration and an amplitude (according to the functions of the data writing frame and the holding frame, and the difference in the signal conditioning phases contained in the data writing frame and the holding frame, the duration of the non-light-emitting period in the data writing frame and the holding frame can be adjusted separately, to optimize the durations of the non-light-emitting periods in the data writing frame and the holding frame, see ¶ 0115).
As to Claim 12, Park and Zhang depending on Claim 4, Zhang teaches
wherein the driving signal comprises at least one of the power supply voltage and the reference voltage, and the driving circuit is configured to adjust the driving signal for each of the 1St to nth hold frames by: adjusting at least one of the power supply voltage and the reference voltage for each of the 1St to n* hold frames, so that an absolute difference between the power supply voltage and the reference voltage for each of the 1st to n* hold frames is less than an absolute difference between the power supply voltage and the reference voltage for the refresh frame (Due to the difference between the degree of the bias of the writing frame and the degree of the bias of the holding frame, the luminance of the image in the writing frame and the luminance of the image in the holding frame may be different from each other. Thus, the display quality of the display panel 100 may be deteriorated due to the difference of the luminances, see ¶ 0109).
As to Claim 17, Park and Zhang depending on Claim 1, Park teaches wherein the driving circuit comprises: a gate driving circuit connected to the plurality of sub-pixels, wherein the gate driving circuit is configured to generate a gate driving signal and a light emitting control signal (The driving controller 200 generates the first control signal CONT1 for controlling an operation of the gate driver 300 based on the input control signal CONT, and outputs the first control signal CONT1 to the gate driver 300, see ¶ 0068; The driving controller 200 generates the fourth control signal CONT4 for controlling an operation of the emission driver 600 based on the input control signal CONT, and outputs the fourth control signal CONT4 to the emission driver 600, see ¶ 0072); and a driving control circuit connected to the gate driving circuit and the plurality of sub-pixels, wherein the driving control circuit is configured to control the gate driving circuit to generate the gate driving signal and the light emitting control signal, apply the data signal to the plurality of sub-pixels, and adjust the light emitting control signal (The driving controller 200 generates a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, a fourth control signal CONT4 and a data signal DATA based on the input image data IMG and the input control signal CONT, see ¶ 0067; The driving controller 200 generates the first control signal CONT1 for controlling an operation of the gate driver 300 based on the input control signal CONT, and outputs the first control signal CONT1 to the gate driver 300, see ¶ 0068; The driving controller 200 generates the fourth control signal CONT4 for controlling an operation of the emission driver 600 based on the input control signal CONT, and outputs the fourth control signal CONT4 to the emission driver 600, see ¶ 0072); wherein the driving control circuit is further configured to provide a first initial voltage and/or a second initial voltage, and adjust the first initial voltage and/or the second initial voltage (The power voltage generator 700 may generate a high power voltage ELVDD, a low power voltage ELVSS, an initialization voltage VINT, a reference voltage VREF and a bias voltage VBIAS. The power voltage generator 700 may output the high power voltage ELVDD, the low power voltage ELVSS, the initialization voltage VINT, the reference voltage VREF and the bias voltage VBIAS to the pixels of the display panel 100, see ¶ 0082); and wherein the driving circuit further comprises a power supply circuit for providing a power supply voltage and a reference voltage to the sub-pixel, and the driving control circuit is further configured to control the power supply circuit to adjust at least one of the power supply voltage and the reference voltage (In the third duration DR3 and the fifth duration DR5, the fourth node A is in a state in which the reference voltage VREF is written. In the third duration DR3 and the fifth duration DR5, the initialization voltage VINT is applied to the first node G through the fourth pixel switching element T4. In the third duration DR3 and the fifth duration DR5, the high power voltage ELVDD is applied to the second node S through the ninth pixel switching element T9. The initialization voltage VINT is applied to the first node G in the third duration DR3 and the fifth duration DR5 so that the third duration DR3 and the fifth duration DR5 may be respectively referred to a second initialization operation and a third initialization operation, see ¶ 0097).
As to Claim 20, Park and Zhang depending on Claim 1, Park teaches wherein the sub-pixel comprises a pixel driving circuit and a light emitting element (Each pixel includes a driving switching element T1 and a light emitting element EE, see ¶ 0084), and the pixel driving circuit comprises: a driving sub-circuit comprising a control terminal, an input terminal and an output terminal (Each pixel includes a driving switching element T1, see ¶ 0084; The pixel may include a first pixel switching element T1 including a control electrode connected to a first node G, an input electrode connected to a second node S and an output electrode connected to a third node D, see ¶ 0085);
a storage sub-circuit connected between the control terminal of the driving sub- circuit and a power supply signal terminal for receiving a power supply voltage (a first capacitor CST including a first electrode receiving the high power voltage ELVDD and a second electrode connected to the fourth node A, see ¶ 0085);
an input sub-circuit connected to the input terminal of the driving sub-circuit, wherein the input sub-circuit is configured to provide a data signal to the input terminal of the driving sub-circuit under control of a first gate driving signal (a second pixel switching element T2 [input sub-circuit] including a control electrode, an input electrode receiving a data voltage VDATA and an output electrode connected to a fourth node A, see ¶ 0085; Figure 2 illustrates transistor T2 controlled by gate driving signal GW and providing a VDATA signal to the input terminal of transistor T1 via transistor T3 and node D);
an input control sub-circuit connected between the output terminal of the driving sub-circuit and the control terminal of the driving sub-circuit, wherein the input control sub-circuit is configured to electrically connect the output terminal of the driving sub-circuit to the control terminal of the driving sub-circuit under control of a second gate driving signal (a third pixel switching element T3 including a control electrode, an input electrode connected to the first node G and an output electrode connected to the third node D, see ¶ 0085; Figure 2 illustrates transistor T3 controlled by gate driving signal GC connecting the control terminal of transistor T1 to the output terminal of transistor T1);
a light emitting control sub-circuit connected between the driving sub-circuit and the power supply signal terminal, and between the driving sub-circuit and the light emitting element, wherein the light emitting control sub-circuit is configured to conduct a path from the power supply signal terminal to the light emitting element through the driving sub-circuit under control of the light emitting control signal (a sixth pixel switching element T6 including a control electrode, an input electrode connected to the third node D and an output electrode connected to an anode electrode of the light emitting element EE, see ¶ 0085; Figure 2 illustrates transistor T6 connected between the transistor T1 and power voltage ELVSS and between the transistor T1 and the light emitting element EE); and
an initialization sub-circuit connected to the input terminal of the driving sub-circuit, the output terminal of the driving sub-circuit and a first electrode of the light emitting element, wherein the initialization sub-circuit is configured to initialize a voltage at each of the input terminal of the driving sub-circuit, the output terminal of the driving sub-circuit and the first electrode of the light emitting element, wherein a second electrode of the light emitting element is connected to a reference signal terminal for receiving a reference voltage (a seventh pixel switching element T7 including a control electrode, an input electrode receiving the initialization voltage VINT and an output electrode connected to the anode electrode of the light emitting element EE, see ¶ 0085; Figure 2 illustrates transistor T7 connected to the input terminal of the transistor T1 and a first electrode of the light emitting element EE, connected to VINT at the input terminal of the driving transistor, output terminal of the driving transistor T1 and first electrode of the light emitting element EE; light emitting element EE receives VREF from transistor T7 via nodes A, G).
As to Claim 26, Park teaches a method of driving a display device, comprising: in a case of displaying at a first frequency, taking each frame as a refresh frame, generating a driving signal for the refresh frame (a first frame may have a frame rate of 240 Hz in FIG. 13. 240 Hz may be the normal frequency. When the driving frequency is the normal frequency, the display panel 100 may only have the writing frames [refresh frames], see ¶ 0113), and
applying the generated driving signal for the refresh frame and a data signal to a plurality of sub- pixels of the display device, so that the plurality of sub-pixels receive the data signal and emit light, under control of the driving signal for the refresh frame (The first frame is the writing frame, so that the first bias operation of the first pixel switching element T1 may be operated using the initialization voltage VINT and the high power voltage ELVDD, see ¶ 0114; the pixel may operate an initialization operation and a data writing operation in a first duration DRA. In the first duration DRA, the data voltage VDATA may be written to the pixel [receive data signal under control of the driving signal for refresh frame], see ¶ 0150; The pixel may emit a light in a third duration DRC. In the third duration DRC, the light emitting element EE may emit the light corresponding to the data voltage VDATA, see ¶ 0152); and
in a case of displaying at a second frequency, taking N consecutive frames comprising a refresh frame and N-1 hold frames as a group, generating for each group a driving signal for the refresh frame in the group and a driving signal for each of N-1 hold frames in the group (a first frame [refresh frame] may have a frame rate of 240 Hz in FIG. 13.240 Hz may be the normal frequency, see ¶ 0113; Second to fifth frames [N-1 hold frames] may have a frame rate of 60 Hz. 60 Hz [second frequency] may be the low driving frequency less than the normal frequency, see ¶ 0115. Examiner construes the group of frames to be first to fifth frames), and
maintain the received data signal and emit light under control of the driving signal for each of the hold frames, wherein N is a ratio of the first frequency to the second frequency, and N is an integer greater than 1 (The second frame is the writing frame, so that the first bias operation of the first pixel switching element T1 may be operated using the initialization voltage VINT and the high power voltage ELVDD in the initialization operation and the second bias operation of the first pixel switching element T1 may be conducted using the bias voltage VBIAS by the eight pixel switching element T8 in the bias operation [maintain received data signal and emit light under control of the driving signal for the hold frames]. In contrast, the third to fifth frames are the holding frames, so that the initialization operation is omitted and only the second bias operation of the first pixel switching element T1 may be operated using the bias voltage VBIAS by the eight pixel switching element T8 in the bias operation, see ¶ 0127 The bias control signal EB for applying the bias voltage VBIAS to the driving switching element T1 may have the first width WW in the writing frame and the first width WW in the holding frame. The bias voltage VBIAS2 of the holding frame may be set greater than the bias voltage VBIAS1 of the writing frame [ratio of the first frequency to the second frequency is greater than 1], see ¶ 0128);
wherein the method further comprises: adjusting the driving signal for each of 1St to n* hold frames in a next group of N consecutive frames relative to the driving signal for the refresh frame in the next group of N consecutive frames, in response to receiving an instruction of switching from the first frequency to the second frequency, wherein 1 <n<N-1 (the width of the bias control signal EB of the writing frame and the width of the bias control signal EB of the holding frame may be set differently in the variable frequency driving method or the bias voltage of the writing frame and the bias voltage of the holding frame may be set differently in the variable frequency driving method so that the difference of the degree of the bias of the writing frame and the degree of the bias of the holding frame may be removed in the variable frequency driving method [adjust driving signal for each of the hold frames in a next group of N consecutive frames in response to switching instruction], see ¶ 0130).
Park does not expressly disclose applying the generated driving signal for the refresh frame and the generated driving signal for each of the hold frames to the plurality of sub-pixels, so that the plurality of sub- pixels receive the data signal and emit light under control of the driving signal for the refresh frame.
Zhang teaches applying the generated driving signal for the refresh frame and the generated driving signal for each of the hold frames to the plurality of sub-pixels, so that the plurality of sub- pixels receive the data signal and emit light under control of the driving signal for the refresh frame (A frame time of the display panel includes a non-light-emitting period and a light-emitting period, where the non-light-emitting period includes a signal conditioning phase. In the signal conditioning phase, the signal conditioning module 12 is configured to provide a preset signal VE [driving signal] for the driving transistor TO. That is, different signal adjustments are performed on the driving transistor TO in different signal conditioning phases in the non-light-emitting period, which can improve the stability of the driving transistor TO generating the driving current, see ¶ 0030. Figure 3 illustrates providing the driving signal in the non-light-emitting period of both the writing frame, i.e. refresh frame, and the holding frame).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Park with Zhang to teach applying the generated driving signal for the refresh frame and the generated driving signal for each of the hold frames to the plurality of sub-pixels, so that the plurality of sub- pixels receive the data signal and emit light under control of the driving signal for the refresh frame. The suggestion/motivation would have been in order to improve the display effect of the display panel (see ¶ 0030).
Allowable Subject Matter
7. Claims 3, 6-11, 13, 15, 21, 27, 29 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EBONI N GILES whose telephone number is (571)270-7453. The examiner can normally be reached Monday - Friday 9 am - 6 pm EST.
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/EBONI N GILES/Examiner, Art Unit 2622
/PATRICK N EDOUARD/Supervisory Patent Examiner, Art Unit 2622
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