DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an
application filed in China on 06/13/2023. It is noted, however, that applicant has not filed a certified copy of the CHINA 202310701919.2 application as required by 37 CFR 1.55.
Claim Objections
3. Claims 1-18 and 40-41 are objected to because of the following informalities:
In lines 1-2 of claim 1: “… a node control sub-circuit, an output sub-circuit, and a pull-down sub-circuit; wherein ..." should be changed to --... a node control sub-circuit; an output sub-circuit; and a pull-down sub-circuit, wherein: ...--;
In line 5 of claim 1: “… a the second node ..." should be changed to --... a second node ...--;
In line 17 of claim 1: “… the second power supply terminal; ..." should be changed to --... the second power supply terminal; and ...--;
In lines 1-2 of claim 2: “… wherein the pull-down sub-circuit comprises: an eleventh transistor; ..." should be changed to --... wherein: the pull-down sub-circuit comprises: an eleventh transistor; and ...--;
In line 1-2 of claim 4: “… wherein the node control sub-circuit comprises: a first transistor, a second transistor, a third transistor, a sixth transistor, ..." should be changed to --... wherein: the node control sub-circuit comprises: a first transistor; a second transistor; a third transistor; a sixth transistor; ...--;
In line 16 of claim 4: “… a fourth node; ..." should be changed to --... a fourth node; and ...--;
In lines 1-2 of claim 5: “… wherein the output sub-circuit comprises: a fourth transistor, a fifth transistor, ..." should be changed to --... wherein: the output sub-circuit comprises: a fourth transistor; a fifth transistor; ...--;
In line 9 of claim 5: “… the first signal output terminal; ..." should be changed to --... the first signal output terminal; and ...--;
In lines 1-2 of claim 6: “… wherein the pull-down sub-circuit comprises: an eleventh transistor; ..." should be changed to --... wherein: the pull-down sub-circuit comprises: an eleventh transistor; and ...--;
In line 4 of claim 7: “… the first power supply terminal; ..." should be changed to --... the first power supply terminal; and ...--;
In lines 1-2 of claim 9: “… wherein the output sub-circuit comprises: a fourth transistor, a fifth transistor, an eighth transistor, a ninth transistor, ..." should be changed to --... wherein: the output sub-circuit comprises: a fourth transistor; a fifth transistor; an eighth transistor; a ninth transistor; ...--;
In line 16 of claim 9: “… the second signal output terminal; ..." should be changed to --... the second signal output terminal; and ...--;
In line 1 of claim 10: “… wherein ..." should be changed to --... wherein: ...--;
In line 3 of claim 10: “… the twelfth transistor; ..." should be changed to --... the twelfth transistor; and ...--;
In lines 1-3 of claim 11: “… wherein the output sub-circuit further comprises: at least one of a first capacitor, a second capacitor, a third capacitor, ..." should be changed to --... wherein: the output sub-circuit further comprises: at least one of a first capacitor; a second capacitor; a third capacitor; ...--;
In lines 1-2 of claim 13: “… an output control sub-circuit; ..." should be changed to --... an output control sub-circuit, ...--;
In line 3 of claim 13: “… the output control sub-circuit ..." should be changed to --... wherein the output control sub-circuit ...--;
In lines 1-2 of claim 14: “… wherein the output control sub-circuit comprises: a fifth capacitor; ..." should be changed to --... wherein: the output control sub-circuit comprises: a fifth capacitor; and ...--;
In line 2 of claim 16: “… the base substrate ..." should be changed to --... wherein the base substrate ...--;
In line 5 of claim 16: “…respectively; ..." should be changed to --... wherein respectively, ...--;
In line 6 of claim 16: “… the gate driving circuit ..." should be changed to --... wherein the gate driving circuit ...--;
In line 7 of claim 16: “… wherein ..." should be changed to --... and wherein ...--;
In line 9 of claim 16: “… N is a total number ..." should be changed to --... and N is a total number ...--; and
In lines 1-2 of claim 17: “… a first signal output terminal ..." should be changed to --... the first signal output terminal ...--.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
4. .The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 1-5, 7, 15-18 and 40-41 are rejected under 35 U.S.C. 103 as being unpatentable Zheng (U.S. Pub. No. US 2021/0358367 A1) in view of Wang (U.S. Pub. No. US 2020/0211435 A1).
As to claim 1, Zheng (Figs. 1-8) teaches a shift register unit (a shift register; Figs. 1-2) comprising:
a node control sub-circuit (transistors T5-T6, T8, T11 and T12), an output sub-circuit (transistors T1-T4, T7, T9 and T10 and capacitors C1-C3), and a pull-down sub-circuit (transistors T5 and T6) (Fig. 2); wherein
the node control sub-circuit (the transistors T5-T6, T8, T11 and T12) is electrically connected to a signal input terminal (an input voltage terminal STV), a first clock signal terminal (a first clock signal terminal CK), a second clock signal terminal (a second clock signal terminal CB), a first power supply terminal (a first power terminal VGH), a second power supply terminal (a second power terminal VGL), a first node (a fourth node N4), a the second node (a third node N3), respectively, and is configured to provide a signal at the signal input terminal (the input voltage terminal STV) or the first power supply terminal (the first power terminal VGH) to the first node (the fourth node N4) and provide a signal at the second power supply terminal (the second power terminal VGL) or the first clock signal terminal (the first clock signal terminal CK) to the second node (the third node N3) under control of signals at the first clock signal terminal (the first clock signal terminal CK) and the second clock signal terminal (the second clock signal terminal CB) (Fig. 2);
the output sub-circuit (the transistors T1-T4, T7, T9, T10 and capacitors C1-C3) is electrically connected to the second clock signal terminal (the second clock signal terminal CB), the first power supply terminal (the first power terminal VGH), the second power supply terminal (the second power terminal VGL), a first signal output terminal (an intermediate output terminal GOUT), the first node (the fourth node N4), and the second node (the third node N3), respectively, and is configured to provide a signal at the first power supply terminal (the first power terminal VGH) or the second clock signal terminal (the second clock signal terminal CB) to the first signal output terminal (the intermediate output terminal GOUT) under control of signals at the first node (the fourth node N4), the second node (the third node N3), and the second power supply terminal (the second power terminal VGL) (Fig. 2).
Zheng does not expressly teach the pull-down sub-circuit is electrically connected to the first node and a third power supply terminal, respectively, and is configured to provide a signal at the third power supply terminal to the first node; an absolute value of a voltage value of the signal at the third power supply terminal is less than an absolute value of a voltage value of the signal at the second power supply terminal.
Wang (Figs. 1-11) teaches
the pull-down sub-circuit (the first pull-down circuit 30) is electrically connected to the first node (the third node P3) and a third power supply terminal (a second DC power supply terminal VGL), respectively, and is configured to provide a signal at the third power supply terminal (the second DC power supply terminal VGL) to the first node (the first node P1) (Fig. 3);
an absolute value of a voltage value (a voltage of the third node P3) of the signal at the third power supply terminal (the second DC power supply terminal VGL) is less (since the voltage at the second DC power supply terminal VGL is provided to the first node P1, the voltage at the first node P1 is less than the voltage at the first clock signal terminal CLK1 in the output stage t2) than an absolute value of a voltage value (a voltage corresponding to V2 in the application) of the signal at the second power supply terminal (the first clock signal terminal CLK1) (Figs. 3 and 9).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have added an additional pull-down circuit as taught by Wang to a shift register of Zheng because the additional pull-down circuit provides noise reduction for the shift register.
As to claim 2, Wang teaches wherein
the pull-down sub-circuit (the first pull-down circuit 30) comprises: an eleventh transistor (a first pull-down transistor L1) (Fig. 3);
a first electrode of the eleventh transistor (the first pull-down transistor L1) is electrically connected to the third power supply terminal (the second DC power supply terminal VGL), and a second electrode of the eleventh transistor (the first pull-down transistor L1) is electrically connected to the first node (the first node P1) (Fig. 3).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have added an additional pull-down circuit as taught by Wang to a shift register of Zheng because the additional pull-down circuit provides noise reduction for the shift register.
As to claim 3, Wang teaches
wherein a control electrode of the eleventh transistor (the first pull-down transistor L1) is electrically connected to the first node (the first node P1) (Fig. 3).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have added an additional pull-down circuit as taught by Wang to a shift register of Zheng because the additional pull-down circuit provides noise reduction for the shift register.
As to claim 4, Zheng teaches wherein
the node control sub-circuit comprises: a first transistor (a transistor T12), a second transistor (a transistor T8), a third transistor (a transistor T11), a sixth transistor (a transistor T5), and a seventh transistor (a transistor T6) (Fig. 2);
a control electrode of the first transistor (the transistor T12) is connected to the first clock signal terminal (the first clock signal terminal CK), a first electrode of the first transistor (the transistor T12) is electrically connected to the signal input terminal (the input voltage terminal STV), and a second electrode of the first transistor (the transistor T12) is electrically connected to the first node (the fourth node N4) (Fig. 2);
a control electrode of the second transistor (the transistor T8) is electrically connected to the first node (the fourth node N4), a first electrode of the second transistor (the transistor T8) is connected to the first clock signal terminal (the first clock signal terminal CK), and the second electrode of the second transistor (the transistor T8) is electrically connected to the second node (the third node N3) (Fig. 2);
a control electrode of the third transistor (the transistor T11) is electrically connected to the first clock signal terminal (the first clock signal terminal CK), a first electrode of the third transistor (the transistor T11) is connected to the second power supply terminal (the second power terminal VGL), and a second electrode of the third transistor (the transistor T11) is electrically connected to the second node (the third node N3) (Fig. 2);
a control electrode of the sixth transistor (the transistor T5) is electrically connected to the second node (the third node N3), a first electrode of the sixth transistor (the transistor T5) is connected to the first power supply terminal (the first power terminal VGH), and a second electrode of the sixth transistor (the transistor T5) is electrically connected to a fourth node (a node between the transistor T5 and the transistor T6) (Fig. 2);
a control electrode of a seventh transistor (the transistor T6) is electrically connected to the second clock signal terminal (the second clock signal terminal CB), a first electrode of the seventh transistor (the transistor T6) is connected to the fourth node (the node between the transistor T5 and the transistor T6), and a second electrode of the seventh transistor (the transistor T6) is electrically connected to the first node (the fourth node N4) (Fig. 2).
As to claim 5, Zheng teaches wherein
the output sub-circuit comprises: a fourth transistor (a transistor T10), a fifth transistor (a transistor T9), and an eighth transistor (a transistor T7) (Fig. 2);
a control electrode of the fourth transistor (the transistor T10) is electrically connected to the second node (the third node N3), a first electrode of the fourth transistor (the transistor T10) is connected to the first power supply terminal (the first power terminal VGH), and a second electrode of the fourth transistor (the transistor T10) is electrically connected to the first signal output terminal (the intermediate output terminal GOUT) (Fig. 2);
a control electrode of the fifth transistor (the transistor T9) is electrically connected to a third node (a second node N2), a first electrode of the fifth transistor (the transistor T9) is connected to the second clock signal terminal (the second clock signal terminal CB), and a second electrode of the fifth transistor (the transistor T9) is electrically connected to the first signal output terminal (the intermediate output terminal GOUT) (Fig. 2);
a control electrode of the eighth transistor (the transistor T7) is electrically connected to the second power supply terminal (the second power terminal VGL), a first electrode of the eighth transistor (the transistor T7) is electrically connected to the first node (the fourth node N4), and a second electrode of the eighth transistor (the transistor T7) is electrically connected to the third node (the second node N2) (Fig. 2).
As to claim 7, Zheng teaches wherein
the output sub-circuit (the transistors T7, T9 and T10 and capacitors C3 and C2) further comprises: at least one of a first capacitor (a capacitor C3) and a second capacitor (a capacitor C2) (Fig. 2);
a first plate of the first capacitor (the capacitor C3) is electrically connected to the second node (the third node N3), and a second plate of the first capacitor (the capacitor C3) is electrically connected to the first power supply terminal (the first power terminal VGH) (Fig. 2);
a first plate of the second capacitor (the capacitor C2) is electrically connected to the third node (the second node N2), and a second plate of the second capacitor (the capacitor C2) is electrically connected to the first signal output terminal (the intermediate output terminal GOUT) (Fig. 2).
As to claim 15, Zheng teaches
wherein the signal at the first clock signal terminal (the first clock signal terminal CK) and the signal at the second clock signal terminal (the second clock signal terminal CB) are not simultaneously effective level signals (the signals are pulses, the levels of which are reverse each other; Fig. 3).
As to claim 16, Zheng teaches a display substrate comprising: a base substrate (a base substrate) and sub-pixels (a plurality of pixel units 4) (Fig. 7), a gate line (a gate line 2) and a gate driving circuit (a gate drive circuit 1) disposed on the base substrate (the base substrate) (Fig. 7),
the base substrate (the base substrate) is provided with a display region (a display region with the pixel units 4) and a non-display region (a non-display region with the gate drive circuit 1), the gate driving circuit (the gate drive circuit 1) is located in the non-display region (Fig. 7), the sub-pixels (the pixel units 4) and the gate line (the gate line 2) are located in the display region (Fig. 7), and the gate line (the gate line 2) is electrically connected to the sub-pixels (the pixel units 4) and the gate driving circuit (the gate drive circuit 1), respectively (Fig. 7);
the gate driving circuit (the gate drive circuit 1) comprises a plurality of cascaded shift register units (shift registers SR1 SR2, SR3, …, SRn) as claimed in claim 1 (Figs. 5 and 7),
wherein a first signal output terminal (GOUT) of an i-th stage shift register unit (the shift register SRi) is connected to a signal input terminal of an (i+1)-st stage shift register unit (the shift register SRi+1), 1≤ i <N, N is a total number of stages of the shift register units (Figs. 5 and 7).
As to claim 17, Zheng teaches
wherein a first signal output terminal (EOUT) of a shift register unit (a shift register SRi) is electrically connected to the gate line (the gate line Gi) (Figs. 5 and 7).
As to claim 18, Zheng teaches further comprising:
an initial signal line (a line from STV0), a first clock signal line (a line CK0), a second clock signal line (a line CK1), a first power supply line (a line from VGH0), a second power supply line (a line from VGL0), and a third power supply line (a line from VGL10) disposed on the base substrate (the base substrate) and located in the non-display region (the non-display region) (Figs. 5 and 7);
any one of the initial signal line (the line from STV0), the first clock signal line (the line CK0), the second clock signal line (the line CK1), the first power supply line (the line from VGH0), the second power supply line (the line from VGL0), and the third power supply line (the line from VGL10) extends in a first direction (a vertical direction), and the gate line (the gate line 2) extends in a second direction (a horizontal direction), and the first direction (the vertical direction) intersects the second direction (the horizontal direction) (Figs. 5 and 7).
As to claim 40, Zheng teaches a display apparatus (a display device; a title), comprising:
the display substrate (the display substrate) of claim 16 (Figs. 5 and 7).
As to claim 41, Zheng teaches a method for driving a shift register unit (a shift register SRi; Fig. 5), configured to drive the shift register unit according to claim 1, wherein the method comprises:
providing a signal at the signal input terminal (the input voltage terminal STV) or the first power supply terminal to the first node (the fourth node N4) and providing a signal at the second power supply terminal (the second power terminal VGL) or the first clock signal terminal (the first clock signal terminal CK) to the second node (the third node N3) under control of signals at the first clock signal terminal (the first clock signal terminal CK) and the second clock signal terminal (the second clock signal terminal CB) by the node control sub-circuit (the transistors T5-T6, T8, T11 and T12) (Fig. 2); and
providing a signal at the first power supply terminal (the first power terminal VGH) or the second clock signal terminal (the second clock signal terminal CB) to the first signal output terminal (the intermediate output terminal GOUT) under control of signals at the first node (the fourth node N4) and the second node (the third node N3) by the output sub-circuit (the transistors T1-T4, T7, T9, T10 and capacitors C1-C3).
Zheng does not expressly teach providing a signal at the third power supply terminal to the first node by the pull-down sub-circuit.
Wang teaches
providing a signal at the third power supply terminal (a second DC power supply terminal VGL) to the first node (the first node P1) by the pull-down sub-circuit (the first pull-down circuit 30) (Fig. 3).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have added an additional pull-down circuit as taught by Wang to a method for driving a shift register of Zheng because the additional pull-down circuit provides noise reduction for the shift register.
Allowable Subject Matter
6. Claims 6 and 8-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record, Zheng and Wang, either individually or in combination, does not teach a limitation “wherein the pull-down sub-circuit comprises: an eleventh transistor; a control electrode of the eleventh transistor is electrically connected to the third node” of claim 6, a limitation “wherein the output sub-circuit is further electrically connected to a third clock signal terminal and a second signal output terminal, respectively, is configured to provide signals at the second power supply terminal or the third clock signal terminal to the second signal output terminal under control of signals at the first node and the second node” of claim 8, and a limitation “further comprising: an output control sub-circuit; the output control sub-circuit is electrically connected to the first power supply terminal and the first signal output terminal, respectively, and is configured to store a voltage difference between signals at the first signal output terminal and the first power supply terminal” of claim 13 in combination with other limitations of the base claim and any intervening claim(s)..
Conclusion
7. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Liang (U.S. Pub. No. US 2021/0209994 A1) is cited to teach a shift-register circuit which includes a pull-up sub-circuit coupled to a pull-up node, a first clock port, and an output port, wherein the pull-up sub-circuit is configured to pass a first clock signal from the first clock port to the output port when the pull-up node is set to a turn-on voltage.
Feng (U.S. Pub. No. US 2021/0201806 A1) is cited to teach a shift register unit which includes a first input circuit, a second input circuit, an output circuit, and a compensation circuit.
Inquiry
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kwang-Su Yang whose telephone number is (571)270-7307. The examiner can normally be reached on Mon-Fri during 9:00am-6:00pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen, can be reached on (571)272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KWANG-SU YANG/
Primary Examiner, Art Unit 2623
Prosecution Insights