DETAILED ACTION
This action is in response to the Application filed on 01/16/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 04/15/2025 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d).
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim(s) 41 and 45 is/are objected to because of the following informalities:
Claim 41, lines 1 - 2 recite “the at least one field-effect transistor” lacks antecedent basis.
Claim 45, line 20 recites “a DC input voltage to a DC output voltage”. It appears that it should be “the DC input voltage to the DC output voltage”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 30 and 40 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 30 and claim 40, the phrase "preferably" renders the claim indefinite because it is unclear whether the limitations following the phrase are part of the claimed invention. See MPEP § 2173.05(d).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 26 – 29, 31 – 32, 36 – 38 and 44 - 45 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Pub. No. 2021/0408891; (hereinafter Yao) in view of US Pub. No. 2020/0006292; (hereinafter Choi).
Regarding claim 26, Yao [e.g. Fig. 5 applied to Fig. 2; paragraph 023 recites “Referring now to FIG. 5, shown is a schematic block diagram of a fifth example voltage converter, in accordance with embodiments of the present invention. This particular example switch and capacitor network”] discloses a switched-capacitor DC-DC converter comprising: at least one input terminal [e.g. terminal having Vin]; at least one output terminal [e.g. terminal having Vout]; a plurality of power switches [e.g. Q1 – Q10] and a plurality of flying capacitors configured to convert a DC input voltage [e.g. Vin] from the at least one input terminal to a DC output voltage [e.g. Vout] to the at least one output terminal by a switched-capacitor power conversion [e.g. Fig. 5], wherein at least one of the plurality of power switches is a segmented switch [e.g. Fig. 5; Q2 – Q6], comprising at least one internal switch-segment disposed on a first semiconductor die of a first semiconductor manufacturing technology [e.g. paragraph 023 recites “switch and capacitor network can include a plurality of the second-type power transistors (e.g., Q2-Q6) connected in series] and at least one external switch- segment disposed on a second semiconductor die of a second semiconductor manufacturing technology [e.g. paragraph 019 recites “first-type power transistor Q1 can be integrated into the first die”] different to the first semiconductor manufacturing technology [e.g. paragraph 019 recites “first-type power transistor Q1 can be integrated into the first die, and one or more second-type power transistors can be integrated into the second die. For example, first-type power transistor Q1 is a GaN power transistor”].
Yao fails to disclose a plurality of gate drivers configured to drive the plurality of power switches.
Choi [e.g. Figs. 1 - 2] teaches a plurality of gate drivers [e.g. 122a1-122a3 and 122b1-122b3] configured to drive the plurality of power switches [e.g. 106a1-106a3 and 106b1-106b3].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Yao by a plurality of gate drivers configured to drive the plurality of power switches as taught by Choi in order of being able to respectively drive or control switching of the switches, paragraph 038.
Regarding claim 27, Yao [e.g. Fig. 5 applied to Fig. 2] discloses wherein the second semiconductor die is of a technology for implementing at least one external GaN FET and/or at least one external vertical power MOSFET [e.g. paragraph 019 recites “first-type power transistor Q1 can be integrated into the first die, and one or more second-type power transistors can be integrated into the second die. For example, first-type power transistor Q1 is a GaN power transistor”].
Regarding claim 28, Yao [e.g. Fig. 5 applied to Fig. 2] discloses wherein the at least one external switch-segment comprises at least one external GaN FET and/or at least one external vertical power MOSFET [e.g. paragraph 019 recites “first-type power transistor Q1 can be integrated into the first die, and one or more second-type power transistors can be integrated into the second die. For example, first-type power transistor Q1 is a GaN power transistor”].
Regarding claim 29, Yao [e.g. Fig. 5 applied to Fig. 2] discloses wherein the second semiconductor die comprises at least one GaN-on-silicon-based external switch-segment [e.g. paragraph 019 recites “first-type power transistor Q1 can be integrated into the first die, and one or more second-type power transistors can be integrated into the second die. For example, first-type power transistor Q1 is a GaN power transistor”].
Regarding claim 31, Yao [e.g. Fig. 5 applied to Fig. 2] discloses wherein the second semiconductor die is of a direct bandgap semiconductor technology, such as a Gallium nitride technology [e.g. paragraph 019 recites “first-type power transistor Q1 can be integrated into the first die, and one or more second-type power transistors can be integrated into the second die. For example, first-type power transistor Q1 is a GaN power transistor”].
Regarding claim 32, Yao [e.g. Fig. 5 applied to Fig. 2] discloses wherein the second semiconductor die is adapted for power transistor implementation [e.g. paragraph 019 recites “first-type power transistor Q1 can be integrated into the first die, and one or more second-type power transistors can be integrated into the second die. For example, first-type power transistor Q1 is a GaN power transistor”] or wherein the first semiconductor die is a silicon-based semiconductor die .
Regarding claim 36, Yao fails to disclose wherein the at least one internal switch-segment and the at least one external switch-segment are independently controlled by the plurality of gate drivers.
Choi [e.g. Figs. 1 - 2] teaches wherein the at least one internal switch-segment and the at least one external switch-segment are independently controlled by the plurality of gate drivers [e.g. 122a1-122a3 and 122b1-122b3 and 106a1-106a3 and 106b1-106b3].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Yao by wherein the at least one internal switch-segment and the at least one external switch-segment are independently controlled by the plurality of gate drivers as taught by Choi in order of being able to respectively drive or control switching of the switches, paragraph 038.
Regarding claim 37, Yao [e.g. Fig. 5 applied to Fig. 2] discloses wherein the at least one internal switch-segment and/or the at least one external switch-segment are connected in parallel [e.g. Q5 – Q10].
Regarding claim 38, Yao discloses in paragraph 019 “The control circuit can be integrated into the first die or the second die, or the control circuit can also be integrated into a third die.”
Yao fails to disclose wherein the plurality of gate drivers are disposed on the first semiconductor die.
Choi teaches wherein the plurality of gate drivers are disposed on the first semiconductor die [e.g. paragraph 083 recites “For example, the logic die may be based on silicon technology, e.g., may include CMOS (Complementary metal-oxide-semiconductor) circuitries. Merely as an example, a processor or an application circuitry may be within the logic die.”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Yao by wherein the plurality of gate drivers are disposed on the first semiconductor die as taught by Choi in order of being able to optimize the circuit arrangement, paragraphs 083 - 084.
Regarding claim 44, Yao [e.g. Fig. 5 applied to Fig. 2; paragraph 023 recites “Referring now to FIG. 5, shown is a schematic block diagram of a fifth example voltage converter, in accordance with embodiments of the present invention. This particular example switch and capacitor network”] discloses programmable switch array for a switched-capacitor DC-DC converter comprising: at least one input terminal [e.g. terminal having Vin]; at least one output terminal [e.g. terminal having Vout]; a plurality of power switches [e.g. Q1 – Q10] and a plurality of flying capacitor terminals connectable to a plurality of flying capacitors configured to convert a DC input voltage [e.g. Vin] from the at least one input terminal to a DC output voltage [e.g. Vout] to the at least one output terminal by a switched-capacitor power conversion [e.g. Fig. 5], wherein at least one of the plurality of power switches is a segmented switch [e.g. Fig. 5; Q2 – Q6], comprising at least one internal switch-segment disposed on a first semiconductor die of a first semiconductor manufacturing technology [e.g. paragraph 023 recites “switch and capacitor network can include a plurality of the second-type power transistors (e.g., Q2-Q6) connected in series], and at least one switch-segment terminal connectable to at least one external switch- segment disposed on a second semiconductor die of a second semiconductor manufacturing technology [e.g. paragraph 019 recites “first-type power transistor Q1 can be integrated into the first die”] different to the first semiconductor manufacturing technology [e.g. paragraph 019 recites “first-type power transistor Q1 can be integrated into the first die, and one or more second-type power transistors can be integrated into the second die. For example, first-type power transistor Q1 is a GaN power transistor”].
Yao fails to disclose a plurality of gate drivers configured to drive the plurality of power switches.
Choi [e.g. Figs. 1 - 2] teaches a plurality of gate drivers [e.g. 122a1-122a3 and 122b1-122b3] configured to drive the plurality of power switches [e.g. 106a1-106a3 and 106b1-106b3].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Yao by a plurality of gate drivers configured to drive the plurality of power switches as taught by Choi in order of being able to respectively drive or control switching of the switches, paragraph 038.
Regarding claim 45, Yao [e.g. Fig. 5 applied to Fig. 2; paragraph 023 recites “Referring now to FIG. 5, shown is a schematic block diagram of a fifth example voltage converter, in accordance with embodiments of the present invention. This particular example switch and capacitor network”] discloses a method for performing a switched-capacitor DC-DC conversion comprising the following steps: providing a switched-capacitor DC-DC converter comprising: at least one input terminal [e.g. terminal having Vin]; at least one output terminal [e.g. terminal having Vout]; a plurality of power switches [e.g. Q1 – Q10] and a plurality of flying capacitors configured to convert a DC input voltage [e.g. Vin] from the at least one input terminal to a DC output voltage [e.g. Vout] to the at least one output terminal by a switched-capacitor power conversion [e.g. Fig. 5], wherein at least one of the plurality of power switches is a segmented switch [e.g. Fig. 5; Q2 – Q6], comprising at least one internal switch-segment disposed on a first semiconductor die of a first semiconductor manufacturing technology [e.g. paragraph 023 recites “switch and capacitor network can include a plurality of the second-type power transistors (e.g., Q2-Q6) connected in series] and at least one external switch- segment disposed on a second semiconductor die of a second semiconductor manufacturing technology [e.g. paragraph 019 recites “first-type power transistor Q1 can be integrated into the first die”] different to the first semiconductor manufacturing technology [e.g. paragraph 019 recites “first-type power transistor Q1 can be integrated into the first die, and one or more second-type power transistors can be integrated into the second die. For example, first-type power transistor Q1 is a GaN power transistor”]; and performing a switched-capacitor DC-DC conversion by switching the plurality of power switches, using the at least one internal switch-segment and the at least one external switch-segment in order to convert a DC input voltage to a DC output voltage [e.g. paragraph 017 recites “The voltage converter can also include a control circuit that controls the multiplexed power transistors in a pulse-width modulation (PWM) mode, a pulse-frequency modulation (PFM) mode, or a PWM/PFM hybrid mode, in order to adjust the output voltage”].
Yao fails to disclose a plurality of gate drivers configured to drive the plurality of power switches.
Choi [e.g. Figs. 1 - 2] teaches a plurality of gate drivers [e.g. 122a1-122a3 and 122b1-122b3] configured to drive the plurality of power switches [e.g. 106a1-106a3 and 106b1-106b3].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Yao by a plurality of gate drivers configured to drive the plurality of power switches as taught by Choi in order of being able to respectively drive or control switching of the switches, paragraph 038.
Claim(s) 30, 33 – 35, 40 and 42 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yao in view of Choi and further in view of US Pub. No. 2015/0171748; (hereinafter Sandner).
Regarding claim 30, Yao fails to disclose wherein the first semiconductor die is of a MOS and/or Bipolar-CMOS-DMOS technology, preferably manufactured with lateral integration.
Sandner teaches wherein the first semiconductor die is of a MOS and/or Bipolar-CMOS-DMOS technology, preferably manufactured with lateral integration [e.g. paragraph 027 recites “One die is a CMOS type die and the other die is a FET or SFET type die.” Paragraph 028 recites “Throughout this disclosure the terms "CMOS type" and "FET or SFET type" are used to describe two different types or forms of semiconductor dies for use in implementing the circuits and techniques described herein. A CMOS type die as referred to herein describes a semiconductor die that includes primarily CMOS type transistors, or that the semiconductor die is primarily manufactured according to a CMOS type manufacturing process, or that the semiconductor die includes substantially more CMOS type transistors than other types of transistors.”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Yao by wherein the first semiconductor die is of a MOS and/or Bipolar-CMOS-DMOS technology, preferably manufactured with lateral integration as taught by Sandner in order of being able to provide accuracy of the power output, paragraph 04.
Regarding claim 33, Yao [e.g. Fig. 5 applied to Fig. 2] discloses wherein at least one external switch-segment comprises a GaN FET [e.g. paragraph 019 recites “first-type power transistor Q1 can be integrated into the first die, and one or more second-type power transistors can be integrated into the second die. For example, first-type power transistor Q1 is a GaN power transistor”] and/or an external vertical power MOSFET.
Yao fails to disclose wherein at least one internal switch-segment comprises a MOS and/or Bipolar-CMOS-DMOS-based transistor.
Sandner teaches wherein at least one internal switch-segment comprises a MOS and/or Bipolar-CMOS-DMOS-based transistor [e.g. paragraph 027 recites “One die is a CMOS type die and the other die is a FET or SFET type die.” Paragraph 028 recites “Throughout this disclosure the terms "CMOS type" and "FET or SFET type" are used to describe two different types or forms of semiconductor dies for use in implementing the circuits and techniques described herein. A CMOS type die as referred to herein describes a semiconductor die that includes primarily CMOS type transistors, or that the semiconductor die is primarily manufactured according to a CMOS type manufacturing process, or that the semiconductor die includes substantially more CMOS type transistors than other types of transistors.” Paragraph 053 recites “Many examples of one or more switches 30 exists and could be any type of switch devices that can be contained to a CMOS type die and further, when arranged in a power stage configuration, are suitable for stepping-down/bucking or stepping-up/boosting a voltage level of a power input. For instance, some examples of one or more switches 30 may include Silicon (Si), Gallium Nitride (GaN), and/or Silicon Carbide (SiC) based switching devices, normally-on or normally-off type switches, GaN high-electron-mobility transistors (HEMT), N-type MOSFET based switch devices, P-type MOSFET based switch devices, diodes, IGBT switch devices, drain extended MOS (deMOS) switch devices, or any other type of power switch transistors or switch device that can operate in a power stage configuration at a CMOS type die”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Yao by wherein at least one internal switch-segment comprises a MOS and/or Bipolar-CMOS-DMOS-based transistor as taught by Sandner in order of being able to provide accuracy of the power output, paragraph 04.
Regarding claim 34, Yao [e.g. Fig. 5 applied to Fig. 2] discloses at least one external switch-segment is GaN-based [e.g. paragraph 019 recites “first-type power transistor Q1 can be integrated into the first die, and one or more second-type power transistors can be integrated into the second die. For example, first-type power transistor Q1 is a GaN power transistor”].
Yao fails to disclose wherein at least one internal switch-segment is silicon-based transistor.
Sandner teaches [e.g. paragraph 028 recites “Throughout this disclosure the terms "CMOS type" and "FET or SFET type" are used to describe two different types or forms of semiconductor dies for use in implementing the circuits and techniques described herein. A CMOS type die as referred to herein describes a semiconductor die that includes primarily CMOS type transistors, or that the semiconductor die is primarily manufactured according to a CMOS type manufacturing process, or that the semiconductor die includes substantially more CMOS type transistors than other types of transistors.” Paragraph 053 recites “Many examples of one or more switches 30 exists and could be any type of switch devices that can be contained to a CMOS type die and further, when arranged in a power stage configuration, are suitable for stepping-down/bucking or stepping-up/boosting a voltage level of a power input. For instance, some examples of one or more switches 30 may include Silicon (Si), Gallium Nitride (GaN), and/or Silicon Carbide (SiC) based switching devices, normally-on or normally-off type switches, GaN high-electron-mobility transistors (HEMT), N-type MOSFET based switch devices, P-type MOSFET based switch devices, diodes, IGBT switch devices, drain extended MOS (deMOS) switch devices, or any other type of power switch transistors or switch device that can operate in a power stage configuration at a CMOS type die”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Yao by wherein at least one internal switch-segment is silicon-based transistor as taught by Sandner in order of being able to provide accuracy of the power output, paragraph 04.
Regarding claim 35, Yao [e.g. Fig. 5 applied to Fig. 2] discloses wherein a plurality of the power switches are segmented switches, comprising at least one internal switch-segment disposed on a first semiconductor die manufactured with a first material composition [e.g. paragraph 023 recites “switch and capacitor network can include a plurality of the second-type power transistors (e.g., Q2-Q6) connected in series] and at least one external switch-segment disposed on a second semiconductor die manufactured with a second material composition [e.g. paragraph 019 recites “first-type power transistor Q1 can be integrated into the first die, and one or more second-type power transistors can be integrated into the second die. For example, first-type power transistor Q1 is a GaN power transistor”].
Yao fails to disclose the fist and second semiconductor dies manufactured with different compositions.
Sandner [e.g. paragraph 027 – 028 recite “One die is a CMOS type die and the other die is a FET or SFET type die”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Yao by the fist and second semiconductor dies manufactured with different compositions as taught by Sandner in order of being able to provide accuracy of the power output, paragraph 04.
Regarding claim 40, Yao fails to disclose wherein the at least one internal switch-segment comprises at least one field-effect transistor, preferably at least one metal-oxide-semiconductor field-effect transistor, and wherein the at least one field-effect transistor is not stacked or cascaded field-effect transistor.
Sandner teaches wherein the at least one internal switch-segment comprises at least one field-effect transistor, preferably at least one metal-oxide-semiconductor field-effect transistor, and wherein the at least one field-effect transistor is not stacked or cascaded field-effect transistor [e.g. Paragraph 028 recites “Paragraph 053 recites “Many examples of one or more switches 30 exists and could be any type of switch devices that can be contained to a CMOS type die and further, when arranged in a power stage configuration, are suitable for stepping-down/bucking or stepping-up/boosting a voltage level of a power input. For instance, some examples of one or more switches 30 may include Silicon (Si), Gallium Nitride (GaN), and/or Silicon Carbide (SiC) based switching devices, normally-on or normally-off type switches, GaN high-electron-mobility transistors (HEMT), N-type MOSFET based switch devices, P-type MOSFET based switch devices, diodes, IGBT switch devices, drain extended MOS (deMOS) switch devices, or any other type of power switch transistors or switch device that can operate in a power stage configuration at a CMOS type die”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Yao by wherein the at least one internal switch-segment comprises at least one field-effect transistor, preferably at least one metal-oxide-semiconductor field-effect transistor, and wherein the at least one field-effect transistor is not stacked or cascaded field-effect transistor as taught by Sandner in order of being able to provide accuracy of the power output, paragraph 04.
Regarding claim 42, Yao fails to disclose wherein the at least one external switch-segment is at least one high electron mobility transistor.
Sandner [e.g. Fig. 2] teaches wherein the at least one external switch-segment is at least one high electron mobility transistor [e.g. paragraph 054 recites “some examples of one or more switches 32 may include Si, GaN, and/or Silicon Carbide SiC based switching devices, normally-on or normally-off type switches, HEMT (GaN), FET (GaN), diodes, JFETs (SiC, normally on or off), vertical or lateral type switch devices, metal-gate switch devices, poli-Si-gate switch devices, or any other type of power switch transistors or switch device that can operate in a power stage configuration at a FET or SFET type die”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Yao by wherein the at least one external switch-segment is at least one high electron mobility transistor as taught by Sandner in order of being able to provide accuracy of the power output, paragraph 04.
Claim(s) 39 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yao in view of Choi and further in view of US Pub. No. 2017/0244318; (hereinafter Giuliano).
Regarding claim 39, Yao fails to disclose wherein the switched- capacitor DC-DC converter further comprises at least one secondary external switch-segment disposed on a third semiconductor die.
Giuliano teaches wherein the switched- capacitor DC-DC converter further comprises at least one secondary external switch-segment disposed on a third semiconductor die [e.g. paragraph 020 recites “In some embodiments, the switched-capacitor converter is a two-phase converter. Some of these embodiments have third and fourth dies. The stack switches comprise first and second sets, each of which is associated with one of the two phases. The first set of stack switches is on the second die and the second set of stack switches is on the fourth die. Meanwhile, the phase switches comprise first and second sets of phase switches, each of which is associated with one of the two phases. The first set of phase switches is on the first die and the second set of phase switches is on the third die”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Yao by wherein the switched- capacitor DC-DC converter further comprises at least one secondary external switch-segment disposed on a third semiconductor die as taught by Giuliano in order of being able to handle a considerable amount of power without adversely affecting switch operation, paragraph 428.
Claim(s) 41 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yao in view of Choi and further in view of US Pub. No. 2006/0285366; (hereinafter Radecker).
Regarding claim 41, Yao fails to disclose wherein the at least one field-effect transistor is a high-voltage transistor, with a blocking voltage equal or higher to the DC input voltage.
Radecker teaches wherein the at least one field-effect transistor is a high-voltage transistor, with a blocking voltage equal or higher to the DC input voltage [e.g. paragraph 0276 recites “An output VG, for example, drives the IGBT transistor or a high-voltage MOSFET (HV MOSFET) which must block the voltage which is twice or four times as high as that of the mains input voltage peak value (AC)”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Yao by wherein the at least one field-effect transistor is a high-voltage transistor, with a blocking voltage equal or higher to the DC input voltage as taught by Radecker in order of being able to handle high voltages without damage.
Claim(s) 41 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yao in view of Choi and further in view of US Patent No. 10,637,355; (hereinafter Shao).
Regarding claim 43, Yao fails to disclose wherein at least two of the plurality of gate drivers are supplied from the DC input voltage.
Shao [e.g. Fig. 1] teaches wherein at least two of the plurality of gate drivers [e.g. 108-2, 108-3] are supplied from the DC input voltage [e.g. VIN].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Yao by wherein at least two of the plurality of gate drivers are supplied from the DC input voltage as taught by Shao in order of being able to provide required voltage to the drivers so as to properly drive the power transistors.
Examiner's Note
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alex Torres-Rivera whose telephone number is (571)272-5261. The examiner can normally be reached M-F 9:00-5:30 ET.
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/ALEX TORRES-RIVERA/Primary Examiner, Art Unit 2838
Prosecution Insights