Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the application filed 1/16/2025 in which Claims 1-19, 21 are pending and Claims 20, 22-23 are canceled.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-7, 9-11, 14-18, 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chinese Patent Publication 113744683 to Cheng et al (“Cheng”) (relied upon English translation).
As to Claim 1, Cheng teaches a pixel circuit, comprising: a driving circuit, comprising a control terminal, a first terminal and a second terminal, and configured to control a magnitude of a driving current flowing through the first terminal and the second terminal (the control terminal of the driving circuit 10 is electrically connected with the second node N2, the first terminal of the driving circuit 10 is electrically connected with the first node N1, the second terminal of the driving circuit 10 is electrically connected with the third node N3, the drive circuit 10 is used for under the control of the potential of the second node N2, controlling the connection between the first node N1 and the third node N3 [control a magnitude of a driving current flowing through a first terminal and a second terminal], see ¶ 0048; the gate of the driving transistor T0 is electrically connected with the second node N2, the source of the driving transistor T0 is electrically connected with the first node N1; the drain of the driving transistor T0 is electrically connected with the third node N3, see ¶ 0074-0075; Figure 2: T0);
a data writing circuit, wherein a first terminal of the data writing circuit is electrically connected with a second terminal of the driving circuit, and the second terminal of the data writing circuit is configured to receive a data signal, and the data writing circuit is configured to write the data signal to the second terminal of the driving circuit in response to a data scanning signal in a data writing stage (the data writing circuit 14 comprises a fourth transistor T4; the control electrode of the fourth transistor T4 is electrically connected with the first scanning line Gn, the first electrode of the fourth transistor T4 is electrically connected with the data line Data, the second electrode of the fourth transistor T4 is electrically connected with the third node N3, see ¶ 0069-0070; Figure 2: T4);
a first compensation circuit, comprising a control terminal, a first terminal and a second terminal, wherein a control terminal of the first compensation circuit is configured to receive a first compensation control signal, the first terminal of the first compensation circuit is electrically connected with the first terminal of the driving circuit, and the second terminal of the first compensation circuit is electrically connected with the control terminal of the driving circuit, and the first compensation circuit is configured to control the control terminal of the driving circuit and the first terminal of the driving circuit whether to be electrically conducted through the first compensation circuit in response to the first compensation control signal (the control electrode of the third transistor is electrically connected with the reset control line Reset [compensation control signal], the first electrode of the third transistor is electrically connected with the first node N1, the second electrode of the third transistor is electrically connected with the second node N2, see ¶ 0068; the control terminal of the driving circuit 10 is electrically connected with the second node N2, the first terminal of the driving circuit 10 is electrically connected with the first node N1, see ¶ 0048; the compensation control circuit, under the control of the rest control signal, controls the connection between the first node and the second node, so that the second node is connected to the power supply voltage terminal, see ¶ 0027; Figure 2: T3 connected at its first terminal to node N1 which shares a connection with the first terminal of the driving transistor T0 and connected at its second terminal to node N2 which shares a connection with the control terminal of the driving transistor T0); and
a second compensation circuit, comprising a compensation capacitor, wherein a first electrode plate of the compensation capacitor is electrically connected with the control terminal of the driving circuit (the first end of the storage capacitor is electrically connected to the second node N2, see ¶ 0076; the control terminal of the driving circuit 10 is electrically connected with the second node N2, see ¶ 0048; Figure 2: Cst connected at its first end to node N2 which shares a connection with the control terminal of the driving transistor T0).
As to Claim 2, Cheng depending on Claim 1, Cheng teaches wherein the first compensation circuit and the second compensation circuit are configured to allow a potential of the control terminal of the driving circuit to change in response to a potential change of the second terminal of the driving circuit in the data writing stage (the control terminal of the driving circuit 10 is electrically connected with the second node N2, the first terminal of the driving circuit 10 is electrically connected with the first node N1, see ¶ 0048; the compensation control circuit, under the control of the reset control signal, controls the connection between the first node and the second node, so that the second node is connected to the power supply voltage terminal, see ¶ 0027; the first end of the storage capacitor [second compensation circuit] is electrically connected to the second node N2, see ¶ 0076; the data writing stage t2, Reset and Gn provide a high voltage signal, Gn + 1 provides a low voltage signal, EM1 and EM2 provide a low voltage signal, Data provides a data voltage Vdata; As shown in FIG. 4 B, T2 is turned off, T5 and T1 are turned off, T3 [first compensation circuit] and T4 are turned on, Vdata is written into N3, and N2 is controlled to communicate with N1, see ¶ 0098; Figure 2: T3 connected at its first terminal to node N1 which shares a connection with the first terminal of the driving transistor T0 and connected at its second terminal to node N2 which shares a connection with the control terminal of the driving transistor T0), and to maintain the potential of the control terminal of the driving circuit in a compensation stage after the data writing stage and not allow the potential of the control terminal of the driving circuit to change in response to the potential change of the second terminal of the driving circuit (when the data writing stage t2 starts, T0 is conducted, the charge stored in Cst is discharged through T2, T3 and T6, so as to control the potential of reducing N2 [maintain the potential of the control terminal of the driving circuit in a compensation stage after the data writing stage], until T0 is cut off, the potential of N2 is changed to Vdata + Vth, wherein Vth is the threshold voltage of T0 [not allow the potential of the control terminal of the driving circuit to change in response to potential change of the second terminal of driving circuit], see ¶ 0099).
As to Claim 3, Cheng depending on Claim 1, Cheng teaches wherein the driving circuit comprises a driving transistor, a gate electrode of the driving transistor serves as the control terminal of the driving circuit, a first electrode of the driving transistor serves as the first terminal of the driving circuit, a second electrode of the driving transistor serves as the second terminal of the driving circuit (the control terminal of the driving circuit 10 is electrically connected with the second node N2, the first terminal of the driving circuit 10 is electrically connected with the first node N1, the second terminal of the driving circuit 10 is electrically connected with the third node N3, the drive circuit 10 is used for under the control of the potential of the second node N2, controlling the connection between the first node N1 and the third node N3, see ¶ 0048; the gate of the driving transistor T0 is electrically connected with the second node N2, the source of the driving transistor T0 is electrically connected with the first node N1; the drain of the driving transistor T0 is electrically connected with the third node N3, see ¶ 0074-0075; Figure 2: T0), and the first terminal of the driving circuit is electrically connected with a first power supply voltage terminal to receive a first power supply voltage (the drive circuit 10 is used for under the control of the potential of the second node N2, controlling the connection between the first node N1 and the third node N3, see ¶ 0048; Figure 2 illustrates the first node N1 is connected to the power supply voltage terminal); the pixel circuit further comprises a light emitting element, the light emitting element is configured to emit light driven by the driving current (the light-emitting element EL is an organic light-emitting diode O1, see ¶ 0077; T0 generates a driving current Ids to drive O1 to emit light, see ¶ 0101), the second terminal of the driving circuit is electrically connected with a first electrode of the light emitting element, and the driving circuit is configured to control a magnitude of a driving current flowing through the light emitting element (T0 generates a driving current Ids to drive O1 to emit light, see ¶ 0101; Figure 2 illustrates the second terminal of the driving transistor T0 connected with the first electrode of the organic light-emitting diode O1);
the first compensation circuit comprises a first compensation transistor, a gate electrode of the first compensation transistor receives the first compensation control signal, a first electrode of the first compensation transistor is electrically connected with the first electrode of the driving transistor, and a second electrode of the first compensation transistor is electrically connected with the gate electrode of the driving transistor (the control electrode of the third transistor is electrically connected with the reset control line Reset [compensation control signal], the first electrode of the third transistor is electrically connected with the first node N1, the second electrode of the third transistor is electrically connected with the second node N2, see ¶ 0068; the control terminal of the driving circuit 10 is electrically connected with the second node N2, the first terminal of the driving circuit 10 is electrically connected with the first node N1, see ¶ 0048; the compensation control circuit, under the control of the reset control signal, controls the connection between the first node and the second node, so that the second node is connected to the power supply voltage terminal, see ¶ 0027; Figure 2: T3 connected at its first terminal to node N1 which shares a connection with the first terminal of the driving transistor T0 and connected at its second terminal to node N2 which shares a connection with the control terminal of the driving transistor T0).
As to Claim 5, Cheng depending on Claim 3, Cheng teaches wherein the first electrode plate of the compensation capacitor is electrically connected with the gate electrode of the driving transistor, and a second electrode plate of the compensation capacitor is electrically connected with the first electrode of the light emitting element (the first end of the energy storage circuit 15 is electrically connected with the second node N2, the second end of the energy storage circuit 15 is electrically connected with the first electrode of the light emitting element EL, the energy storage circuit 15 is used for storing electric energy, see ¶ 0076; the control terminal of the driving circuit 10 is electrically connected with the second node N2, see ¶ 0048).
As to Claim 6, Cheng depending on Claim 1, Cheng teaches wherein the pixel circuit further comprises a first reset circuit, a control terminal of the first reset circuit is configured to receive a first reset control signal, a first terminal of the first reset circuit is electrically connected with the second terminal of the driving circuit, and a second terminal of the first reset circuit is electrically connected with a first reset signal terminal to receive a first reset signal (the gate of the first transistor T1 is electrically connected to the second scan line Gn+1, the source of the first transistor T1 is electrically connected to the initial voltage terminal, and the drain of the first transistor T1 is electrically connected to the third node N3; the initial voltage terminal is used to provide the initial voltage Vini, see ¶ 0079; Figure 2 illustrates the first transistor T1 connected to node N3 which shares a connection with the second terminal of the driving transistor T0),
the first reset circuit is configured to write the first reset signal to the second terminal of the driving circuit in response to the first reset control signal (during the node potential control phase, the conduction control circuit writes the first initial voltage into the third node, see ¶ 0114; Figure 2 illustrates the first transistor T1 is connected to the second terminal of the driving circuit).
As to Claim 7, Cheng depending on Claim 6, Cheng teaches wherein the first reset circuit comprises a first reset transistor, a gate electrode of the first reset transistor is electrically connected with a first reset control terminal to receive the first reset control signal, a first electrode of the first reset transistor is electrically connected with the second terminal of the driving circuit, and a second electrode of the first reset transistor is electrically connected with the first reset signal terminal to receive the first reset signal (the gate of the first transistor T1 is electrically connected to the second scan line Gn+1, the source of the first transistor T1 is electrically connected to the initial voltage terminal, and the drain of the first transistor T1 is electrically connected to the third node N3; the initial voltage terminal is used to provide the initial voltage Vini, see ¶ 0079; Figure 2 illustrates the first transistor T1 connected to node N3 which shares a connection with the second terminal of the driving transistor T0);
the data writing circuit comprises a data writing transistor, a gate electrode of the data writing transistor is configured to receive the data scanning signal, the first electrode of the data writing transistor is electrically connected with the second terminal of the driving circuit, and the second electrode of the data writing transistor is electrically connected with a data signal terminal to receive the data signal (the data writing circuit 14 comprises a fourth transistor T4; the control electrode of the fourth transistor T4 is electrically connected with the first scanning line Gn [data scanning signal], the first electrode of the fourth transistor T4 is electrically connected with the data line Data [data signal], the second electrode of the fourth transistor T4 is electrically connected with the third node N3, see ¶ 0069-0070; Figure 2 illustrates transistor T4 connected via node N3 to the second terminal of the driving transistor T0);
the data writing transistor and the first reset transistor are independent and different transistors, and the data signal terminal and the first reset signal terminal are independent and different signal terminals or, the data writing transistor also serves as the first reset transistor, the data scanning signal also serves as the first reset control signal, and the data signal terminal also serves as the first reset signal terminal, and is configured to receive the data signal and the first reset signal at different time periods, respectively (Figure 2 illustrates transistor T4 [data writing transistor] and transistor T1 [first reset transistor] as independent, different transistors having different reset and data scanning terminals).
As to Claim 9, Cheng depending on Claim 1, Cheng teaches wherein the pixel circuit further comprises a light emitting element, the light emitting element is configured to emit light driven by the driving current, the second terminal of the driving circuit is electrically connected with a first electrode of the light emitting element, and the driving circuit is configured to control a magnitude of a driving current flowing through the light emitting element (driving transistor T0 generates a driving current Ids to drive O1 to emit light, see ¶ 0101; Figure 2 illustrates the second terminal of the driving transistor T0 connected with the first electrode of the organic light-emitting diode O1);
the pixel circuit further comprises a second reset circuit, a control terminal of the second reset circuit is configured to receive a second reset control signal, a first terminal of the second reset circuit is electrically connected with the first electrode of the light emitting element, and the second terminal of the second reset circuit is electrically connected with a second reset signal terminal to receive a second reset signal (the gate of the sixth transistor T6 is electrically connected to the reset control line Reset, the source of the sixth transistor T6 is electrically connected to the initial voltage terminal, and the second terminal of the sixth transistor is electrically connected to the anode of O1, see ¶ 0087), the second reset circuit is configured to apply the second reset signal to the first electrode of the light emitting element and/or the second electrode plate of the compensation capacitor in response to the second reset control signal (Figure 2 illustrates that transistor T6 [second reset circuit] applies the second reset signal to the second electrode of Cst in response to the reset control signal).
As to Claim 10, Cheng depending on Claim 1, Cheng teaches wherein the pixel circuit further comprises a second reset circuit, a control terminal of the second reset circuit is configured to receive a second reset control signal, a first terminal of the second reset circuit is electrically connected with the second terminal of the driving circuit, and a second terminal of the second reset circuit is electrically connected with a second reset signal terminal to receive a second reset signal (the gate of the sixth transistor T6 is electrically connected to the reset control line Reset, the source of the sixth transistor T6 is electrically connected to the initial voltage terminal [second reset signal terminal], and the second terminal of the sixth transistor is electrically connected to the anode of O1, see ¶ 0087; Figure 2 illustrates the first terminal of the sixth transistor is connected to the second terminal of the driving circuit), the second reset circuit is configured to apply the second reset signal to the second terminal of the driving circuit and/or the second electrode plate of the compensation capacitor in response to the second reset control signal (Figure 2 illustrates that transistor T6 [second reset circuit] applies the second reset signal to the second electrode of Cst in response to the reset control signal).
As to Claim 11, Cheng depending on Claim 10, Cheng teaches wherein the first reset circuit comprises a first reset transistor, a gate electrode of the first reset transistor is electrically connected with a first reset control terminal to receive a first reset control signal, a first electrode of the first reset transistor is electrically connected with the second terminal of the driving circuit, and a second electrode of the first reset transistor is electrically connected with a first reset signal terminal to receive a first reset signal (the gate of the first transistor T1 is electrically connected to the second scan line Gn+1, the source of the first transistor T1 is electrically connected to the initial voltage terminal, and the drain of the first transistor T1 is electrically connected to the third node N3; the initial voltage terminal is used to provide the initial voltage Vini, see ¶ 0079; Figure 2 illustrates the first transistor T1 connected to node N3 which shares a connection with the second terminal of the driving transistor T0);
the second reset circuit comprises a second reset transistor, a gate electrode of the second reset transistor is electrically connected with a second reset control terminal to receive the second reset control signal, a first electrode of the second reset transistor is electrically connected with the second terminal of the driving circuit, and a second electrode of the second reset transistor is electrically connected with the second reset signal terminal to receive the second reset signal (the gate of the sixth transistor T6 is electrically connected to the reset control line Reset, the source of the sixth transistor T6 is electrically connected to the initial voltage terminal [second reset signal terminal], and the second terminal of the sixth transistor is electrically connected to the anode of O1, see ¶ 0087; Figure 2 illustrates the first terminal of the sixth transistor is connected to the second terminal of the driving circuit);
the first reset transistor also serves as the second reset transistor, the first reset control signal also serves as the second reset control signal, and the first reset signal terminal also serves as the second reset signal terminal, and is configured to receive the first reset signal and the second reset signal respectively in different time periods; or, the second reset transistor and the first reset transistor are independent and different transistors, and the first reset signal terminal and the second reset signal terminal are independent and different signal terminals (Figure 2 illustrates transistor T1 [first reset transistor] and transistor T6 [second reset transistor] as independent, different transistors having different reset and data scanning terminals).
As to Claim 14, Cheng depending on Claim 1, Cheng teaches wherein the first compensation circuit comprises a first compensation transistor, a first electrode of the first compensation circuit is electrically connected with the first terminal of the driving circuit, and a second electrode of the first compensation circuit is electrically connected with a control driving terminal of the driving circuit (the control electrode of the third transistor is electrically connected with the reset control line Reset [compensation control signal], the first electrode of the third transistor is electrically connected with the first node N1, the second electrode of the third transistor is electrically connected with the second node N2, see ¶ 0068; the control terminal of the driving circuit 10 is electrically connected with the second node N2, the first terminal of the driving circuit 10 is electrically connected with the first node N1, see ¶ 0048; Figure 2: T3 connected at its first terminal to node N1 which shares a connection with the first terminal of the driving transistor T0 and connected at its second terminal to node N2 which shares a connection with the control terminal of the driving transistor T0).
the second reset circuit comprises a second reset transistor, a gate electrode of the second reset transistor is electrically connected with a second reset control terminal to receive a second reset control signal, a first electrode of the second reset transistor is electrically connected with the second terminal of the driving circuit, and a second electrode of the second reset transistor is electrically connected with the second reset signal terminal to receive the second reset signal (the gate of the sixth transistor T6 is electrically connected to the reset control line Reset, the source of the sixth transistor T6 is electrically connected to the initial voltage terminal [second reset signal terminal], and the second terminal of the sixth transistor is electrically connected to the anode of O1, see ¶ 0087; Figure 2 illustrates the first terminal of the sixth transistor is connected to the second terminal of the driving circuit);
a gate electrode of the first compensation transistor and the gate electrode of the second reset transistor are connected with a same gate line, and the second reset control signal and the first compensation control signal are a same gate scanning signal (Under the control of the reset control signal provided by Reset, the compensation control circuit 12 controls the connection between the first node N1 and the second node N2. Under the control of the reset control signal provided by Reset, the initialization circuit 22 writes the second initial voltage Vini2 to the first electrode of the light-emitting element EL, see ¶ 0060).
As to Claim 15, Cheng depending on Claim 10, Cheng teaches wherein the pixel circuit further comprises a first light emission control circuit and a second light emission control circuit (the first light-emitting control circuit 11 includes a second transistor, see ¶ 0066; the second light-emitting control circuit 21 includes a fifth transistor, see ¶ 0071); a control terminal of the first light emission control circuit is configured to receive a first light emission control signal, a first terminal of the first light emission control circuit is electrically connected with the first terminal of the driving circuit, and a second terminal of the first light emission control circuit is electrically connected with a first voltage terminal to receive a first power supply voltage, and the first light emission control circuit is configured to apply the first power supply voltage to the first terminal of the driving circuit in response to the first light emission control signal (the control electrode of the second transistor is electrically connected to the first light-emitting control line EM1, the first electrode of the second transistor is electrically connected to the power supply voltage terminal [first power supply voltage], and the second electrode of the second transistor is electrically connected to the first node N1, see ¶ 0067; during the light emitting stage, the first light-emitting control circuit 11 controls the connection between the power supply voltage terminal and the first node N1 under the control of the first light-emitting control signal provided by EM1…and the driving circuit 10 drives the light-emitting element EL to emit light, see ¶ 0063);
a control terminal of the second light emission control circuit is configured to receive a second light emission control signal, the second light emission control signal is different from the first light emission control signal, a first terminal of the second light emission control circuit is electrically connected with the second terminal of the driving circuit, a second terminal of the second light emission control circuit is electrically connected with the first electrode of the light emitting element, and the second electrode of the light emitting element is electrically connected with a second voltage terminal to receive a second power supply voltage, and the second light emission control circuit is configured to apply the driving current to the light emitting element in response to the second light emission control signal (the control electrode of the fifth transistor is electrically connected to the second light-emitting control line EM2, the first electrode of the fifth transistor is electrically connected to the third node N3, and the second electrode of the fifth transistor is electrically connected to the first electrode of the light-emitting element EL, see ¶ 0072; during the light emitting stage…the second light-emitting control circuit 21 controls the connection between the third node N3 and the first pole of the light-emitting element EL under the control of the second light-emitting control signal provided by EM2, and the driving circuit 10 drives the light-emitting element EL to emit light, see ¶ 0063).
As to Claim 16, Cheng depending on Claim 1, Cheng teaches a display device comprising a pixel circuit (display technology, and more particularly to a pixel circuit, driving method and display device, see ¶ 0001).
As to Claim 17, Cheng depending on Claim 1, Cheng teaches a driving method of a pixel circuit, wherein the pixel circuit pixel circuit comprises: a driving circuit, comprising a control terminal, a first terminal and a second terminal, and configured to control a magnitude of a driving current flowing through the first terminal and the second terminal (the control terminal of the driving circuit 10 is electrically connected with the second node N2, the first terminal of the driving circuit 10 is electrically connected with the first node N1, the second terminal of the driving circuit 10 is electrically connected with the third node N3, the drive circuit 10 is used for under the control of the potential of the second node N2, controlling the connection between the first node N1 and the third node N3 [control a magnitude of a driving current flowing through a first terminal and a second terminal], see ¶ 0048; the gate of the driving transistor T0 is electrically connected with the second node N2, the source of the driving transistor T0 is electrically connected with the first node N1; the drain of the driving transistor T0 is electrically connected with the third node N3, see ¶ 0074-0075; Figure 2: T0);
a data writing circuit, wherein a first terminal of the data writing circuit is electrically connected with a second terminal of the driving circuit, and the second terminal of the data writing circuit is configured to receive a data signal, and the data writing circuit is configured to write the data signal to the second terminal of the driving circuit in response to a data scanning signal in a data writing stage (the data writing circuit 14 comprises a fourth transistor T4; the control electrode of the fourth transistor T4 is electrically connected with the first scanning line Gn, the first electrode of the fourth transistor T4 is electrically connected with the data line Data, the second electrode of the fourth transistor T4 is electrically connected with the third node N3, see ¶ 0069-0070; Figure 2: T4);
a first compensation circuit, comprising a control terminal, a first terminal and a second terminal, wherein a control terminal of the first compensation circuit is configured to receive a first compensation control signal, the first terminal of the first compensation circuit is electrically connected with the first terminal of the driving circuit, and the second terminal of the first compensation circuit is electrically connected with the control terminal of the driving circuit, and the first compensation circuit is configured to control the control terminal of the driving circuit and the first terminal of the driving circuit whether to be electrically conducted through the first compensation circuit in response to the first compensation control signal (the control electrode of the third transistor is electrically connected with the reset control line Reset [compensation control signal], the first electrode of the third transistor is electrically connected with the first node N1, the second electrode of the third transistor is electrically connected with the second node N2, see ¶ 0068; the control terminal of the driving circuit 10 is electrically connected with the second node N2, the first terminal of the driving circuit 10 is electrically connected with the first node N1, see ¶ 0048; the compensation control circuit, under the control of the rest control signal, controls the connection between the first node and the second node, so that the second node is connected to the power supply voltage terminal, see ¶ 0027; Figure 2: T3 connected at its first terminal to node N1 which shares a connection with the first terminal of the driving transistor T0 and connected at its second terminal to node N2 which shares a connection with the control terminal of the driving transistor T0); and
a second compensation circuit, comprising a compensation capacitor, wherein a first electrode plate of the compensation capacitor is electrically connected with the control terminal of the driving circuit (the first end of the storage capacitor is electrically connected to the second node N2, see ¶ 0076; the control terminal of the driving circuit 10 is electrically connected with the second node N2, see ¶ 0048; Figure 2: Cst connected at its first end to node N2 which shares a connection with the control terminal of the driving transistor T0).
the driving method of the pixel circuit comprises: in the data writing stage, setting the data scanning signal as a turn-on signal to turn on the data writing circuit, wherein the data signal is written to the second terminal of the driving circuit through the data writing circuit (during the data writing phase, under the control of the first scan signal provided by Gn, the data writing circuit 14 writes the data voltage Vdata on the data line Data to the third node N3 [second terminal of the driving circuit]. Under the control of the reset control signal provided by Reset, the compensation control circuit 12 controls the connection between the first node N1 and second node N2, see ¶ 0060), and the potential of the control terminal of the driving circuit changes in response to the potential change of the second terminal of the driving circuit by controlling the first compensation circuit and the second compensation circuit (Under the control of the reset control signal provided by Reset, the compensation control circuit 12 controls the connection between the first node N1 and second node N2, see ¶ 0060. Figure 2 illustrates the potential of the control terminal is controlled at node N2 via the first compensation circuit, T3, and the second compensation circuit, Cst); and
in a compensation stage after the data writing stage, controlling the first compensation circuit and the second compensation circuit to maintain the potential of the control terminal of the driving circuit, wherein the potential of the control terminal of the driving circuit is not allowed to change in response to the potential change of the second terminal of the driving circuit (when the data writing stage t2 starts, T0 is conducted, the charge stored in Cst is discharged through T2, T3 and T6, so as to control the potential of reducing N2 [maintain the potential of the control terminal of the driving circuit in a compensation stage after the data writing stage], until T0 is cut off, the potential of N2 is changed to Vdata + Vth, wherein Vth is the threshold voltage of T0 [not allow the potential of the control terminal of the driving circuit to change in response to potential change of the second terminal of driving circuit], see ¶ 0099).
As to Claim 18, Cheng depending on Claim 1, Cheng teaches wherein in the data writing stage, the first compensation control signal is set as a turn-on signal to turn on the first compensation circuit in response to the first compensation control signal, the control terminal of the driving circuit and the first terminal of the driving circuit are electrically conducted through the first compensation circuit, and the first terminal of the driving circuit and the second terminal of the driving circuit are electrically conducted, as to generate a compensation current between the control terminal of the driving circuit and the second terminal of the driving circuit (Under the control of the reset control signal provided by Reset, the compensation control circuit 12 controls the connection between the first node N1 and second node N2, see ¶ 0060. Figure 2 illustrates the potential of the control terminal is controlled at node N1 via the first compensation circuit, T3), and
the compensation current flows through the first compensation circuit and the driving circuit, so that the potential of the control terminal of the driving circuit changes in response to the change of a potential of the second terminal of the driving circuit (Under the control of the reset control signal provided by Reset, the compensation control circuit 12 controls the connection between the first node N1 and second node N2, see ¶ 0060. Figure 2 illustrates the potential of the control terminal is controlled at node N1 via the first compensation circuit, T3);
in the compensation stage, at least the first compensation control signal is set as a turn-off signal to turn off the first compensation circuit, so that no current is allowed to generate between the control terminal of the driving circuit and the second terminal of the driving circuit, and the potential of the control terminal of the driving circuit is maintained unchanged, and the potential of the control terminal of the driving circuit is not allowed to change in response to the potential change of the second terminal of the driving circuit (during the node potential control phase t3, reset and Gn both provide low voltage signals, Gn+1 provides a high voltage signal, and EM1 and EM2 provide low voltage signals. T2, T3, T4, T5 and T6 are all cut off, and T1 is turned on to write Vini into N3, so as to ensure that T0 can be turned on during the light emission phase t4, see ¶ 0100; during the node potential control phase, the conduction control circuit, under the control of the second scan signal, writes the first initial voltage into the third node so that during the light emission phase, the driving circuit can control the connection between the first node and the third node, see ¶ 0112).
As to Claim 21, Cheng depending on Claim 18, Cheng teaches wherein the driving circuit comprises a driving transistor, a gate electrode of the driving transistor serves as the control terminal of the driving circuit, a first electrode of the driving transistor serves as the first terminal of the driving circuit, and a second electrode of the driving transistor serves as the second terminal of the driving circuit (the control terminal of the driving circuit 10 is electrically connected with the second node N2, the first terminal of the driving circuit 10 is electrically connected with the first node N1, the second terminal of the driving circuit 10 is electrically connected with the third node N3, see ¶ 0048; the gate of the driving transistor T0 is electrically connected with the second node N2, the source of the driving transistor T0 is electrically connected with the first node N1; the drain of the driving transistor T0 is electrically connected with the third node N3, see ¶ 0074-0075; Figure 2: T0);
the first compensation circuit comprises a first compensation transistor, a gate electrode of the first compensation transistor receives the first compensation control signal, a first electrode of the first compensation transistor is electrically connected with the first electrode of the driving transistor, and a second electrode of the first compensation transistor is electrically connected with the gate electrode of the driving transistor (the control electrode of the third transistor is electrically connected with the reset control line Reset [compensation control signal], the first electrode of the third transistor is electrically connected with the first node N1, the second electrode of the third transistor is electrically connected with the second node N2, see ¶ 0068);
the pixel circuit further comprises a light emitting element configured to emit light under driving of the driving current, wherein the second terminal of the driving circuit is electrically connected with a first electrode of the light emitting element, and the driving circuit is configured to control a magnitude of a driving current flowing through the light emitting element (driving transistor T0 generates a driving current Ids to drive O1 to emit light, see ¶ 0101; Figure 2 illustrates the second terminal of the driving transistor T0 connected with the first electrode of the organic light-emitting diode O1);
the first electrode plate of the compensation capacitor is electrically connected with the gate electrode of the driving transistor, and a second electrode plate of the compensation capacitor is electrically connected with the first electrode of the light emitting element (the first end of the storage capacitor is electrically connected to the first node N1, and the second end of the storage capacitor is electrically connected to the first electrode of the light-emitting element EL, see ¶ 0076);
the driving method comprises: in the data writing stage, setting the first compensation control signal as a turn-on signal to turn on the first compensation transistor to generate the compensation current (Under the control of the reset control signal provided by Reset, the compensation control circuit 12 controls the connection between the first node N1 and second node N2, see ¶ 0060. Figure 2 illustrates the potential of the control terminal is controlled at node N1 via the first compensation circuit, T3); and
in the compensation stage, setting the first compensation control signal as a turn-off signal to turn off the first compensation transistor to maintain the potential of the control terminal of the driving circuit unchanged (during the node potential control phase t3, reset and Gn both provide low voltage signals, Gn+1 provides a high voltage signal, and EM1 and EM2 provide low voltage signals. T2, T3, T4, T5 and T6 are all cut off, and T1 is turned on to write Vini into N3, so as to ensure that T0 can be turned on during the light emission phase t4, see ¶ 0100; during the node potential control phase, the conduction control circuit, under the control of the second scan signal, writes the first initial voltage into the third node so that during the light emission phase, the driving circuit can control the connection between the first node and the third node, see ¶ 0112).
Claim Rejections - 35 USC § 103
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
8. Claim(s) 8 is rejected under 35 U.S.C. 103 as being unpatentable over Chinese Patent Publication 113744683 to Cheng et al (“Cheng”) (relied upon English translation) in view of U.S. Patent Publication 2021/0065624 to Li et al (“Li”).
As to Claim 8, Cheng depending from Claim 1, Cheng does not expressly disclose wherein the pixel circuit further comprises an auxiliary capacitor, a first electrode plate of the auxiliary capacitor is electrically connected with the second terminal of the driving circuit, and a second electrode plate of the auxiliary capacitor is electrically connected with a first reset signal voltage terminal. Li teaches wherein the pixel circuit further comprises an auxiliary capacitor, a first electrode plate of the auxiliary capacitor is electrically connected with the second terminal of the driving circuit, and a second electrode plate of the auxiliary capacitor is electrically connected with a first reset signal voltage terminal (the storage circuit 11 comprises a first capacitor C1. A first terminal of the first capacitor C1 is connected to a first power supply terminal V1 [first reset signal voltage terminal], a second terminal of the first capacitor C1 is connected to a first node S [second terminal of the driving circuit], and the data writing circuit 12 is also connected to the first node S, that is, the second terminal of the first capacitor C1 is connected to the data writing circuit 12, see ¶ 0045).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Cheng with Li to teach wherein the pixel circuit further comprises an auxiliary capacitor, a first electrode plate of the auxiliary capacitor is electrically connected with the second terminal of the driving circuit, and a second electrode plate of the auxiliary capacitor is electrically connected with a first reset signal voltage terminal. The suggestion/motivation would have been in order to write the compensation voltage to the compensation circuit according to the stored data voltage (see ¶ 0019).
Claim(s) 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Chinese Patent Publication 113744683 to Cheng et al (“Cheng”) (relied upon English translation) in view of U.S. Patent Publication 2022/0122522 to Li et al (“Li”).
As to Claim 12, Cheng depending from Claim 1, Cheng does not expressly disclose wherein the pixel circuit further comprises a third reset circuit, a control terminal of the third reset circuit is configured to receive a third reset control signal, a first terminal of the third reset circuit is electrically connected with the first terminal of the driving circuit, and a second terminal of the third reset circuit is electrically connected with a third reset signal terminal to receive the third reset signal, the third reset circuit is configured to apply the third reset signal to the first terminal of the driving circuit in response to the third reset signal. Li teaches wherein the pixel circuit further comprises a third reset circuit, a control terminal of the third reset circuit is configured to receive a third reset control signal, a first terminal of the third reset circuit is electrically connected with the first terminal of the driving circuit, and a second terminal of the third reset circuit is electrically connected with a third reset signal terminal to receive the third reset signal, the third reset circuit is configured to apply the third reset signal to the first terminal of the driving circuit in response to the third reset signal (the reset module 15 includes a fourth transistor T4. The first terminal of the fourth transistor T4 receives the reset signal Vini [second terminal of the third reset circuit receives a third reset signal]. The second terminal of the fourth transistor T4 is electrically connected to the second terminal of the driving transistor T0 [first terminal of the third reset circuit connected with first terminal of the driving circuit]. A gate of the fourth transistor T4 receives a third scan signal s2-p1 [third reset control signal], see ¶ 0072).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Cheng with Li to teach wherein the pixel circuit further comprises a third reset circuit, a control terminal of the third reset circuit is configured to receive a third reset control signal, a first terminal of the third reset circuit is electrically connected with the first terminal of the driving circuit, and a second terminal of the third reset circuit is electrically connected with a third reset signal terminal to receive the third reset signal, the third reset circuit is configured to apply the third reset signal to the first terminal of the driving circuit in response to the third reset signal. The suggestion/motivation would have been in order to write the compensation voltage to the compensation circuit according to the stored data voltage (see ¶ 0019).
As to Claim 13, Cheng and Li depending from Claim 12, Li teaches wherein the third reset circuit comprises a third reset transistor, a gate electrode of the third reset transistor is configured to receive a third reset control signal, a first electrode of the third reset transistor is electrically connected with the first electrode of the first compensation transistor and the first terminal of the driving circuit, and the first electrode of the third reset transistor is electrically connected with a third reset signal terminal to receive the third reset signal (the reset module 15 includes a fourth transistor T4. The first terminal of the fourth transistor T4 receives the reset signal Vini [second terminal of the third reset circuit receives a third reset signal]. The second terminal of the fourth transistor T4 is electrically connected to the second terminal of the driving transistor T0 [first terminal of the third reset circuit connected with first terminal of the driving circuit]. A gate of the fourth transistor T4 receives a third scan signal s2-p1 [third reset control signal], see ¶ 0072. Figure 2 illustrates the first electrode of the fourth transistor T4 connected to the first terminal of the driving transistor via node N3).
Allowable Subject Matter
Claims 4, 19 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/EBONI N GILES/Examiner, Art Unit 2622
/PATRICK N EDOUARD/Supervisory Patent Examiner, Art Unit 2622
