Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al (2023/0082959) hereinafter, Jeong in view of Tamaki et al (2020/0004071) hereinafter, Tamaki.
In regards to claim 1, Jeong teaches (Original) a display device, comprising a plurality of display panels mutually spliced (fig. 1 displays 10-3, 10-4, etc).,
A display device includes a display area which displays an image, and a non-display area disposed around the display area and including a pad part. The display area includes pixels of a first pixel row which are pixels arranged in a first direction along the first pixel row, pixels of a second pixel row, which are pixels arranged in the first direction along the second pixel row next to the first pixel row, and pixel circuits of a first circuit row which are pixel circuits arranged in the first direction along the first circuit row, where the pixel circuits of the first circuit row are electrically connected to the pixels of the first pixel row, respectively. The first pixel row and the first circuit row are spaced apart from each other with the second pixel row interposed therebetween.
wherein each of a plurality of display panels comprises (fig. 13 display):
a base substrate (fig. 13 (SUB)), comprising a display area (fig. 13 DA) and a peripheral area (fig. 13 (NDA));
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an edge pixel group, comprising a plurality of edge sub-pixels (fig. 2 subpixels along edge); and
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a row driving circuit ([0023] gate driver), comprising a plurality of gate driving units ([0025] stages fig. 9) and a plurality of light emitting control units (fig 7 DL., CKL VL, etc to fig. 2 PC1, PC2, P3, etc).
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wherein the display area comprises a middle display area and an edge display area located at a side of the middle display area close to the peripheral area (fig. 1 (middle section)), and
Jeong fails to teach each of a plurality of edge sub-pixels comprises an edge pixel driving circuit and an anode connected with the edge pixel driving circuit;
However, Tamaki teaches each of a plurality of edge sub-pixels comprises an edge pixel driving circuit and an anode connected with the edge pixel driving circuit;(abstract)(fig. 2 (PE1 and Anode [0063])Examiner notes the connecting anode of the PE is above the gate driver circuit).
According to one embodiment, a display device includes a driver, a first pixel circuit disposed apart from the driver in plan view but electrically connected to the driver, a second pixel circuit separated further from the driver than the first pixel circuit in plan view but electrically connected to the driver, a first pixel electrode overlapping the driver in plan view, a second pixel electrode overlapping the first pixel circuit in plan view, a first relay line electrically connecting the first pixel circuit and the first pixel electrode to each other, and a second relay line electrically connecting the second pixel circuit and the second pixel electrode to each other.
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It would have been obvious to one of ordinary skill in the art to modify the teachings of Jeong to further include each of a plurality of edge sub-pixels comprises an edge pixel driving circuit and an anode connected with the edge pixel driving circuit as taught by Tamaki to make the bezel narrower [0003]
Therefore, Jeong in view of Tamaki teaches the edge pixel group is located in the edge display area, and the row driving circuit is at least partially located in the edge display arca and overlaps with the anode of at least one edge among a plurality of edge sub-pixels in the edge pixel group, ;(abstract)(fig. 2 (PE1 and Anode [0063, 0041-0056] Tamaki
a plurality of the edge pixel driving circuits of a plurality of edge sub-pixels in the edge pixel group are arranged in a first direction (fig. 14 (Pc)) and fig. 2 PC first direction is X direction)Jeong , the plurality of gate driving units and the plurality of light emitting control units are arranged in a second direction, and the second direction intersects with the first direction (fig. 9 and fig. 11 stg1, stg2, etc in Y direction) (fig. 3 ACL1 Jeong),
the display panel further includes a clock signal line(fig. 4 CKL), a start line ([146] initialization stage)Jeong, a first power line (fig. 4 VL) and (fig. 14 VDL1) Jeong and a second power line that are configured to drive the row driving circuit (fig. 14 VDL2) [201-203] Jeong, and
the plurality of gate driving units and the plurality of light emitting control units share at least one selected from a group consisting of the clock signal line, the start line, the first power line and the second power line (fig. 4 gate driving stages, and traces, CKL, etc) Jeong.
In regards to claim 18, Jeong teaches (Original) a display panel, comprising: a base substrate (fig. 13 (SUB)), comprising a display area (fig. 13 DA) and a peripheral area (fig. 13 (NDA));
an edge pixel group, comprising a plurality of edge sub-pixels (fig. 2 subpixels along edge); and
a row driving circuit ([0023] gate driver), comprising a plurality of gate driving units ([0025] stages fig. 9) and a plurality of light emitting control units (fig 7 DL., CKL VL, etc).
wherein the display area comprises a middle display area and an edge display area located at
a side of the middle display area close to the peripheral area (fig. 1 (middle section)), and
Jeong fails to teach each of a plurality of edge sub-pixels comprises an edge pixel driving circuit and an anode connected with the edge pixel driving circuit;
However, Tamaki teaches each of a plurality of edge sub-pixels comprises an edge pixel driving circuit and an anode connected with the edge pixel driving circuit;(abstract)(fig. 2 (PE1 and Anode [0063])Examiner notes the connecting anode of the PE is above the gate driver circuit).
It would have been obvious to one of ordinary skill in the art to modify the teachings of Jeong to further include each of a plurality of edge sub-pixels comprises an edge pixel driving circuit and an anode connected with the edge pixel driving circuit as taught by Tamaki in order to make the bezel narrower [0003]
Therefore, Jeong in view of Tamaki teaches the edge pixel group is in the edge display area, and the row driving circuit is at least partially located in the edge display arca and overlaps with the anode of at least one edge sub-pixels in the edge pixel group, ;(abstract)(fig. 2 (PE1 and Anode [0063, 0041-0056] Tamaki
a plurality of the edge pixel driving circuits of a plurality of edge sub-pixels in the edge pixel group are arranged in a first direction (fig. 14 (Pc)) and fig. 2 PC first direction is X direction)Jeong , the plurality of gate driving units and the plurality of light emitting control units are arranged in a second direction, and the second direction perpendicular with the first direction (fig. 9 and fig. 11 stg1, stg2, etc in Y direction) (fig. 3 ACL1 Jeong),
the display panel further includes a clock signal line(fig. 4 CKL), a start line ([146] initialization stage)Jeong, a first power line (fig. 4 VL) and (fig. 14 VDL1) Jeong and a second power line that are configured to drive the row driving circuit (fig. 14 VDL2) [201-203] Jeong, and
the plurality of gate driving units and the plurality of light emitting control units share at least one selected from a group consisting of the clock signal line, the start line, the first power line and the second power line (fig. 4 gate driving stages, and traces, CKL, etc) Jeong.
In regards to claim 16, Jeong in view of Tamaki teaches (Currently amended) the display device according to any one of claims 1 15 claim 1, wherein the row driving circuit is located at a side of a plurality of edge pixel driving circuits in the edge pixel group away from the middle display area. (fig. 1 Cr1 on edge) Tamaki.
In regards to claim 17, Jeong in view of Tamaki teaches (Currently amended) The display device according to any one of claims 1 16 claim 1, wherein each edge sub-pixel further comprises: an edge organic light emitting layer, located at a side of the anode away from the base substrate; and a cathode, located at a side of the edge organic light emitting layer away from the base substrate [203] (fig. 13 ACL and cathode of fig. 14 ED) away from sub) Jeong.
Allowable Subject Matter
Claims 2-15, 19-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/GRANT SITTA/Primary Examiner, Art Unit 2622
