DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-8, 14, 17, 20, and 22-24 are rejected under 35 U.S.C. 103 as being unpatentable over Long et al (US 2021/0005144; hereinafter Long), in view of Li et al (US 2021/0225253; hereinafter Li).
• Regarding claims 1 and 23, Long discloses a driving circuit and associated method (figure 5), comprising:
a first node control circuit (element M1 in figure 5 and ¶s 93-97),
a first control circuit (element M3 in figure 5 and ¶s 93-97),
an output node control circuit (element M7 in figure 5 and ¶s 93-97),
a first energy storage circuit (element C2 in figure 5 and ¶ 96) and
an output circuit (elements M9 and M10 in figure 5 and ¶s 93-97);
the first node control circuit is electrically connected to a first node and is configured to control a potential of the first node (¶s 93-97);
the first control circuit is electrically connected to a setting control end, a first voltage line and a second node, respectively, and is configured to control the connection or disconnection between the second node and the first voltage line under the control of a setting control signal provided by the setting control end (¶s 93-97);
the output node control circuit is electrically connected to the first clock signal line, the second node and a first output node, respectively, and is configured to control the connection or disconnection between the second node and the first output node under the control of the first clock signal (¶s 93-97);
the first energy storage circuit is electrically connected to a second output node and is configured to store electric energy (¶ 96);
the output circuit is electrically connected to the first output node, the second output node and a driving output end, respectively, and is configured to control the driving output end to output a driving signal under the control of a potential of the first output node and a potential of the second output node (¶s 93-97).
However, Long fails to disclose the additional details of the driving circuit.
In the same field of endeavor, Li discloses a driving circuit (figure 3) comprising:
a first control circuit (element 110 in figure 3 and ¶ 41),
a second control circuit (element 140, specifically, element T13, in figure 3 and ¶ 62),
an output circuit (elements 120, 151, and 152 in figure 3 and ¶s 52-54);
the first control circuit is electrically connected to a setting control end, a first voltage line and a second node, respectively, and is configured to control the connection or disconnection between the second node and the first voltage line under the control of a setting control signal provided by the setting control end (¶ 41);
the second control circuit is electrically connected to a first clock signal line, the second node and a second voltage line, respectively, and is configured to control the connection or disconnection between the second node and the second voltage line under the control of a first clock signal provided by the first clock signal line and a potential of the second node (¶s 62 and 70);
the output circuit is electrically connected to the first output node, the second output node and a driving output end, respectively, and is configured to control the driving output end to output a driving signal under the control of a potential of the first output node and a potential of the second output node (¶s 52-54).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Long according to the teachings of Li, for the purpose of reducing signal noise, power consumption, and current leakage (¶ 94).
• Regarding claims 5-8, 14, 17, 20, 22, and 24, Long, in view of Li, discloses everything claimed, as applied to claim 1. Additionally, Long discloses where:
Claim 5: a first end of the first energy storage circuit is electrically connected to the second output node, and a second end of the first energy storage circuit is electrically connected to the first clock signal line (note the relationship between CB, EM, and C2 in figure 5).
Claim 14: the first energy storage circuit comprises:
a first capacitor (element C2 in figure 5);
a first end of the first capacitor is electrically connected to the second output node, and a second end of the first capacitor is electrically connected to the first clock signal line (note the relationship between CB, EM, and C2 in figure 5).
Claim 6: the driving circuit further comprises:
a third control circuit (element M8 in figure 5 and ¶s 93-97);
or,
the third control circuit is electrically connected to the first node, the first output node and a fourth voltage line respectively, and is configured to control the connection or disconnection between the first output node and the fourth voltage line under the control of the potential of the first node (¶ 97);
the third control circuit comprises a ninth transistor (element M8 in figure 5 and ¶s 93-97);
a gate of the ninth transistor is electrically connected to the second output node, a first pole of the ninth transistor is electrically connected to the fourth voltage line, and a second pole of the ninth transistor is electrically connected to the first output node (element M8 in figure 5 and at least ¶ 97).
Claim 7: the driving circuit further comprises:
a fourth control circuit (elements M4 and M5 in figure 5 and ¶s 93-97);
the fourth control circuit is electrically connected to the first node, a fourth voltage line and the second node, respectively, and is configured to control the connection or disconnection between the second node and the fourth voltage line under the control of the potential of the first node (¶ 96);
the fourth control circuit comprises a fifth transistor (the combination of elements M4 and M5 in figure 5);
a gate of the fifth transistor is electrically connected to the first node, a first pole of the fifth transistor is electrically connected to the fourth voltage line, and a second pole of the fifth transistor is electrically connected to the second node (elements M4 and M5 in figure 5 and at least ¶ 96).
Claim 8: the driving circuit further comprises:
a second energy storage circuit which is electrically connected to the first output node to store electric energy (element C3 in figure 5 and ¶ 95).
Claim 17: the first node control circuit is further electrically connected to an input end, a second node, a second clock signal line, a first clock signal line and a fourth voltage line, respectively, and is configured to control the connection or disconnection between the first node and the input end under the control of a second clock signal provided by the second clock signal line, and control the connection or disconnection between the first node and the fourth voltage line under the control of the first clock signal and the potential of the second node (elements M1, M4, and M5 in figure 5 and ¶s 93-97);
the first node control circuit comprises:
a sixth transistor (element M1 in figure 5),
a seventh transistor (element M4 in figure 5) and
an eighth transistor (element M5 in figure 5);
a gate of the sixth transistor is electrically connected to the second clock signal line, a first pole of the sixth transistor is electrically connected to the input end, and a second pole of the sixth transistor is electrically connected to the first node (element M1 in figure 5 and ¶s 93-97);
a gate of the seventh transistor is electrically connected to the first clock signal line, a first pole of the seventh transistor is electrically connected to the fourth voltage line, and a second pole of the seventh transistor is electrically connected to a first pole of the eighth transistor (element M4 in figure 5 and ¶s 93-97; where the positions of elements M4 and M5 could be switched without altering their functionality);
a gate of the eighth transistor is electrically connected to the second node, and a second pole of the eighth transistor is electrically connected to the first node (element M5 in figure 5 and ¶s 93-97; where the positions of elements M4 and M5 could be switched without altering their functionality).
Claim 20: the output node control circuit comprises a tenth transistor (element M7 in figure 5 and ¶s 93-97);
a gate of the tenth transistor is electrically connected to the first clock signal line, a first pole of the tenth transistor is electrically connected to the second node, and a second pole of the tenth transistor is electrically connected to the first output node (element M7 in figure 5 and ¶s 93-97).
Claim 22: the output circuit comprises:
a twelfth transistor (element M9 in figure 5 and ¶s 93-97) and
a thirteenth transistor (element M10 in figure 5 and ¶s 93-97);
a gate of the twelfth transistor is electrically connected to the first output node, a first pole of the twelfth transistor is electrically connected to a fifth voltage line, and a second pole of the twelfth transistor is electrically connected to the driving output end (element M9 in figure 5 and ¶s 93-97);
a gate of the thirteenth transistor is electrically connected to the second output node, a first pole of the thirteenth transistor is electrically connected to the driving output end, and a second pole of the thirteenth transistor is electrically connected to a sixth voltage line (element M10 in figure 5 and ¶s 93-97).
Claim 24: a display apparatus comprises the driving circuit according to claim 1 (figures 1 and 29).
However, Long fails to disclose the additional details of the driving circuit.
While Long and Li fail to explicitly disclose the particular details of the combination of the first and second transistors, Li discloses the details of the second transistor, as shown below. Additionally, Long discloses a similar structure with respect to elements M4 and M5 in figure 5.
Claim 9: the second control circuit comprises:
a first transistor (element T13 in figure 3, in combination with elements M4 and M5 of Long) and
a second transistor (element T13 in figure 3 and ¶ 62 of Li);
a gate of the first transistor is electrically connected to the second node, a first pole of the first transistor is electrically connected to the second voltage line, and a second pole of the first transistor is electrically connected to a first pole of the second transistor (element T13 in figure 3, in combination with elements M4 and M5 of Long);
a gate of the second transistor is electrically connected to the first clock signal line, and a second pole of the second transistor is electrically connected to the second node (element T13 in figure 3 and ¶ 62 of Li).
Therefore, it would have been obvious to one of ordinary skill in the art to have tried implementing the structure of element M4 and M4 in figure 5 of Long in combination with element T13 in figure 3 of Li as such implementation would have yielded the predictable results of maintaining a particular node at a particular level at a particular time (¶s 94 and 96 of Long) and stabilizing the pull-up and pull-down nodes of a shift register circuit (¶ 62 of Li).
Claims 2, 3, 13, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Long, in view of Li, and further in view of Zheng (US 2020/0265877).
• Regarding claims 2, 3, 13, and 21, Long, in view of Li, discloses everything claimed, as applied to claim 1. Additionally, Long discloses where:
Claim 3: the first node and the second output node are the same node (N1 in figure 5).
However, Long, in view of Li, fails to disclose the additional details of the driving circuit.
In the same field of endeavor, Zheng discloses where:
Claim 2: a first end of the first energy storage circuit is electrically connected to the second output node, and a second end of the first energy storage circuit is electrically connected to the driving output end (element C1 in figure 3 and ¶ 57).
Claim 13: the first energy storage circuit comprises:
a first capacitor (element C1 in figure 3 and ¶ 57);
a first end of the first capacitor is electrically connected to the second output node, and a second end of the first capacitor is electrically connected to the driving output end (element C1 in figure 3 and ¶ 57).
Claim 3: the drive circuit further comprises:
an on-off control circuit (element T2 in figure 3 and ¶ 57);
the first node is electrically connected to the second output node through the on-off control circuit (element T2 in figure 3 and ¶ 57);
a control end of the on-off control circuit is electrically connected to a third voltage line (element T2 in figure 3 and ¶ 57), and
the on-off control circuit is configured to control the connection or disconnection between the first node and the second output node under the control of a third voltage signal provided by the third voltage line (element T2 in figure 3 and ¶ 57).
Claim 21: the driving circuit further comprises an on-off control circuit (element T2 in figure 3 and ¶ 57);
the on-off control circuit comprises an eleventh transistor (element T2 in figure 3 and ¶ 57);
a gate of the eleventh transistor is electrically connected to the third voltage line, a first pole of the eleventh transistor is electrically connected to the first node, and a second pole of the eleventh transistor is electrically connected to the second output node (element T2 in figure 3 and ¶ 57).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Long, as modified by Li, according to the teachings of Zheng, for the purpose of preventing a pull-down node from leaking electricity (¶ 74).
Claims 4 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Long, in view of Li, and further in view of In et al (US 2023/0360573; hereinafter In).
• Regarding claims 4 and 15, Long, in view of Li, discloses everything claimed, as applied to claim 1. However, Long, in view of Lim, fails to disclose the additional details of the driving circuit.
In the same field of endeavor, In discloses where:
Claim 4: the driving circuit further comprises:
an energy storage control circuit (elements C1 and T13 in figure 3);
the energy storage control circuit is electrically connected to the second output node, the first clock signal line and an energy storage node, respectively, and is configured to control the connection or disconnection between the first clock signal line and the energy storage node under the control of the potential of the second output node (elements C1 and T13 in figure 3 and ¶s 122 and 149);
a first end of the first energy storage circuit is electrically connected to the second output node, and a second end of the first energy storage circuit is electrically connected to the energy storage node (elements C1 and T13 in figure 3 and ¶s 122 and 149).
Claim 15: the first energy storage circuit comprises a first capacitor (element C1 in figure 3 and ¶s 122 and 149), and
the energy storage control circuit comprises a fourth transistor (element T13 in figure 3 and ¶s 122 and 149);
a first end of the first capacitor is electrically connected to the second output node (element C1 in figure 3 and ¶s 122 and 149); and
a second end of the first capacitor is electrically connected to the energy storage node (element C1 in figure 3 and ¶s 122 and 149);
a gate of the fourth transistor is electrically connected to the second output node, a first pole of the fourth transistor is electrically connected to the energy storage node, and a second pole of the fourth transistor is electrically connected to the first clock signal line (element T13 in figure 3 and ¶s 122 and 149).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Long, as modified by Li, according to the teachings of In, for the purpose of boosting a transistor turn on voltage to ensure the transistor is completely turned on (¶ 149).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Long, in view of Li, and further in view of Takasugi (US 2019/0180691).
• Regarding claim 10, Long, in view of Li, discloses everything claimed, as applied to claim 1. Additionally, Long discloses where:
Claim 10: the first control circuit comprises:
a third transistor (element M3 in figure 5 and ¶s 93-97); and
the setting control end is an input end (element M3 in figure 5);
a gate of the third transistor is electrically connected to the input end, a first pole of the third transistor is electrically connected to the first voltage line, and a second pole of the third transistor is electrically connected to the second node (element M3 in figure 5).
However, Long fails to disclose the additional details of the driving circuit.
In the same field of endeavor, Takasugi discloses where:
Claim 10: the third transistor is an oxide transistor (¶s 37 and 38).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Long, as modified by Li, according to the teachings of Takasugi, for the purpose of realizing a narrow bezel (¶ 11).
Allowable Subject Matter
Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record, either alone or in combination, fails to teach or fairly suggest, in claim 11, where “the first output node is electrically connected to an adjacent next-stage inverting input end, and the driving output end is electrically connected to an adjacent next-stage input end”, in combination with all the remaining limitations in the claim and all the limitations in claim 1.
Closing Remarks/Comments
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN DANIELSEN whose telephone number is (571)272-4248. The examiner can normally be reached Monday-Friday 9:00 AM to 5:00 PM Eastern Time.
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/NATHAN DANIELSEN/Primary Examiner, Art Unit 2622
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