DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Interpretation
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: light-emitting unit(s) in claims 2 and 7.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Examiner is interpreting the light-emitting unit(s) to include at least a light emitting diode based on at least Fig. 1, item L.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 26 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ryoo et al. (USPN 2023/0189605).
With respect to claim 1, Ryoo teaches a display panel (Figs. 1-19B), comprising a plurality of pixel driving circuits (Figs. 1-19B. At least Figs. 2 and 14), wherein the pixel driving circuit comprises a driving transistor and a fourth transistor, the fourth transistor has a first terminal connected to a data line, a second terminal connected to a first terminal of the driving transistor, and a gate connected to a first gate line (Figs. 1-19B. At least Fig. 14, items DRT and T4. Examiner notes a reasonably broad interpretation of the term “connected” includes indirect connection), wherein
the plurality of pixel driving circuits comprises a first pixel driving circuit and a second pixel driving circuit (Figs. 1-19B. At least Fig. 14, items SP1 and SP2);
a capacitance formed by the first gate line and an equipotential structure of a gate of the driving transistor in the first pixel driving circuit is C1, and a capacitance formed by the first gate line and the equipotential structure of the gate of the driving transistor in the second pixel driving circuit is C2, where C1 is not equal to C2 (Figs. 1-19B. At least Fig. 14 and paragraphs [0367]-[0390] teach first/second pixel driving circuits with a capacitance difference from the gate line to the gate of the driving transistor. At least paragraphs [0023] and [0386] teach capacitance relationships as claimed such that C1 is not equal to C2).
Claim 26, a display device, corresponds to and is analyzed and rejected for substantially the same reasons as the display panel of Claim 1, discussed above.
Allowable Subject Matter
Claims 2-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record teaches a display with a capacitance formed by a first gate line and an equipotential structure of a first pixel driving transistor not being equal to a capacitance formed by a first gate line and an equipotential structure of a second pixel driving transistor (see Ryoo et al. USPN 2023/0189605).
However, the prior art of record fails to teach or suggest Applicant’s specifically claimed
“display panel according to claim 1, further comprising a plurality of light-emitting units, wherein the plurality of light-emitting units comprises a first light-emitting unit and a second light-emitting unit;
the first pixel driving circuit is used to drive the first light-emitting unit, and the second pixel driving circuit is used to drive the second light-emitting unit;
with a same driving current, a brightness of the first light-emitting unit is less than a brightness of the second light-emitting unit, and C1 is less than C2” (claim 2 – emphasis added); and
“display panel according to claim 1, discussed above, wherein the plurality of pixel driving circuits is arranged along the first direction and the second direction, and the display panel further comprises:
a base substrate;
a fourth conductive layer located on a side of the base substrate, wherein the fourth conductive layer comprises a plurality of first power line segments, the first power line segments are arranged corresponding to the pixel driving circuits, orthographic projections of the plurality of first power line segments on the base substrate are arranged along the first direction and the second direction and extend along the second direction, the first direction and the second direction intersect, and the first power line segments are connected to a stable voltage source;
a fifth conductive layer located on a side of the fourth conductive layer away from the base substrate, wherein the fifth conductive layer comprises the data line, and an orthographic projection of the data line on the base substrate extends along the second direction” (claim 8);
“display panel according to claim 1, wherein
the first terminal of the driving transistor is connected to a power line, and the display panel further comprises:
a base substrate;
a second conductive portion, the second conductive portion being connected to the gate of the driving transistor;
a fifth conductive layer located on a side of the base substrate, wherein the fifth conductive layer comprises the power line, and an orthographic projection of the power line on the base substrate covers an orthographic projection of the second conductive portion on the base substrate” (claim 16); and
“display panel according to claim 1, wherein the first terminal of the driving transistor is connected to a power line, and the display panel further comprises:
a base substrate;
a fifth conductive layer located on a side of the base substrate, wherein the fifth conductive layer comprises the power line and the data line, and an orthographic projection of the power line on the base substrate and an orthographic projection of the data line on the base substrate
extend along a second direction;
an electrode layer comprising a plurality of electrode portions, wherein an orthographic projection of the electrode portion on the base substrate overlaps with the orthographic projection of the power line on the base substrate and the orthographic projection of the data
line on the base substrate;
a pixel definition layer located on a side of the electrode layer away from the base substrate,
wherein a pixel opening used for forming a light-emitting unit is provided on the pixel definition layer, and an orthographic projection of the pixel opening on the base substrate coincides with the orthographic projection of the electrode portion on the base substrate” (claim 17).
Claims 3-7, 9-14 and 18-19 are dependent on claims 2, 8 and 17, respectively, and allowable for substantially the same reasons, discussed above.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTONIO J XAVIER whose telephone number is (571)270-7688. The examiner can normally be reached on M-F 830am-5pm PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, PATRICK EDOUARD can be reached on 571-272-7603. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTONIO XAVIER/
Primary Examiner, Art Unit 2622
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