DETAILED ACTION
This is a first office action in response to application No. 18/995,743 filed on 01/16/2025, in which claims 1 - 20 are presented for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5 - 8, 11 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by WU “US 2021/0225217”.
Re-claim 1, WU teaches a display panel, (fig. 2 and par. [0026] display panel) having a display area (fig. 2 and par. [0026] display region (or called an active area, AA) 20) and a peripheral area outside the display area, (par. [0026] non-display region) wherein the display area is provided with pixel circuits distributed along a row direction and a column direction; (par. [0026] The display region 20 further includes a plurality of pixel units 23 used for displaying images. The pixel units 23 are formed by interlacing the scan lines 21 and the data lines) the peripheral area is provided with at least one peripheral circuit distributed along the row direction with the display area; (fig. 2 and par. [0029] a test line 25 disposed in the non-display region in the row direction) the at least one peripheral circuit comprises a plurality of circuit groups spaced apart along the column direction, a trigger signal line, and at least one test line; (pars. [0027] - [0028] first group: fig. 2; 28 a virtual GOA circuit region 1 and GOA circuit units 24 G1 to Gk; second group spaced apart from the first group in the column direction fig. 2; 28 virtual GOA circuit region n/k and GOA circuit units 24 Gn-k+1 to Gn; and pars. [0039] Please continue to FIG. 2. The display panel further includes a plurality of virtual GOA circuit regions 28. The virtual GOA circuit regions 28 are disposed corresponding to the groups of GOA circuit units. The number of the virtual GOA circuit regions 28 is equal to the number of the groups of GOA electric circuits. The virtual GOA circuit regions 28 has circuits with a function as the same as the GOA circuit units 24. [0040] In one embodiment, the virtual GOA circuit regions 28 may have a circuit corresponding to one GOA circuit unit 24. When one invalid GOA circuit unit 24 exists in a certain group of GOA circuit units, the one invalid GOA circuit unit 24 is replaced with a circuit in the virtual GOA circuit region 28 disposed corresponding to said group. When two or more than two invalid GOA circuit units 24 exist in a certain group of GOA circuit units, one of the invalid GOA electric circuits 24 is replaced with a circuit in the virtual GOA circuit region 28 disposed corresponding to said group, and the other ones of the invalid GOA circuit units 24 are replaced with circuits in the virtual GOA circuit regions 28 disposed corresponding to other groups. That is, the invalid GOA circuit units 24 are replaced by the virtual GOA circuit regions 28 corresponding to the groups different from the groups of the invalid GOA circuit units) one of the circuit groups comprises a plurality of shift registers cascaded along the column direction; (As shown in fig. 2 and mentioned in the above limitations fig. 2; G1-Gk GOA circuit units 24 of the above-mentioned first group, and Gn-k+1 to Gn GOA circuit units 24 of the above-mentioned second group) any row of the pixel circuits is connected to at least one of the shift registers through a scanning line; (fig. 2 and par. [0027] The GOA circuit units 24 are disposed in the non-display region and are connected to the scan lines 21 of the display region 20.)
a first shift register of each of the circuit groups is connected to one trigger signal line, and there are different trigger signal lines connected to different circuit groups; (As shown in fig. 2 and mentioned in the above limitations the input signal line of the first GOA circuit G1 of the first group and the input signal line of the first GOA circuit Gn- k+1 of the second group which is connected to an output of the previous GOA circuit Gn-k- can be equated to the claimed trigger signal lines of the first and second groups, respectively, and are distinct lines) a last shift register of at least one of the circuit groups is connected to one test line; (see fig. 2 the last GOA circuit Gk of the first group and the last GOA circuit Gn of the second group are connected to a test line equated to the line formed by the test line 25 and the connecting lines 26) at least a part of the test line is located between the shift register and the pixel circuit, and a length of the part of the test line located between the shift register and the pixel circuit in the column direction is smaller than a length of the peripheral circuit in the column direction. (see annotated fig. 2 below a part of the connecting line 26 extending in the column direction (L1), positioned between the GOA circuitry and the pixels (20), is shorter than the length of the GOA circuitry in the column direction)
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Re-claim 5, WU teaches wherein the at least one test line extends at least partially to a side, away from the pixel circuit, of the shift register connected to the test line. (see fig. 2; e.g., the GOA circuitry positioned on the left side of the panel 20: the connecting lines 26 of said GOA circuitry extend away from the panel 20 towards a left side of the GOA circuitry)
Re-claim 6, WU teaches wherein the at least one test line comprises a first connection segment, (fig. 2; portion of lines 26 which extends in the column direction) a transition segment, (fig. 2; portion of lines 26 which extends in the row direction) and a second connection segment (fig. 2; test line 25) sequentially connected; the first connection segment is located at a side of the shift register away from the pixel circuit and is connected to the shift register; the transition segment extends along the row direction; and the second connection segment is located at the side of the shift register away from the pixel circuit. (fig. 2; locations for the portions of line 26 and line 25 with respect to the panel 20 and the GOA circuitry)
Re-claim 7, WU teaches wherein the transition segment of the test line is located between the shift register and a first shift register of an adjacent circuit group. (fig. 2; the portion of line 26 which extends in the row direction and which is connected to Gk is positioned between Gk and Gn-k+1)
Re-claim 8, WU teaches wherein at least a part of the second connection segment extends linearly along the column direction, and a length of the second connection segment is not less than the length of the peripheral circuit in the column direction. (fig. 2; the test line 25 extends in the column direction and is longer than a length of the GOA circuitry in the column direction (L1))
Re-claim 11, WU teaches wherein the second connection segment is located at a side of the trigger signal line away from the pixel circuit. (fig. 2; line 25 is located on the left of the input signal line, i.e. on a side of the input signal line away from the display panel 20)
Re-claim 20, WU teaches a display device comprising the display panel according to claim 1. (see rejection of claim 1 above)
4. Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over WU “US 2021/0225217” in view of Shu “US 2024/0419271”.
Re-claim 19, WU teaches all the limitations of claim 1 but does not explicitly teach wherein the display panel is divided into a plurality of display portions along the column direction, and one of the display portions comprises one circuit group; two adjacent display portions are bendable relative to each other.
However, Shu teaches wherein the display panel is divided into a plurality of display portions (figs. 2-3) along the column direction, and one of the display portions comprises one circuit group; two adjacent display portions (fig. 3; 31 & 32) are bendable relative to each other. (figs. 2-3 and par. [0051] For example, as shown in FIG. 2 and FIG. 3, the display panel of the touchscreen may include a first touch zone 31 and a second touch zone 32. When the touchscreen is folded, the first touch zone 31 and the second touch zone 32 may be located in different planes. The touchscreen in FIG. 3 is folded inwards, so that the first touch zone 31 and the second touch zone 32 are opposite to each other after the touchscreen is completely folded. And par. [0070])
It would have been obvious to one of ordinary skill in the art before the effective filing date to further modify the invention of WU with the teaching of Shu to improve touch performance of the touchscreen. (par. [0073])
Allowability Subject matter
5. Claims 2 - 4, 9 - 10 and 12 - 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Contact Information
6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Sosina Abebe whose telephone number is (571) 270-7929. The examiner can normally be reached on Mon-Friday from 9:00-5:30 If attempts to reach the examiner by telephone are unsuccessful, the examiner's Supervisor, Temesghen Ghebretinsae can be reached on (571) 272-3017. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/S.A/Examiner, Art Unit 2626
/TEMESGHEN GHEBRETINSAE/Supervisory Patent Examiner, Art Unit 2626 6/26/26B
Prosecution Insights