DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/10/2025 has been placed in record and considered by the examiner.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9, 11-17, 22-24, and 27 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Referring to claim 1 recites the limitations “the driving circuit”, "the input terminal”, “the pull-up node”, “the potential”, “the input signal”, “the first reset terminal”, “the first voltage terminal”, “the first reset signal”, “the first voltage signal”, “the first pull-down node”, “the second voltage terminal”, “the second voltage signal”, and “the voltage value”.
There are insufficient antecedent basis for these limitations in the claims (see claim 1 below).
1. (suggest to amend) A driving module, comprising multiple stages of driving circuits;
[the] each driving circuit comprises an input circuit, a first reset circuit, and a first pull-down noise reduction circuit;
the input circuit is electrically connected to [the] an input terminal and [the] a pull-up node, respectively, and is configured to control [the] a potential of the pull-up node based on [the] an input signal provided by the input terminal;
the first reset circuit is electrically connected to [the] a first reset terminal, the pull-up node, and [the] a first voltage terminal, respectively, and is configured to, under the control of [the] a first reset signal provided by the first reset terminal, input [the] a first voltage signal from the first voltage terminal to the pull-up node;
the first pull-down noise reduction circuit is electrically connected to [the] a first pull-down node, the pull-up node, and [the] a second voltage terminal, and is configured to, under the control of the potential of the first pull-down node, input [the] a second voltage signal provided by the second voltage terminal to the pull-up node;
[the] a voltage value of the first voltage signal is greater than [the] a voltage value of the second voltage signal.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 7, 9, 22, and 27 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xue et al. (US 20210366350 Xue).
Referring to claim 1, Xue discloses a driving module ([0029]; FIG. 1 is a schematic structural diagram of a shift register circuit according to some embodiments of the present disclosure. As shown in FIG. 1, the shift register circuit includes a shift output circuit 10, N driving output circuits 20, and a pull-down circuit 30, wherein the N can be an integer greater than 1.), comprising multiple stages of driving circuits ([0029]; FIG. 1 is a schematic structural diagram of a shift register circuit according to some embodiments of the present disclosure. As shown in FIG. 1, the shift register circuit includes a shift output circuit 10, N driving output circuits 20, and a pull-down circuit 30, wherein the N can be an integer greater than 1.);
each driving circuit comprises an input circuit (Fig. 3; 101), a first reset circuit (Fig. 3; 103), and a first pull-down noise reduction circuit (Fig. 3; 105);
the input circuit (Fig. 3; 101) is electrically connected to an input terminal (Fig. 3; IN) and a pull-up node (Fig. 3; PU), respectively, and is configured to control a potential of the pull-up node (Fig. 3; PU) based on an input signal provided by the input terminal (Fig. 3; IN) ([0033]; In some embodiments, the shift output circuit 10 is provided with a pull-up node PU. The shift output circuit 10 can charge the pull-up node PU under a control of the input signal terminal IN. When the potential of the pull-up node PU is an effective potential, the control clock signal terminal CK is electrically coupled to the shill output terminal OUT, so that a control clock signal is inputted to the shift output terminal OUT. Meanwhile, each driving clock signal terminal is electrically coupled to a corresponding driving output terminal, and the driving clock signals are inputted to the corresponding driving output terminals respectively…. and [0051]; The input sub-circuit 101 is respectively coupled to the input signal terminal IN, the first direct-current power source terminal VS, and the pull-up node PU. The input sub-circuit 101 is configured to input a first direct-current power source signal from the first direct-current power source terminal VS to the pull-up node PU under a control of the input signal. The potential of the first direct-current power supply signal can be an effective potential.);
the first reset circuit (Fig. 3; 103) is electrically connected to a first reset terminal (Fig. RST), the pull-up node (Fig. 3; PU), and a first voltage terminal (Fig. 3; VD), respectively, and is configured to, under the control of a first reset signal provided by the first reset terminal (Fig. RST), input a first voltage signal from the first voltage terminal to the pull-up node (Fig. 3; PU) ([0055]; In some embodiments, the reset sub-circuit 103 is respectively coupled to the reset signal terminal RST, second direct-current power supply terminal VD, and the pull-up node PU. The reset sub-circuit 103 is configured to input a second direct-current power source signal from the second direct-current power source terminal VD to the pull-up node PU under a control of the reset signal. The potential of the second direct-current power supply signal is an ineffective potential.);
the first pull-down noise reduction circuit (Fig. 3; 105) is electrically connected to a first pull-down node (Fig. 3; PD), the pull-up node (Fig. 3; PU), and a second voltage terminal (Fig. 3; VGL), and is configured to, under the control of the potential of the first pull-down node (Fig. 3; PD), input a second voltage signal provided by the second voltage terminal (Fig. 3; VGL) to the pull-up node (Fig. 3; PU) ([0059]; The noise reduction sub-circuit 105 is respectively coupled to the pull-down node PD, the pull-down power supply terminal VGL, the pull-up node PU, and the shift output terminal OUT. The noise reduction sub-circuit 105 is configured to input pull-down power supply signal to the pull-up node PU and the shift output terminal OUT respectively under a control of the pull-down node PD.);
a voltage value of the first voltage signal is greater than a voltage value of the second voltage signal (Fig. 3; a voltage value of the first voltage signal VD is greater than a voltage value of the second voltage signal VGL).
Referring to claim 7, Xue discloses wherein the driving circuit further comprises a first noise reduction circuit (Fig.3-4; noise reduction sub-circuit 105);
the first noise reduction circuit is electrically connected to the first noise reduction control terminal, the first pull-down node, and the second voltage terminal, respectively, and is configured to, under the control of the first noise reduction control signal provided by the first noise reduction control terminal, control the conduction or disconnection between the first pull-down node and the second voltage terminal ([0059]; The noise reduction sub-circuit 105 is respectively coupled to the pull-down node PD, the pull-down power supply terminal VGL, the pull-up node PU, and the shift output terminal OUT. The noise reduction sub-circuit 105 is configured to input pull-down power supply signal to the pull-up node PU and the shift output terminal OUT respectively under a control of the pull-down node PD.);
the first noise reduction control terminal is either the input terminal of the adjacent m-stage preceding driving circuit or the first reset terminal ([0015]; Another example of the present disclosure is a gate driving circuit. The gate driving circuit may include at least two cascaded shill register circuits. Each of the at least two cascaded shift register circuits may be the shift register circuit according to one embodiment of the present disclosure. A shift output terminal of a shift register circuit of each stage may be respectively coupled to an input signal terminal of a shift register circuit of a next stage, and a reset signal terminal of a shill register circuit of a previous stage.).
Referring to claim 9, Xue discloses wherein the first reset circuit (Fig. 4; 103) comprises a first transistor (Fig. 4; M6);
the gate of the first transistor is electrically connected to the first reset terminal (Fig. 4; gate of M6 is connected to reset terminal RST), the first terminal of the first transistor is electrically connected to the pull-up node, and the second terminal of the first transistor is electrically connected to the first voltage terminal (Fig. 4; the first and second terminals of M6 are connected to PU and VD).
Referring to claim 22, Xue discloses comprising:
controlling, by the input circuit (Fig. 3; 101), the potential of the pull-up node (Fig. 3; PU) based on the input signal provided by the input terminal (Fig. 3; IN) ([0033]; In some embodiments, the shift output circuit 10 is provided with a pull-up node PU. The shift output circuit 10 can charge the pull-up node PU under a control of the input signal terminal IN. When the potential of the pull-up node PU is an effective potential, the control clock signal terminal CK is electrically coupled to the shill output terminal OUT, so that a control clock signal is inputted to the shift output terminal OUT. Meanwhile, each driving clock signal terminal is electrically coupled to a corresponding driving output terminal, and the driving clock signals are inputted to the corresponding
driving output terminals respectively…. and [0051]; The input sub-circuit 101 is
respectively coupled to the input signal terminal IN, the first direct-current power source
terminal VS, and the pull-up node PU. The input sub-circuit 101 is configured to input a
first direct-current power source signal from the first direct-current power source terminal VS to the pull-up node PU under a control of the input signal. The potential of the first direct-current power supply signal can be an effective potential.);
inputting, by the first reset circuit (Fig. 3; 103), a first voltage signal to the pull-up node (Fig. 3; PU) under the control of the first reset signal provided by the first reset terminal (Fig.
RST) ([0055]; In some embodiments, the reset sub-circuit 103 is respectively coupled to the reset signal terminal RST, second direct-current power supply terminal VD, and the pull up node PU. The reset sub-circuit 103 is configured to input a second direct-current power source signal from the second direct-current power source terminal VD to the pullup node PU under a control of the reset signal. The potential of the second direct-current power supply signal is an ineffective potential.);
inputting, by the first pull-down noise reduction circuit (Fig. 3; 105), a second voltage signal to the pull-up node (Fig. 3; PU) under the control of the first pull-down node (Fig. 3; PD) ([0059]; The noise reduction sub-circuit 105 is respectively coupled to the pull-down node PD, the pull-down power supply terminal VGL, the pull-up node PU, and the shift output terminal OUT. The noise reduction sub-circuit 105 is configured to input pull-down power supply signal to the pull-up node PU and the shift output terminal OUT respectively under a control of the pull-down node PD.);
wherein the voltage value of the first voltage signal is greater than the voltage value of the second voltage signal (Fig. 3; a voltage value of the first voltage signal VD is greater than a voltage value of the second voltage signal VGL).
Referring to claim 27, Xue discloses a display device, comprising the driving module of claim 1 ([0016]; Another example of the present disclosure is a display apparatus. The display apparatus may include a display panel and the gate driving circuit according to one embodiment of the present disclosure. The display panel may include a plurality of gate lines. Each stage of shift register circuit in the gate drive circuit may include N driving output terminals, and each of the driving output terminal may be coupled to one of the plurality of the gate lines in the display panel respectively.).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Xue et al. (US 20210366350 Xue) in view Feng (CN 111402774 A hereinafter Feng).
Referring to claim 6, Xue as applied above does not specifically disclose wherein the driving circuit further comprises a second pull-down noise reduction circuit;
the second pull-down noise reduction circuit is electrically connected to the second pull- down node, the pull-up node, and the second voltage terminal, respectively, and is configured to, under the control of the second pull-down node, input the second voltage signal provided by the second voltage terminal to the pull-up node.
In an analogous art, Feng discloses wherein the driving circuit further comprises a second pull-down noise reduction circuit (Fig. 2; second noise reduction circuit 52);
the second pull-down noise reduction circuit (Fig. 2; second noise reduction circuit 52) is electrically connected to the second pull-down node (Fig. 2; PD2), the pull-up node (Fig. 2; PU), and the second voltage terminal (Fig. 3; VSS1), respectively, and is configured to, under the control of the second pull-down node (Fig. 2; PD2), input the second voltage signal provided by the second voltage terminal (Fig. 3; VSS1) to the pull-up node (Fig. 2; PU) (Feng- see highlighted section; It can be understood that, when the second voltage terminal VDDE-IO provides an effective level signal, a first voltage terminal VDDO provides the invalid level signal, in the input stage. the second control sub-circuit 51 response to an effective level signal of effective level signal input terminal Input and pull-up node PU, the second pull node PD2 to pull down, the reset stage and a noise reduction stage, the second control sub-circuit 51 response to an effective level signal to the second voltage terminal VDDE-IO, the second pull node PD2 to be charged; the second noise reduction circuit 52 response to an effective level signal of the second pull-down node PD2, upper pull node PU, shift signal, output end of the OC and the scanning signal output terminal Output for noise reduction, the second gating unit 53 response to an effective level signal to the second voltage terminal VDDE-IO, the first pull-down node PD1 to pull down.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the technique of Feng to the system of Xue in order to replace of the gate drive IC, so can effectively reduce the size of the peripheral area, which is good for narrow frame.
Claim Objections
Claims 2-5, 8, 11-17, and 23-24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Referring to claim 2, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitation “wherein the driving circuit further comprises a second reset circuit;
the second reset circuit is electrically connected to the first pull-down node, the pull-up node of the adjacent m-stage preceding driving circuit, and the second voltage terminal, respectively, and is configured to, under the control of the potential of the first pull-down node, control the conduction or disconnection between the pull-up node of the adjacent m-stage preceding driving circuit and the second voltage terminal;
m is a positive integer”.
Referring to claims 4,11,13 are objected upon dependent on the claim 2.
Referring to claim 3, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitation “wherein the driving circuit further comprises a second reset circuit;
the second reset circuit is electrically connected to the first pull-down node, the pull-up node, and the second voltage terminal, respectively, and is configured to, under the control of the potential of the first pull-down node, control the connection or disconnection between the pull-up node and the second voltage terminal”.
Referring to claims 5,12,14 are objected upon dependent on the claim 3.
Referring to claim 8, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitation “wherein the driving circuit further comprises a second noise reduction circuit;
the second noise reduction circuit is electrically connected to the second noise reduction control terminal, the second pull-down node, and the second voltage terminal, respectively, and is configured to, under the control of the second noise reduction control signal provided by the second noise reduction control terminal, control the conduction or disconnection between the second pull-down node and the second voltage terminal;
the second noise reduction control terminal is either the input terminal of the adjacent m- stage preceding driving circuit or the first reset terminal; m is a positive integer”.
Referring to claim 16 is objected upon dependent on the claim 8.
Referring to claim 15, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitation “wherein the first noise reduction circuit comprises a fourth transistor:
the gate of the fourth transistor is electrically connected to the first noise reduction control terminal, the first terminal of the fourth transistor is electrically connected to the first pull-down node, and the second terminal of the fourth transistor is electrically connected to the second voltage terminal”.
Referring to claim 17, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitation “wherein the driving circuit further comprises a driving signal output terminal and a drive reset circuit:
the drive reset circuit is electrically connected to the pull-down node, the driving signal output terminal, and the first voltage terminal, and is configured to, under the control of the potential of the pull-down node, control the conduction or disconnection between the driving signal output terminal and the first voltage terminal; or,
the drive reset circuit is electrically connected to the pull-down node, the driving signal output terminal, and the third voltage terminal, and is configured to, under the control of the potential of the pull-down node, control the conduction or disconnection between the driving signal output terminal and the third voltage terminal; the third voltage terminal is different from the first voltage terminal”.
Referring to claim 23, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitation “wherein the driving circuits in the driving module further comprise a second reset circuit, a driving output circuit, and an energy storage circuit;
the driving cycle comprises a first stage, a second stage, a third stage, a fourth stage, and a fifth stage, and the driving method comprises:
during the first stage, the input terminal provides an effective input signal, and the input circuit controls the pull-up node potential for the current stage to reach a first potential based on the input signal;
during the second stage, the driving output circuit supplies a first clock signal to the driving signal output terminal under the control of the potential at the pull-up node, the potential of the first clock signal is a second potential, and the energy storage circuit bootstraps the potential of the current-stage pull-up node;
during the third stage, the potential of the first clock signal falls from the second potential to a third potential, the driving output circuit supplies the first clock signal to the driving signal output terminal under the control of the potential at the pull-up node, as the potential of the first clock signal falls, the energy storage circuit pulls down the potential of the current-stage pull-up node;
during the fourth stage, under the control of the first reset signal, the first reset circuit connects the pull-up node to the first voltage terminal;
during the fifth stage, the second reset circuit in the subsequent m-stage driving circuits connects the pull-up node to the second voltage terminal under the control of the potential of the first pull-down node in the subsequent m-stage driving circuits;
m is a positive integer”.
Referring to claim 24 is objected upon dependent on the claim 23.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wang et al. (US 2019/0139475) disclose a shift register circuit, and driving method thereof, gate drive circuit and display device.
MI et al. (US 2021/0366351) disclose a shift register unit, gate driving circuit and driving method thereof, display device.
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/SCOTT D AU/Examiner, Art Unit 2624
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