DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 26 is objected to because of the following informalities: a typo (period instead of comma/semicolon) is found here “ …. pixel driving region. a sixth gating circuit … “. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 31 and 33 are rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (USPN 2023/0169900 A1) in view of Zhang et al. (CN 116246569 A).
As to claim 1, Han teaches a display substrate, comprising:
a row addressing circuit in a row addressing region (see at least [0047] “the transition region is further provided with a row driving circuit, the row driving circuit is configured to drive the plurality of pixels in the first display region, the second display region and the transition region by rows. .. the display substrate provides a GIP (gate in pixel) design, that is, by setting the transition region between the high PPI region and the low PPI region, and setting a row driving circuit, such as gate driving circuit (GOA), in the transition region”; [0049] “The transition region 130 is further provided with a row driving circuit 220” – note transition region 130 is addressing region and row driving circuit 220 is row addressing circuit);
a first pixel circuit in a first pixel driving region on one side of the row addressing region; and a second pixel circuit in a second pixel driving region, on another side of the row addressing region (see at least [0047] “a first display region; a second display region, located at a side of the first display region in a first direction; and a transition region, located between the first display region and the second display region.”; [0049] “the display substrate 100 includes a first display region 110, a second display region 120 and a transition region 130. The second display region 120 is located on at least one side of the first display region 110 in the first direction X, and the transition region 130 is located between the first display region 110 and the second display region 120.”; [0053] “each of the two sides of the first row driving circuit unit 225A in the first direction respectively have an output terminal OUT, so that the first row driving circuit unit 225A can simultaneously drive the plurality of pixels 210 belonging to the same row in the first display region 110, the second display region 120 and the transition region 130.”; [0065] “each of the plurality sub-pixels 215 includes a pixel driving circuit 2152”; [0067] “the display substrate can be provided with a pixel driving circuit 2152 on the pixel circuit island 131”; [0084]-[0089]),
wherein the row addressing region is between the first pixel driving region and the second pixel driving region (see at least [0047] “a transition region, located between the first display region and the second display region.”; [0050] “by inserting a transition region between the high PPI region and the low PPI region, and arranging a row driving circuit in the transition region”);
wherein the row addressing circuit comprises:
a scan driving circuit (see at least [0055] “the row driving circuit 220 includes a gate driving circuit 2202 and a light-emitting control driving circuit 2204.”; [0105] “the gate driving unit 2252 includes an input transistor 241, a first control transistor 242, a second control transistor 243, an output control transistor 244, a gate output transistor 245…”; [0106] “the above-mentioned gate driving unit is a gate scanning shift register. … thereby realizing shift output for scanning pixels in the display substrate line by line.” – note gate driving circuit 2202/gate driving units 2252 are scan driving circuit);
the scan driving circuit between the first pixel driving region and the second pixel driving region, and the scan driving circuit being connected to and configured to drive pixel circuits of the first pixel driving region and the second pixel driving region (see at least [0047], [0049] “the transition region 130 is located between the first display region 110 and the second display region 120. … The transition region 130 is further provided with a row driving circuit 220, the row driving circuit 220 is configured to drive the plurality of pixels 210 in the first display region 110, the second display region 120 and the transition region 130 by rows”; [0050]; [0052] “the row driving circuit 220 can be a gate driving circuit”; [0053] “each of the two sides of the first row driving circuit unit 225A in the first direction respectively have an output terminal OUT, so that the first row driving circuit unit 225A can simultaneously drive the plurality of pixels 210 belonging to the same row in the first display region 110, the second display region 120 and the transition region 130”).
Han does not directly teach a first gating circuit, wherein the first gating circuit connects the scan driving circuit and the first pixel circuit; and a second gating circuit, wherein the second gating circuit connects the scan driving circuit and the second pixel circuit.
Zhang teaches a first gating circuit, wherein the first gating circuit connects the scan driving circuit and the first pixel circuit (see at least figs. 1 and 3 and description: “a first gate line MUX-display and a plurality of first switch elements T1,”; “the first electrode of each of the first switch element T1 is respectively connected with the output end G(1) … G(n) … of one of the shift register unit 1”; “a first type of pixel circuit connected to the first gate line L1.” – note first switching elements T1 are a first gating circuit connecting the scan/gate driving circuit to the first pixel circuit through the first gate line L1); and
a second gating circuit, wherein the second gating circuit connects the scan driving circuit and the second pixel circuit (see at least figs. 1 and 3 and description “a second gate line MUX-sensor and a plurality of second switch elements T2,”; “the first pole of each of the second switching element T2 is respectively connected with one output end G(1) … G(n) … of the shift register unit 1”; “a second type of pixel circuit connected with the second gate line L2.” – note second switching elements T2 is a second gating circuit connecting the scan/gate driving circuit to the second pixel circuit through the second gate line L2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Han’s respective output connections extending from the scan driving circuit toward the first and second pixel driving regions to include Zhang’s respective first and second gating circuits in those output paths, thereby resulting in “a first gating circuit between the scan driving circuit and the first pixel driving region, wherein the first gating circuit connects the scan driving circuit and the first pixel circuit; and a second gating circuit between the scan driving circuit and the second pixel driving region, wherein the second gating circuit connects the scan driving circuit and the second pixel circuit.” One of ordinary skill in the art would have been motivated to make such a modification to permit selective coupling of the common scan driving circuit to respective pixel circuits.
As to claim 31, Han teaches a method for manufacturing a display substrate (see Han at least [0121] “the display device 900 includes the display substrate 100 according to any embodiment described above.”), wherein the method comprises:
providing a base; forming a row addressing region, a first pixel driving region, and a second pixel driving region on the base, wherein the row addressing region is provided with a row addressing circuit; the first pixel driving region is on one side of the row addressing region, and is provided with a pixel circuit; and the second pixel driving region is on the other side of the row addressing region, and is provided with a pixel circuit (see at least [0047] “a first display region; a second display region, located at a side of the first display region in a first direction; and a transition region, located between the first display region and the second display region. .. the transition region is further provided with a row driving circuit, the row driving circuit is configured to drive the plurality of pixels in the first display region, the second display region and the transition region by rows. .. the display substrate provides a GIP (gate in pixel) design, that is, by setting the transition region between the high PPI region and the low PPI region, and setting a row driving circuit, such as gate driving circuit (GOA), in the transition region”; [0049] “the display substrate 100 includes a first display region 110, a second display region 120 and a transition region 130. The second display region 120 is located on at least one side of the first display region 110 in the first direction X, and the transition region 130 is located between the first display region 110 and the second display region 120. … The transition region 130 is further provided with a row driving circuit 220” – note transition region 130 is addressing region and row driving circuit 220 is row addressing circuit); [0053] “each of the two sides of the first row driving circuit unit 225A in the first direction respectively have an output terminal OUT, so that the first row driving circuit unit 225A can simultaneously drive the plurality of pixels 210 belonging to the same row in the first display region 110, the second display region 120 and the transition region 130.”; [0065] “each of the plurality sub-pixels 215 includes a pixel driving circuit 2152”; [0067] “the display substrate can be provided with a pixel driving circuit 2152 on the pixel circuit island 131”; [0084]-[0089]),
wherein the row addressing region is between the first pixel driving region and the second pixel driving region (see at least [0047] “a transition region, located between the first display region and the second display region.”; [0050] “by inserting a transition region between the high PPI region and the low PPI region, and arranging a row driving circuit in the transition region”);
wherein the row addressing circuit comprises:
a scan driving circuit (see at least [0055] “the row driving circuit 220 includes a gate driving circuit 2202 and a light-emitting control driving circuit 2204.”; [0105] “the gate driving unit 2252 includes an input transistor 241, a first control transistor 242, a second control transistor 243, an output control transistor 244, a gate output transistor 245…”; [0106] “the above-mentioned gate driving unit is a gate scanning shift register. … thereby realizing shift output for scanning pixels in the display substrate line by line.” – note gate driving circuit 2202/gate driving units 2252 are scan driving circuit);
the scan driving circuit between the first pixel driving region and the second pixel driving region, and the scan driving circuit being connected to and configured to drive pixel circuits of the first pixel driving region and the second pixel driving region (see at least [0047], [0049] “the transition region 130 is located between the first display region 110 and the second display region 120. … The transition region 130 is further provided with a row driving circuit 220, the row driving circuit 220 is configured to drive the plurality of pixels 210 in the first display region 110, the second display region 120 and the transition region 130 by rows”; [0050]; [0052] “the row driving circuit 220 can be a gate driving circuit”; [0053] “each of the two sides of the first row driving circuit unit 225A in the first direction respectively have an output terminal OUT, so that the first row driving circuit unit 225A can simultaneously drive the plurality of pixels 210 belonging to the same row in the first display region 110, the second display region 120 and the transition region 130”).
Han does not directly teach a first gating circuit, wherein the first gating circuit connects the scan driving circuit and the first pixel circuit; and a second gating circuit, wherein the second gating circuit connects the scan driving circuit and the second pixel circuit.
Zhang teaches a first gating circuit, wherein the first gating circuit connects the scan driving circuit and the first pixel circuit (see at least figs. 1 and 3 and description: “a first gate line MUX-display and a plurality of first switch elements T1,”; “the first electrode of each of the first switch element T1 is respectively connected with the output end G(1) … G(n) … of one of the shift register unit 1”; “a first type of pixel circuit connected to the first gate line L1.” – note first switching elements T1 are a first gating circuit connecting the scan/gate driving circuit to the first pixel circuit through the first gate line L1); and
a second gating circuit, wherein the second gating circuit connects the scan driving circuit and the second pixel circuit (see at least figs. 1 and 3 and description “a second gate line MUX-sensor and a plurality of second switch elements T2,”; “the first pole of each of the second switching element T2 is respectively connected with one output end G(1) … G(n) … of the shift register unit 1”; “a second type of pixel circuit connected with the second gate line L2.” – note second switching elements T2 is a second gating circuit connecting the scan/gate driving circuit to the second pixel circuit through the second gate line L2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Han’s respective output connections extending from the scan driving circuit toward the first and second pixel driving regions to include Zhang’s respective first and second gating circuits in those output paths, thereby resulting in “a first gating circuit between the scan driving circuit and the first pixel driving region, wherein the first gating circuit connects the scan driving circuit and the first pixel circuit; and a second gating circuit between the scan driving circuit and the second pixel driving region, wherein the second gating circuit connects the scan driving circuit and the second pixel circuit.” One of ordinary skill in the art would have been motivated to make such a modification to permit selective coupling of the common scan driving circuit to respective pixel circuits.
As to claim 33, Han teaches a display device, comprising a display, wherein a display substrate (see Han at least [0121] “the display device 900 includes the display substrate 100 according to any embodiment described above.”; [0122] “the above-mentioned display device can be an electronic product with display function such as a television, a mobile phone, a computer, a navigator, and an electronic picture frame, etc.”) comprises:
a row addressing circuit in a row addressing region (see at least [0047] “the transition region is further provided with a row driving circuit, the row driving circuit is configured to drive the plurality of pixels in the first display region, the second display region and the transition region by rows. .. the display substrate provides a GIP (gate in pixel) design, that is, by setting the transition region between the high PPI region and the low PPI region, and setting a row driving circuit, such as gate driving circuit (GOA), in the transition region”; [0049] “The transition region 130 is further provided with a row driving circuit 220” – note transition region 130 is addressing region and row driving circuit 220 is row addressing circuit);
a first pixel circuit in a first pixel driving region on one side of the row addressing region; and a second pixel circuit in a second pixel driving region, on another side of the row addressing region (see at least [0047] “a first display region; a second display region, located at a side of the first display region in a first direction; and a transition region, located between the first display region and the second display region.”; [0049] “the display substrate 100 includes a first display region 110, a second display region 120 and a transition region 130. The second display region 120 is located on at least one side of the first display region 110 in the first direction X, and the transition region 130 is located between the first display region 110 and the second display region 120.”; [0053] “each of the two sides of the first row driving circuit unit 225A in the first direction respectively have an output terminal OUT, so that the first row driving circuit unit 225A can simultaneously drive the plurality of pixels 210 belonging to the same row in the first display region 110, the second display region 120 and the transition region 130.”; [0065] “each of the plurality sub-pixels 215 includes a pixel driving circuit 2152”; [0067] “the display substrate can be provided with a pixel driving circuit 2152 on the pixel circuit island 131”; [0084]-[0089]),
wherein the row addressing region is between the first pixel driving region and the second pixel driving region (see at least [0047] “a transition region, located between the first display region and the second display region.”; [0050] “by inserting a transition region between the high PPI region and the low PPI region, and arranging a row driving circuit in the transition region”);
wherein the row addressing circuit comprises:
a scan driving circuit (see at least [0055] “the row driving circuit 220 includes a gate driving circuit 2202 and a light-emitting control driving circuit 2204.”; [0105] “the gate driving unit 2252 includes an input transistor 241, a first control transistor 242, a second control transistor 243, an output control transistor 244, a gate output transistor 245…”; [0106] “the above-mentioned gate driving unit is a gate scanning shift register. … thereby realizing shift output for scanning pixels in the display substrate line by line.” – note gate driving circuit 2202/gate driving units 2252 are scan driving circuit);
the scan driving circuit between the first pixel driving region and the second pixel driving region, and the scan driving circuit being connected to and configured to drive pixel circuits of the first pixel driving region and the second pixel driving region (see at least [0047], [0049] “the transition region 130 is located between the first display region 110 and the second display region 120. … The transition region 130 is further provided with a row driving circuit 220, the row driving circuit 220 is configured to drive the plurality of pixels 210 in the first display region 110, the second display region 120 and the transition region 130 by rows”; [0050]; [0052] “the row driving circuit 220 can be a gate driving circuit”; [0053] “each of the two sides of the first row driving circuit unit 225A in the first direction respectively have an output terminal OUT, so that the first row driving circuit unit 225A can simultaneously drive the plurality of pixels 210 belonging to the same row in the first display region 110, the second display region 120 and the transition region 130”).
Han does not directly teach a first gating circuit, wherein the first gating circuit connects the scan driving circuit and the first pixel circuit; and a second gating circuit, wherein the second gating circuit connects the scan driving circuit and the second pixel circuit.
Zhang teaches a first gating circuit, wherein the first gating circuit connects the scan driving circuit and the first pixel circuit (see at least figs. 1 and 3 and description: “a first gate line MUX-display and a plurality of first switch elements T1,”; “the first electrode of each of the first switch element T1 is respectively connected with the output end G(1) … G(n) … of one of the shift register unit 1”; “a first type of pixel circuit connected to the first gate line L1.” – note first switching elements T1 are a first gating circuit connecting the scan/gate driving circuit to the first pixel circuit through the first gate line L1); and
a second gating circuit, wherein the second gating circuit connects the scan driving circuit and the second pixel circuit (see at least figs. 1 and 3 and description “a second gate line MUX-sensor and a plurality of second switch elements T2,”; “the first pole of each of the second switching element T2 is respectively connected with one output end G(1) … G(n) … of the shift register unit 1”; “a second type of pixel circuit connected with the second gate line L2.” – note second switching elements T2 is a second gating circuit connecting the scan/gate driving circuit to the second pixel circuit through the second gate line L2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Han’s respective output connections extending from the scan driving circuit toward the first and second pixel driving regions to include Zhang’s respective first and second gating circuits in those output paths, thereby resulting in “a first gating circuit between the scan driving circuit and the first pixel driving region, wherein the first gating circuit connects the scan driving circuit and the first pixel circuit; and a second gating circuit between the scan driving circuit and the second pixel driving region, wherein the second gating circuit connects the scan driving circuit and the second pixel circuit.” One of ordinary skill in the art would have been motivated to make such a modification to permit selective coupling of the common scan driving circuit to respective pixel circuits.
Claims 2-3, 9, 11-12, 15, 18, 21, 23 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (USPN 2023/0169900 A1) in view of Zhang et al. (CN 116246569 A), further in view of Jung (CN 109390377 A).
As to claim 2, the combination of Han and Zhang teach the display substrate according to claim 1 (see above rejection), further comprising: a base; a driving circuit layer on the base (see Han at least [0068] “when the above-mentioned display substrate is an organic light-emitting diode display substrate, the above-mentioned driving electrode can be an anode”; [0079] “the first portion 510A and the data line 610 are located on a first source-drain metal layer SD1, and the second portion 510B is located on a second source-drain metal layer SD2.”; [0103] “the active layer (channel region) of the transistor uses semiconductor materials, such as poly-silicon … amorphous silicon, indium gallium zinc oxide (IGZO), etc., while the gate electrode, source electrode and drain electrode use metal materials”).
Han and Zhang do not directly teach an organic light-emitting layer on the driving circuit layer and away from the base; wherein the driving circuit layer comprises the row addressing circuit of the row addressing region.
Jung teaches a base; a driving circuit layer on the base; and an organic light-emitting layer on the driving circuit layer and away from the base; wherein the driving circuit layer comprises the row addressing circuit of the row addressing region (see Jung at least fig. 4 and description: “display panel DP may include a substrate 100, a driving layer 200, a display element layer 300 and the sealing layer 400.”; “the driving layer 200 disposed on the substrate 100. driving layer 200 comprises a circuit element and at least one intermediate insulating layer.”; “a display element layer 300 set on the driving layer 200…. In an exemplary embodiment of the invention, the display element may be an organic light emitting diode.”; “the circuit element comprises a signal line described with reference to FIG. 2, the scan driving circuit GDC, the pixel driving circuit of the pixel PX, light sensor and light pixel HX of the light drive circuit.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the OLED display substrate of Han/Zhang with Jung’s known OLED layer structure, in which the organic light-emitting layer is disposed over the driving circuit layer, in order to provide the light-emitting elements over the circuitry that drives the light-emitting elements.
As to claim 3, the combination of Han, Zhang and Jung teach the display substrate according to claim 2 (see above rejection), wherein the first pixel circuit and the second pixel circuit are in the driving circuit layer, and the first pixel circuit comprises a first capacitor and first thin film transistors and is configured to control light emission of a first pixel, and the second pixel circuit comprises a second capacitor and second thin film transistors and is configured to control light emission of a second pixel (see Han at least [0067] “the driving spacing region 133 is provided with a row driving circuit unit 225 … the display substrate can be provided with a pixel driving circuit 2152 on the pixel circuit island 131 … and a row driving circuit unit 225 on the driving spacing region 133”; [0084] “the pixel driving circuit 2152 includes a first thin film transistor T21, a second thin film transistor T22, a third thin film transistor T23, a fourth thin film transistor T24, a fifth thin film transistor T25, a sixth thin film transistor T26, a seventh thin film transistor T27 and a storage capacitor Cst. .. the pixel driving circuit illustrated in FIG. 7 adopts a 7T1C structure.”; [0089] “the driving current Id is applied to each of the plurality sub-pixels through the fifth thin film transistor T5, so that the light-emitting layer of each of the plurality sub-pixels emits light.”; and Jung at least figs. 4, 5, 7 (first and second groups of pixel driving circuits), 8A-B (pixel driving circuits), and description: “Referring to FIG. 4, FIG. 5, FIG. 7, FIG. 8A and FIG. 8B, the driver layer 200 may include … the first driving circuit group UC1 and UC2 and … the second drive circuit UC3 and UC4.”; “a first driving circuit group UC1 comprises N pixel drive circuits CK1 to CK8. .. a transistor and a capacitor … first pixel drive circuit CK1 to CK8 … may include a driving circuit … for driving the first display element group UP1.”; “the second drive circuit group UC3 can include N pixel drive circuits CK17 to CK24. .. second pixel drive circuit CK17 to CK24 … may include a transistor and a capacitor corresponding to the second display element.”; fig. 10 (TFT implementation) and description: “driving layer 200 of the pixel driving circuit CK1 to CK32 can include a pixel transistor …. a pixel transistor TRX comprises an active layer 281, a gate electrode 283, a source electrode 285 and a drain electrode 287.”; fig. 14 (capacitor/TFT pixel circuit) and description: “FIG. 14 is a circuit diagram of a pixel shown in FIG. 12. … may include a plurality of transistors T1 to T7, a storage capacitor Cst and an organic emitting device OLED according to one pixel PX”); wherein the row addressing circuit is in a same layer as the first pixel circuit and the second pixel circuit (see Jung at least fig. 4 and description: “the driving layer 200 … comprises … the scan driving circuit GDC, the pixel driving circuit of the pixel PX, light sensor and … light drive circuit.”).
As to claim 9, the combination of Han, Zhang and Jung teach the display substrate according to claim 2 (see above rejection), wherein the driving circuit layer comprises: a first active layer; a first gate layer; a second gate layer on the first gate layer and away from the base; a second active layer; and a third gate layer on the second gate layer and away from the base (see Jung at least fig. 10 and description: “FIG. 10 is a view of the display panel taken along the line I-I’ of FIG. 5.”; “light optical transistor TRP … comprises an active layer 211, a gate electrode 213, a source electrode 215 and a drain electrode 217.”; “a pixel transistor TRX comprises an active layer 281, a gate electrode 283, a source electrode 285 and a drain electrode 287.”), wherein the first active layer comprises amorphous silicon or polycrystalline silicon (see Han at least [0103] “the active layer (channel region) of the transistor uses semiconductor materials, such as poly-silicon (such as low-temperature poly-silicon or high-temperature poly-silicon), amorphous silicon, indium gallium zinc oxide (IGZO), etc.”; [0118] “the active layer (channel region) of the transistor uses semiconductor materials, such as poly-silicon … amorphous silicon, indium gallium zinc oxide (IGZO), etc.”).
As to claim 11, the combination of Han, Zhang and Jung teach the display substrate according to claim 9 (see above rejection), wherein the first active layer comprises first active regions, wherein each of the first active regions corresponds to a thin film transistor or a plurality of electrically connected thin film transistors; and the first active regions are in the row addressing region, the first pixel driving region, and the second pixel driving region (see Han at least [0103] “the active layer (channel region) of the transistor uses semiconductor materials”; [0118]).
As to claim 12, the combination of Han, Zhang and Jung teach the display substrate according to claim 9 (see above rejection), wherein the first gate layer in the first pixel driving region and the second pixel driving region comprises a first type gate line extending along the first direction, and gate pattern blocks; wherein the gate pattern block is block-shaped, and some of the gate pattern blocks are arranged in a row along a first direction (see Han at least [0085] “the gate line 650 is connected with the third gate electrode G of the third thin film transistor T23”).
As to claim 15, the combination of Han, Zhang and Jung teach the display substrate according to claim 9 (see above rejection), wherein the first gate layer comprises a first gate connecting line for connecting a gate line on any one of two sides of the row addressing region; wherein the first gate connecting line comprises a gate connecting end connecting the gate line, an away gate end in the row addressing region and away from the gate line, and a winding line segment between the gate connecting end and the away gate end and connecting the gate connecting end and the away gate end, wherein the gate connecting end, the away gate end or both extend along a first direction, and the winding line segment extends along a second direction (see Han at least [0078] “Each of the plurality of first driving lines 510 includes a first portion 510A extending in the second direction and a second portion 510B extending in the first direction”; [0080] “each of the plurality of first driving lines 510 is arranged in steps.”).
As to claim 18, the combination of Han, Zhang and Jung teach the display substrate according to claim 9 (see above rejection), wherein the second gate layer in the first pixel driving region and the second pixel driving region comprises a fourth type gate line extending along a first direction, and gate pattern blocks; wherein at least one portion of the fourth type gate line and a corresponding portion of the first gate layer form a capacitor, and at least one portion of one of the gate pattern blocks and a corresponding portion of the first gate layer form a capacitor (see Han at least [0084] “The storage capacitor Cst includes a first electrode block CE1 and a second electrode block CE2.”).
As to claim 21, the combination of Han, Zhang and Jung teach the display substrate according to claim 9 (see above rejection), wherein the second gate layer comprises a third gate connecting line for connecting a gate line on any one of two sides of the row addressing region; wherein the third gate connecting line comprises a middle connecting segment, two near gate ends, and two vertical segments, wherein the middle connecting segment is in a middle region of the row addressing region and extends along the first direction to both sides of the row addressing region, the two near gate ends are on opposite sides of the gate connecting line along the first direction, and the vertical segments each extend along the second direction and are connected between the middle connecting segment and one of the two near gate ends (see Han at least [0078] “the plurality of gate driving units 2252 are arranged in a staggered way in the first direction. Each of the plurality of first driving lines 510 includes a first portion 510A extending in the second direction and a second portion 510B extending in the first direction”; [0080] “each of the plurality of first driving lines 510 is arranged in steps.”).
As to claim 23, the combination of Han, Zhang and Jung teach the display substrate according to claim 9 (see above rejection), wherein the third gate layer in the first pixel driving region and the second pixel driving region comprises a first type gate line extending along a first direction (see Han at least [0051] “the second display regions 120 are located at two sides of the first display region 110 in the first direction, and the two transition regions 130 are respectively located between the first display region 110 and the two second display regions 120.”; [0060] “the display substrate 100 further includes a third display region 180”; [0062] “the display substrate 100 further includes an edge driving circuit 280 located on at least one side of the third display region 180 in the first direction X. The edge driving circuit 280 is configured to drive the pixels 210 in the third display region 180.”).
As to claim 30, the combination of Han, Zhang and Jung teach the display substrate according to claim 1 (see above rejection), wherein a refresh rate of the first pixel driving region and a refresh rate of the second pixel driving region are independently controlled by the row addressing circuit of the row addressing region.- Examiner is taking official notice that it is known in the art to operate different display regions at different refresh rates and would be obvious to incorporate into Han/Zhang/Jung in order to permit different portions of the display to be refreshed according to their respective display requirements, thereby reducing unnecessary driving operations and associated power consumption).
Allowable Subject Matter
Claims 5, 13, 17, 19 and 24-26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: None of the prior art of record teach:
“A display substrate, comprising:
a row addressing circuit in a row addressing region;
a first pixel circuit in a first pixel driving region on one side of the row addressing region; and
a second pixel circuit in a second pixel driving region, on another side of the row addressing region, wherein the row addressing region is between the first pixel driving region and the second pixel driving region;
wherein the row addressing circuit comprises:
a scan driving circuit;
a first gating circuit between the scan driving circuit and the first pixel driving region, wherein the first gating circuit connects the scan driving circuit and the first pixel circuit; and
a second gating circuit between the scan driving circuit and the second pixel driving region, wherein the second gating circuit connects the scan driving circuit and the second pixel circuit;
further comprising: a base; a driving circuit layer on the base; and an organic light-emitting layer on the driving circuit layer and away from the base; wherein the driving circuit layer comprises the row addressing circuit of the row addressing region;
further comprising: a bottom shielding layer between the base and the driving circuit layer;
wherein the bottom shielding layer comprises connecting wires and shielding patterns, wherein the connecting wires electrically connect the shielding patterns;
wherein one of the shielding patterns comprises a horizontal shielding line extending along a first direction, a vertical shielding line extending along a second direction, and a square shielding block at an intersection of the horizontal shielding line and the vertical shielding line.”; and
“A display substrate, comprising:
a row addressing circuit in a row addressing region;
a first pixel circuit in a first pixel driving region on one side of the row addressing region; and
a second pixel circuit in a second pixel driving region, on another side of the row addressing region, wherein the row addressing region is between the first pixel driving region and the second pixel driving region;
wherein the row addressing circuit comprises:
a scan driving circuit;
a first gating circuit between the scan driving circuit and the first pixel driving region, wherein the first gating circuit connects the scan driving circuit and the first pixel circuit; and
a second gating circuit between the scan driving circuit and the second pixel driving region, wherein the second gating circuit connects the scan driving circuit and the second pixel circuit;
further comprising: a base; a driving circuit layer on the base; and an organic light-emitting layer on the driving circuit layer and away from the base; wherein the driving circuit layer comprises the row addressing circuit of the row addressing region;
wherein the driving circuit layer comprises: a first active layer; a first gate layer; a second gate layer on the first gate layer and away from the base; a second active layer; and a third gate layer on the second gate layer and away from the base; wherein the first active layer comprises amorphous silicon or polycrystalline silicon;
wherein the first gate layer in the row addressing region comprises a first type gate line extending along a first direction, a second type gate line extending both along the first direction and a second direction, block- shaped gate pattern blocks, and U-shaped third type gate lines; wherein the third type gate line comprises a horizontal connecting line extending along the first direction, and two vertical gate portions respectively arranged at both ends of the horizontal connecting line, wherein the two vertical gate portions are parallel and spaced apart from each other;
or
wherein the first gate layer comprises a second gate connecting line for connecting a gate line on any one of two sides of the row addressing region, one end of the second gate connecting line is connected to the gate line, and another end of the second gate connecting line does not extend to a region of the scan driving circuit of the row addressing region;
or
wherein the second gate layer in the row addressing region comprises a fourth type gate line extending along a first direction, a fifth type gate line extending both along the first direction and a second direction, block-shaped gate pattern blocks, and U-shaped sixth type gate lines; wherein the sixth type gate line comprises a horizontal connecting line extending along the first direction, and two vertical gate portions respectively arranged at both ends of the horizontal connecting line, wherein the two vertical gate portions are parallel and spaced apart from each other; wherein one of the gate pattern blocks and a corresponding portion of the first gate layer form a capacitor;
or
wherein the third gate layer in the row addressing region comprises a first type gate line extending along a first direction, a second type gate line extending both along the first direction and a second direction, and U-shaped third type gate lines; wherein the third type gate line comprises a horizontal connecting line extending along the first direction, and two vertical gate portions respectively arranged at both ends of the horizontal connecting line, wherein the two vertical gate portions are parallel and spaced apart from each other;
or
wherein the third gate layer comprises a third gate connecting line for connecting a gate line on any one of two sides of the row addressing region; wherein the third gate connecting line comprises a middle connecting segment, two near gate ends, and two vertical segments, wherein the middle connecting segment is in a middle region of the row addressing region and extends along the first direction to both sides of the row addressing region, the two near gate ends are located on opposite sides of the gate connecting line along the first direction, and the vertical segments each extends along the second direction and is connected between the middle connecting segment and one of the two near gate ends.”;
and
“A display substrate, comprising:
a row addressing circuit in a row addressing region;
a first pixel circuit in a first pixel driving region on one side of the row addressing region; and
a second pixel circuit in a second pixel driving region, on another side of the row addressing region, wherein the row addressing region is between the first pixel driving region and the second pixel driving region;
wherein the row addressing circuit comprises:
a scan driving circuit;
a first gating circuit between the scan driving circuit and the first pixel driving region, wherein the first gating circuit connects the scan driving circuit and the first pixel circuit; and
a second gating circuit between the scan driving circuit and the second pixel driving region, wherein the second gating circuit connects the scan driving circuit and the second pixel circuit;
further comprising:
a second row addressing circuit in a second row addressing region at an edge of the display substrate; and
a third pixel driving region between the second row addressing region and the first pixel driving region;
wherein the second row addressing circuit comprises:
a second scan driving circuit;
a third gating circuit between the second scan driving circuit and the third pixel driving region, wherein the third gating circuit connects the second scan driving circuit and a third pixel circuit in the third pixel driving region; and
a third row addressing circuit in a third row addressing region at another edge of the display substrate;
wherein the third row addressing circuit comprises:
a third scan driving circuit;
a fourth gating circuit between the third scan driving circuit and a fourth pixel driving region between the second pixel driving region and the third row addressing region, wherein the fourth gating circuit connects the third scan driving circuit and a pixel circuit in the fourth pixel driving region; and
a fourth row addressing circuit in a fourth row addressing region;
wherein the fourth row addressing circuit comprises:
a fourth scan driving circuit;
a fifth gating circuit between the fourth scan driving circuit and a fifth pixel driving region between the fourth row addressing region and the third pixel driving region, wherein the fifth gating circuit connects the fourth scan driving circuit and a pixel circuit in the fifth pixel driving region.
a sixth gating circuit between the fourth scan driving circuit and a sixth pixel driving region between the fourth row addressing region and the first pixel driving region, wherein the sixth gating circuit connects the fourth scan driving circuit and a pixel circuit in the sixth pixel driving region;
wherein a number of pixels in each row of the first pixel driving region is equal to a number of pixels in each row of the second pixel driving region and/or a number of pixels in each row of the fifth pixel driving region is equal to a number of pixels in each row of the sixth pixel driving region.”
Conclusion
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/JENNIFER L ZUBAJLO/ Examiner, Art Unit 2627 9/4/2026
/KE XIAO/ Supervisory Patent Examiner, Art Unit 2627
