Prosecution Insights
Last updated: April 19, 2026
Application No. 18/995,855

DISPLAY PANEL AND DISPLAY DEVICE

Final Rejection §103§112
Filed
Jan 17, 2025
Examiner
JANSEN II, MICHAEL J
Art Unit
2626
Tech Center
2600 — Communications
Assignee
BOE TECHNOLOGY GROUP CO., LTD.
OA Round
2 (Final)
66%
Grant Probability
Favorable
3-4
OA Rounds
2y 3m
To Grant
86%
With Interview

Examiner Intelligence

Grants 66% — above average
66%
Career Allow Rate
409 granted / 619 resolved
+4.1% vs TC avg
Strong +20% interview lift
Without
With
+20.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
37 currently pending
Career history
656
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
46.0%
+6.0% vs TC avg
§102
25.2%
-14.8% vs TC avg
§112
23.2%
-16.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 619 resolved cases

Office Action

§103 §112
DETAILED ACTION This FINAL action is in response to Application No. 18/995,855 originally filed 01/17/2025. The amendment presented on 02/10/2026 which provides amendments to claims 1, 16, and 20 is hereby acknowledged. Currently Claims 1-20 are pending. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Previous Claim Rejections - 35 USC § 112 2nd Paragraph The claims were previously rejected as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor regards as the invention. The office thanks the applicant for addressing these concerns as the claims have been amended to overcome this rejection and consequently the previous rejection is now hereby withdrawn. Response to Arguments Applicant's arguments filed 02/10/2026 have been fully considered but they are not persuasive. Applicant makes assertions regarding Fig. 1 and statements regarding paragraphs [0028] (noted in the Remarks as [0024]) and paragraphs [0050-0051] however fails to further provide consideration of the further cited paragraphs in view of the additional embodiment as disclosed in Figures 13-14 and paragraphs [0093-0102]. Fig. 13 expressly provides for connecting like colors in a single driving row as seen in the figure and as described in paragraph [0102] which expressly states “pixel electrodes 201G1 and 201G2 of green pixels may be connected to a pixel circuit in the same row.”. It can be concluded that these are in the same row as the cited portion expressly states that they are. Therefore, Applicant’s arguments regarding the prior art are not found persuasive and the rejection will be currently maintained. Claim Rejections - 35 USC § 103 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claim(s) 1-15 and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Song et al. U.S. Patent Application Publication No. 2016/0217744 A1 hereinafter Song and further in view of Hwang et al. U.S. Patent Application Publication No. 2019/0279563 A1 hereinafter Hwang. Consider Claim 1: Song discloses a display panel, comprising: (Song, See Abstract.) a base substrate; (Song, [0056-0058], [0056], “FIGS. 4 to 8 illustrate embodiments of layouts of the pixels. Referring to FIG. 4, one layout embodiment includes a substrate, an active pattern 110, a gate insulation layer, first gate electrodes 120 and 121, second gate electrodes 125 and 126, third gate electrodes 130 and 131, fourth gate electrodes 135, and 136 and fifth gate electrodes 140 and 141.”) … n rows of drive terminals, n being greater than or equal to two; (Song, [0093-0102], [0028], “FIG. 1 illustrates an embodiment of pixels of an organic light emitting display device. Referring to FIG. 1, the pixels include a pixel (N) in an even-numbered row (even row) in a first direction and a pixel (N+1) in an odd-numbered row (odd row).”) a plurality of sub-pixel clusters, disposed on the base substrate, (Song, [0049-0051], [0093-0102], [0049], “FIG. 2 illustrates an embodiment of a plurality of data wirings (DATA_ODD1, DATA_ODD2, DATA_EVEN1, DATA_EVEN2) and pixels (1-1, 2-1, 3-1, 4-1, 1-2, 2-2, 3-2, 4-2). The pixels (1-1, 2-1, 3-1, 4-1, 1-2, 2-2, 3-2, 4-2) may be arranged in a first direction and a second direction perpendicular to the first direction. The pixels (1-1, 2-1, 3-1, 4-1) are arranged in a first pixel column in the first direction. The pixels (1-2, 2-2, 3-2, 4-2) are arranged in a second pixel column in the first direction. The pixel columns may be arranged along the second direction. Each of the pixels may include a plurality of transistors (TR1-TR7), an organic light emitting diode, and one or more capacitors, as described, for example, in FIG. 1.”) wherein each of the sub-pixel clusters comprises n rows of sub-pixels emitting light of m colors, wherein m is a number of colors of the sub-pixels, and m is greater than or equal to n; the n rows of sub-pixels forming n sub-pixel groups, each of the n sub-pixel groups comprising at least one sub-pixel of at least one color, and adjacent sub-pixel groups comprising sub-pixels of different colors, (Song, [0093-0102], [0060], “In some example embodiments, a part of the active pattern 110 corresponding to a pixel (N) in an even-numbered row may have a symmetrical shape with a part of active pattern 110 corresponding to a pixel (N+1) in odd-numbered row with respect to an axis extending in the first direction. For example, the active pattern 110 of the pixel (N) in the even-numbered row and an active pattern 110 of the pixel (N+1) in the odd-numbered row may have symmetrical shape relative to each other. Therefore, the first to seventh areas (a, b, c, d, e, f, g) of the active pattern 110 corresponding to the pixel (N) in an even-numbered row may be symmetrical to the first to seventh areas (a′, b′, c′, d′, e′, f′, g′) of the active pattern 110 corresponding to the pixel (N+1) in an odd-numbered row.”) wherein the n sub-pixel groups are in correspondence with the n rows of drive terminals respectively and row numbers of the drive terminals corresponding to the sub-pixel groups comprising the sub-pixels of a same color in different sub-pixel clusters are the same, the sub-pixels in the sub-pixel groups of a Kth row are electrically connected to the drive terminals of the Kth row, 1 <K< n, the sub-pixels of the same color is driven via a same row of the drive terminals. (Song, [0093-0102], [0102], “In accordance with one or more embodiments, second connecting patterns 177 and 178 and connecting portions 204R, 204G, and 204B are included and pixel electrodes 201G1 and 201G2 of green pixels may be connected to a pixel circuit in the same row. Therefore, image quality may be improved.”) Song, while implying that a gate/scan drive circuit would exist in the device as Song expressly teaches n rows of drive terminals, n being greater than or equal to two. (Song, See Fig. 1 items n and n+1) Song however does not expressly recite a drive circuit, disposed on the base substrate and comprising a plurality of drive units, wherein the plurality of drive units comprise n rows of drive terminals, n being greater than or equal to two. Hwang however teaches that it was a known technique to those having ordinary skill in the art before the effective filing date of the invention that a display panel would have gate/scan driver to drive the rows. Hwang therefore teaches a drive circuit, disposed on the base substrate and comprising a plurality of drive units, wherein the plurality of drive units comprise n rows of drive terminals, n being greater than or equal to two. (Hwang, [0055-0058], [0081-0085], [0083] The display panel 510 may have a plurality of pixel regions PR1 and PR2, and each pixel region PR1 and PR2 may include two sub-pixel regions SPR1, SPR2, SPR3 and SPR4. Further, in each sub-pixel region SPR1, SPR2, SPR3 and SPR4, one OLED G1, R1, B1 and G2 and one sub-pixel circuit SPC1, SPC2, SPC3 and SPC4 may be disposed. In the display panel 510 of FIG. 10, unlike a display panel 110 of FIG. 1, each sub-pixel circuit SPC1, SPC2, SPC3 and SPC4 may drive the OLED G1, R1, B1 and G2 in a sub-pixel region SPR1, SPR2, SPR3 and SPR4 the same as a sub-pixel region SPR1, SPR2, SPR3 and SPR4 in which the sub-pixel circuit SPC1, SPC2, SPC3 and SPC4 is disposed.”) It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide gate/scan drivers as this was a known technique in view of Hwang and would have been utilized for the purpose of having the ability of the panel to be driven under different driving conditions (e.g., different SOTs, different off period ratios, etc.) (Hwang, [0084]) Consider Claim 2: Song in view of Hwang discloses the display panel according to claim 1, wherein n is 2, and the row numbers of the drive terminals corresponding to the sub-pixel groups comprising the sub- pixels of the same color in different sub-pixel clusters have a same parity. (Hwang, [0081-0085], Song, [0093-0102], [0102], “In accordance with one or more embodiments, second connecting patterns 177 and 178 and connecting portions 204R, 204G, and 204B are included and pixel electrodes 201G1 and 201G2 of green pixels may be connected to a pixel circuit in the same row. Therefore, image quality may be improved.”) Consider Claim 3: Song in view of Hwang discloses the display panel according to claim 1, wherein each of the sub-pixels comprises a light-emitting unit and a sub-pixel circuit, wherein the sub-pixel circuit is electrically connected to the light-emitting unit, and the sub-pixel circuit is further electrically connected to a drive terminal corresponding to the sub-pixel where the sub-pixel circuit is disposed. (Hwang, [0081-0085], Song, [0093-0102], [0028], “FIG. 1 illustrates an embodiment of pixels of an organic light emitting display device. Referring to FIG. 1, the pixels include a pixel (N) in an even-numbered row (even row) in a first direction and a pixel (N+1) in an odd-numbered row (odd row). Each of the pixels (N, N+1) includes organic light emitting diode (OLED), a first transistor (TR1), a second transistor (TR2), a third transistor (TR3), a storage capacitor (CST), a forth transistor (TR4), a fifth transistor (TR5), a sixth transistor (TR6) and a seventh transistor (TR7). According to some example embodiments, each of the pixels (N, N+1) may further include cell capacitor (CEL) formed by a parasitic capacitor.”) Consider Claim 4: Song in view of Hwang discloses the display panel according to claim 3, wherein sub-pixel circuits of the n rows of sub-pixels are arranged in n rows on the base substrate, wherein the n rows of sub-pixel circuits correspond to the n rows of drive terminals respectively, and each of the n rows of sub-pixel circuits is electrically connected to a corresponding drive terminal. (Hwang, [0081-0085], Song, [0093-0102], [0094], “The pixel electrodes 201G1, 201G2, 201R, and 201B may have a diamond shape including sides extending in the first direction and the second direction. The electrodes 201G1, 201G2, 201R, and 201B may have a different shape in another embodiment.” See Fig. 13.) Consider Claim 5: Song in view of Hwang discloses the display panel according to claim 4, wherein light-emitting units of the n rows of sub-pixels are arranged in n rows on the base substrate, wherein among the n rows of light-emitting units, an orthographic projection of each of the light-emitting units of an xth row on the base substrate is overlapped with an orthographic projection of each of the sub- pixel circuits of an xth row on the base substrate,1<x<n; a first sub-pixel group of the n sub-pixel groups comprises a target sub-pixel, the light- emitting unit of the target sub-pixel is disposed in the xth row, and the sub-pixel circuit of the target sub-pixel is disposed in an (x+a)th row, 1 < x+a < n, and a ≠ 0. (Hwang, [0081-0085], Song, [0093-0102], [0099], “In one embodiment, pixel electrodes 201G1 and 201G2 of a green pixel may be connected to a seventh area (g′) of the active pattern 110 in a pixel (N+1) of odd-numbered row. Electrodes 201R and 201B of a red pixel and a blue pixel may be connected to a seventh area (g) of the active pattern 110 in a pixel (N) of an even-numbered row.” See Fig. 13) Consider Claim 6: Song in view of Hwang discloses the display panel according to claim 5, further comprising: a plurality of connection structures, wherein the plurality of connection structures are disposed on the base substrate, a first connection structure of the plurality of connection structures is electrically connected to the light-emitting unit of the target sub-pixel disposed in the xthrow, and connected to the sub-pixel circuit of the target sub-pixel disposed in the (x+a)th row, respectively. (Hwang, [0081-0085], Song, [0093-0102], [0099], “In one embodiment, pixel electrodes 201G1 and 201G2 of a green pixel may be connected to a seventh area (g′) of the active pattern 110 in a pixel (N+1) of odd-numbered row. Electrodes 201R and 201B of a red pixel and a blue pixel may be connected to a seventh area (g) of the active pattern 110 in a pixel (N) of an even-numbered row.” See Fig. 13) Consider Claim 7: Song in view of Hwang discloses the display panel according to claim 6, wherein the light-emitting unit comprises a first electrode, an electroluminescent layer, and a second electrode stacked sequentially along a direction away from the base substrate, wherein the first electrode is electrically connected to the first connection structure. (Song, [0087], “The common electrode 220 may be on the pixel defined layer 215 and the organic light emitting layer 210. In one embodiment, the common electrode 220 may include a transparent conductive material. For example, the common electrode 220 may include indium a tin oxide, an indium zinc oxide, a zinc oxide, a tin oxide, a gallium oxide, an indium oxide, etc. In one embodiment, the common electrode 220 may be a cathode electrode, e.g., the common electrode 220 may be in an organic light emitting diode (OLED) in FIG. 1 and an organic light emitting layer and a pixel electrode 200G1 may correspond to the common electrode 220. In one embodiment, the common electrode 220 may be an anode electrode. The common electrode 220 may be supplied with a second power supply voltage (ELVSS).”) Consider Claim 8: Song in view of Hwang discloses the display panel according to claim 7, wherein the first connection structure and the first electrode are disposed in a same layer. (Song, [0089-0102], [0097], “In one embodiment, one or more of the pixel electrodes 201G1, 201G2, 201R, and 201B may be connected to a seventh area (g, g′; referring to FIG. 10) through second connecting patterns 177 and 178, connecting portion 204R, 204G, and 204B, and/or electrode contacts 205R, 205G, and 205B.”) Consider Claim 9: Song in view of Hwang discloses the display panel according to claim 8, wherein the sub-pixel circuit comprises a source-drain conductive structure, wherein the source-drain conductive structure comprises a source-drain connection terminal, wherein a second end of the first connection structure is connected to the source-drain connection terminal. (Hwang, [0081-0085], Song, [0089-0102], [0085], “FIG. 9 illustrates a cross-sectional view illustrating an embodiment of the seventh transistor in FIG. 8. Referring to FIG. 9, this embodiment includes the active pattern 110, a gate insulating layer 118, a fifth gate electrode 140, a first insulating interlayer 145, a second insulating interlayer 159, a seventh contact 186, a ninth contact 191, a first power supply wiring 165, a third insulating interlayer 198, an electrode contact 205, a pixel electrode 200G1, an organic light emitting layer 210, a pixel defined layer 215, and a common electrode 220 on a substrate 100.”) Consider Claim 10: Song in view of Hwang discloses the display panel according to claim 7, wherein the sub-pixel circuit comprises a source-drain conductive structure, wherein the first connection structure and the source-drain conductive structure are disposed in a same layer. (Song, See Fig. 11. [0091], [0080], “The first power supply wiring 165 may be supplied an internal voltage (VINT) in FIG. 1. The first power supply wiring 165 may be connected to the second conductive pattern 155 (referring to FIG. 5) apart in the second direction through a first contact 180 and a third contact 183. The first power supply wiring 165 may be connected to second conductive patterns 156 (referring to FIG. 5) apart in the second direction through a eighth contact 190 and a tenth contact 192. In another embodiment, the first power supply wiring 165 may be connected to fifth areas (e, e′; referring to FIG. 4) of an active pattern 110 through a second contact 181 and a ninth contact 191.”) Consider Claim 11: Song in view of Hwang discloses the display panel according to claim 10, wherein the source-drain conductive structure comprises a first source-drain conductive structure and a second source-drain conductive structure; wherein the first source-drain conductive structure and the second source-drain conductive structure are arranged in a direction away from the base substrate; and one end of the first connection structure is connected to the second source-drain conductive structure and the other end of the first connection structure is electrically connected to the first electrode. (Song, See Fig. 6-7, 11. [0091], [0080], [0077], “The first data wiring 160 and the second data wiring 161 may extend in the first direction and may be separated from each other along the second direction. The first data wiring 160 and the second data wiring 161 may correspond to pixels in one column. In one embodiment, the first data wiring 160 may be electrically connected to a third area (c; referring to FIG. 4) of the active pattern 110 under a pixel (N) in even-numbered column, through a fourth contact 183. In another embodiment, the second data wiring 161 may be connected to a third area (c′; referring to FIG. 4) of an active pattern 110 under a pixel (N+1) in odd-numbered column, through an eleventh contact 183.”) Consider Claim 12: Song in view of Hwang discloses the display panel according to claim 7, wherein the sub-pixel circuit comprises a source-drain conductive structure and an insulating layer stacked sequentially in a direction away from the base substrate, wherein the source-drain conductive structure is disposed between the light-emitting unit and the base substrate, and the insulating layer is disposed between the source-drain conductive structure and the light-emitting unit; (Song, See Fig. 9. [0091], [0080], [0085], “FIG. 9 illustrates a cross-sectional view illustrating an embodiment of the seventh transistor in FIG. 8. Referring to FIG. 9, this embodiment includes the active pattern 110, a gate insulating layer 118, a fifth gate electrode 140, a first insulating interlayer 145, a second insulating interlayer 159, a seventh contact 186, a ninth contact 191, a first power supply wiring 165, a third insulating interlayer 198, an electrode contact 205, a pixel electrode 200G1, an organic light emitting layer 210, a pixel defined layer 215, and a common electrode 220 on a substrate 100.”) . wherein the first connection structure comprises an adapter wire, and a first via is disposed in the insulating layer, wherein one end of the adapter wire is connected to the source-drain conductive structure through the first via in the insulating layer, and another end of the adapter wire is connected to the light-emitting unit. (Song, [0097] In one embodiment, one or more of the pixel electrodes 201G1, 201G2, 201R, and 201B may be connected to a seventh area (g, g′; referring to FIG. 10) through second connecting patterns 177 and 178, connecting portion 204R, 204G, and 204B, and/or electrode contacts 205R, 205G, and 205B.”) Consider Claim 13: Song in view of Hwang discloses the display panel according to claim 4, wherein m is 3, and the sub-pixels of three colors comprise red sub-pixels, blue sub-pixels, and green sub-pixels; and the sub-pixels in one row comprise a plurality of pixels, wherein each of the plurality of pixels comprises two green sub-pixels, one red sub-pixel, and one blue sub-pixel. (Song, [0084], [0095], [0098-0102], [0014], Hwang, [0057], [0056], “The display panel 110 may have a plurality of pixel regions PR1 and PR2, and each pixel region PR1 and PR2 may include two sub-pixel regions SPR1 and SPR2, and SPR3 and SPR4, respectively. Further, in each sub-pixel region SPR1, SPR2, SPR3 and SPR4, one OLED of G1, R1, B1 and G2 and one sub-pixel circuit of SPC1, SPC2, SPC3 and SPC4 may be disposed. ”) Consider Claim 14: Song in view of Hwang discloses the display panel according to claim 13, wherein n is 2, a first sub-pixel group among the two sub-pixel groups comprises the red sub-pixels and the blue sub-pixels, and a second sub-pixel group among the two sub-pixel groups comprises the green sub-pixels, the red sub-pixels and the blue sub-pixels are electrically connected to a first drive terminal among the two rows of the drive terminals, and the green sub-pixels are electrically connected to a second drive terminal among the two rows of the drive terminals. (Song, [0084], [0095], [0098-0102], [0014], “The pixel electrodes may include a first pixel electrode connected to one of the pixels in the even row of an even pixel column, the first pixel electrode in a first light emitting diode emitting a first color; a second pixel electrode connected to one of the pixels in the even row of an odd pixel column, the second pixel electrode in a second light emitting diode emitting a second color; a third pixel electrode connected to one of the pixels in the odd row of the even pixel column, the third pixel electrode in a third light emitting diode emitting a third color; and a fourth pixel electrode connected to one of the pixels in the odd row of the odd pixel column, the fourth pixel electrode in a fourth light emitting diode emitting a third color. The first color may be red, the second color may be blue, and the third color may be green.”) Consider Claim 15: Song in view of Hwang discloses the display panel according to claim 13, wherein each of the sub-pixels comprises the light-emitting unit and the sub-pixel circuit electrically connected to the light-emitting unit; the display panel further comprises a source-drain data signal line, wherein an orthographic projection of the source-drain data signal line on the base substrate is overlapped with an orthographic projection of at least one of a light-emitting unit of the red sub-pixel and a light-emitting unit of the blue sub-pixel on the base substrate. (Song, [0075-0083], [0077], “The first data wiring 160 and the second data wiring 161 may extend in the first direction and may be separated from each other along the second direction. The first data wiring 160 and the second data wiring 161 may correspond to pixels in one column. In one embodiment, the first data wiring 160 may be electrically connected to a third area (c; referring to FIG. 4) of the active pattern 110 under a pixel (N) in even-numbered column, through a fourth contact 183. In another embodiment, the second data wiring 161 may be connected to a third area (c′; referring to FIG. 4) of an active pattern 110 under a pixel (N+1) in odd-numbered column, through an eleventh contact 183.”) Consider Claim 18: Song in view of Hwang discloses the display panel according to claim 1, wherein the sub-pixels on the base substrate form pixels of an RGBG structure; or the sub-pixels on the base substrate form pixels of a GGRB structure. (Song, [0084], [0095], [0098-0102], [0014], Hwang, [0057], [0056], “The display panel 110 may have a plurality of pixel regions PR1 and PR2, and each pixel region PR1 and PR2 may include two sub-pixel regions SPR1 and SPR2, and SPR3 and SPR4, respectively. Further, in each sub-pixel region SPR1, SPR2, SPR3 and SPR4, one OLED of G1, R1, B1 and G2 and one sub-pixel circuit of SPC1, SPC2, SPC3 and SPC4 may be disposed. ”) Consider Claim 19: Song in view of Hwang discloses the display panel according to claim 2, wherein sub-pixel circuits and light-emitting units of the n rows of sub-pixels are arranged in n rows respectively on the base substrate, the sub-pixel circuits of the n rows are electrically connected to the light- emitting units of the n rows respectively and the sub-pixel circuits are electrically connected to the drive terminals corresponding to the sub-pixel groups where the sub-pixel circuits are disposed. (Song, [0084], [0095], [0098-0102], [0014], Hwang, [0057], [0056], “The display panel 110 may have a plurality of pixel regions PR1 and PR2, and each pixel region PR1 and PR2 may include two sub-pixel regions SPR1 and SPR2, and SPR3 and SPR4, respectively. Further, in each sub-pixel region SPR1, SPR2, SPR3 and SPR4, one OLED of G1, R1, B1 and G2 and one sub-pixel circuit of SPC1, SPC2, SPC3 and SPC4 may be disposed. ”) Consider Claim 20: Song discloses the display device, comprising: (Song, See Abstract.) a housing and a display panel, wherein the display panel is disposed on the housing; and the display panel comprises: (Song, [0028], “FIG. 1 illustrates an embodiment of pixels of an organic light emitting display device.”) a base substrate; (Song, [0056-0058], [0056], “FIGS. 4 to 8 illustrate embodiments of layouts of the pixels. Referring to FIG. 4, one layout embodiment includes a substrate, an active pattern 110, a gate insulation layer, first gate electrodes 120 and 121, second gate electrodes 125 and 126, third gate electrodes 130 and 131, fourth gate electrodes 135, and 136 and fifth gate electrodes 140 and 141.”) … n rows of drive terminals, n being greater than or equal to two; (Song, [0028], “FIG. 1 illustrates an embodiment of pixels of an organic light emitting display device. Referring to FIG. 1, the pixels include a pixel (N) in an even-numbered row (even row) in a first direction and a pixel (N+1) in an odd-numbered row (odd row).”) a plurality of sub-pixel clusters, disposed on the base substrate, (Song, [0049-0051], [0049], “FIG. 2 illustrates an embodiment of a plurality of data wirings (DATA_ODD1, DATA_ODD2, DATA_EVEN1, DATA_EVEN2) and pixels (1-1, 2-1, 3-1, 4-1, 1-2, 2-2, 3-2, 4-2). The pixels (1-1, 2-1, 3-1, 4-1, 1-2, 2-2, 3-2, 4-2) may be arranged in a first direction and a second direction perpendicular to the first direction. The pixels (1-1, 2-1, 3-1, 4-1) are arranged in a first pixel column in the first direction. The pixels (1-2, 2-2, 3-2, 4-2) are arranged in a second pixel column in the first direction. The pixel columns may be arranged along the second direction. Each of the pixels may include a plurality of transistors (TR1-TR7), an organic light emitting diode, and one or more capacitors, as described, for example, in FIG. 1.”) wherein each of the sub- pixel clusters comprises n rows of sub-pixels emitting light of m colors, the n rows of sub- pixels forming n sub-pixel groups, each of the n sub-pixel groups comprising at least one sub- pixel of at least one color, and adjacent sub-pixel groups comprising sub-pixels of different colors, (Song, [0060], “In some example embodiments, a part of the active pattern 110 corresponding to a pixel (N) in an even-numbered row may have a symmetrical shape with a part of active pattern 110 corresponding to a pixel (N+1) in odd-numbered row with respect to an axis extending in the first direction. For example, the active pattern 110 of the pixel (N) in the even-numbered row and an active pattern 110 of the pixel (N+1) in the odd-numbered row may have symmetrical shape relative to each other. Therefore, the first to seventh areas (a, b, c, d, e, f, g) of the active pattern 110 corresponding to the pixel (N) in an even-numbered row may be symmetrical to the first to seventh areas (a′, b′, c′, d′, e′, f′, g′) of the active pattern 110 corresponding to the pixel (N+1) in an odd-numbered row.”) wherein m is a number of colors of the sub-pixels, and m is greater than or equal to n the n sub-pixel groups are in correspondence with the n rows of drive terminals respectively and row numbers of the drive terminals corresponding to the sub-pixel groups comprising the sub-pixels of a same color in different sub-pixel clusters are the same, the sub-pixels in the sub-pixel groups of a Kth row are electrically connected to the drive terminals of the Kth row, 1 < K < n; and in each of the sub-pixel clusters, the sub-pixels of the same color is driven via a same row of the drive terminals. (Song, [0093-0102], [0102], “In accordance with one or more embodiments, second connecting patterns 177 and 178 and connecting portions 204R, 204G, and 204B are included and pixel electrodes 201G1 and 201G2 of green pixels may be connected to a pixel circuit in the same row. Therefore, image quality may be improved.”) Song, while implying that a gate/scan drive circuit would exist in the device as Song expressly teaches n rows of drive terminals, n being greater than or equal to two. (Song, See Fig. 1 items n and n+1) Song however does not expressly recite a drive circuit, disposed on the base substrate and comprising a plurality of drive units, wherein the plurality of drive units comprise n rows of drive terminals, n being greater than or equal to two. Hwang however teaches that it was a known technique to those having ordinary skill in the art before the effective filing date of the invention that a display panel would have gate/scan driver to drive the rows. Hwang therefore teaches a drive circuit, disposed on the base substrate and comprising a plurality of drive units, wherein the plurality of drive units comprise n rows of drive terminals, n being greater than or equal to two. (Hwang, [0055-0058], [0081-0085], [0083] The display panel 510 may have a plurality of pixel regions PR1 and PR2, and each pixel region PR1 and PR2 may include two sub-pixel regions SPR1, SPR2, SPR3 and SPR4. Further, in each sub-pixel region SPR1, SPR2, SPR3 and SPR4, one OLED G1, R1, B1 and G2 and one sub-pixel circuit SPC1, SPC2, SPC3 and SPC4 may be disposed. In the display panel 510 of FIG. 10, unlike a display panel 110 of FIG. 1, each sub-pixel circuit SPC1, SPC2, SPC3 and SPC4 may drive the OLED G1, R1, B1 and G2 in a sub-pixel region SPR1, SPR2, SPR3 and SPR4 the same as a sub-pixel region SPR1, SPR2, SPR3 and SPR4 in which the sub-pixel circuit SPC1, SPC2, SPC3 and SPC4 is disposed.”) It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide gate/scan drivers as this was a known technique in view of Hwang and would have been utilized for the purpose of having the ability of the panel to be driven under different driving conditions (e.g., different SOTs, different off period ratios, etc.) (Hwang, [0084]) Claim Rejections - 35 USC § 103 Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Song et al. U.S. Patent Application Publication No. 2016/0217744 A1 hereinafter Song and further in view of Hwang et al. U.S. Patent Application Publication No. 2019/0279563 A1 as applied to claim 15 above, and further in view of Lee et al. U.S. Patent Application Publication No. 2016/0247452 A1 hereinafter Lee. Consider Claim 16: Song in view of Hwang discloses the display panel according to claim 15, and while teaching a thin film transistor and a power line, however does not appear to specify the power line comprising a shielding block; wherein the thin film transistor is disposed on the base substrate, the power line is disposed on a side of the thin film transistor away from the base substrate, and an orthographic projection of the shielding block on the base substrate is overlapped with an orthographic projection of the thin film transistor on the base substrate; and an orthographic projection of a light-emitting unit of the green sub-pixel on the base substrate overlaps the orthographic projection of the shielding block on the base substrate. Lee however teaches that it was a known technique to those having ordinary skill in the art before the effective filing date of the invention to provide a shielding layer in connection with the power and therefore teaches the power line comprising a shielding block; wherein the thin film transistor is disposed on the base substrate, the power line is disposed on a side of the thin film transistor away from the base substrate, and an orthographic projection of the shielding block on the base substrate overlaps an orthographic projection of the thin film transistor on the base substrate; and an orthographic projection of a light-emitting unit of the green sub-pixel on the base substrate is overlapped with the orthographic projection of the shielding block on the base substrate. (Lee, [0066], [0085-0086], [0114], [0085], “As shown in FIG. 5, the first shielding electrode 172a and the second shielding electrode 172b of the driving voltage line 172 are disposed between the first data connecting member 174 connected to the driving gate electrode 155a and two data lines 171 disposed on two sides of the first data connecting member 174. The first shielding electrode 172a and the second shielding electrode 172b are connected to the driving voltage line 172 and supplied with the driving voltage ELVDD having a constant magnitude.”) It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide a shielding layer as this was a known technique as taught in Lee and would have been utilized for the purpose of interference between the data signal transmitted through the data line and the gate voltage supplied to the driving gate electrode can be prevented. (Lee, [0086]) Claim Rejections - 35 USC § 103 Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Song et al. U.S. Patent Application Publication No. 2016/0217744 A1 hereinafter Song and further in view of Hwang et al. U.S. Patent Application Publication No. 2019/0279563 A1 as applied to claim 15 above, and further in view of Li et al. U.S. Patent Application Publication No. 2022/0309981 A1 hereinafter Li. Consider Claim 17: Song in view of Hwang discloses the display panel according to claim 13, however does not appear to further specify a variation wherein n is 3, a first sub-pixel group of the three sub-pixel groups comprises the red sub-pixels, a second sub-pixel group of the three sub-pixel groups comprises the green sub-pixels, and the second sub-pixel group of the three sub-pixel groups comprises the blue sub-pixels; wherein the red sub-pixels are connected to a first drive terminal of the three drive terminals, the green sub-pixels are connected to a second drive terminal of the three drive terminals, and the blue sub-pixels are connected to a third drive terminal of the three drive terminals. Li however teaches that it was a known technique to those having ordinary skill in the art before the effective filing date of the invention to provide the same pixel colors wherein n is 3, a first sub-pixel group of the three sub-pixel groups comprises the red sub-pixels, a second sub-pixel group of the three sub-pixel groups comprises the green sub-pixels, and the second sub-pixel group of the three sub-pixel groups comprises the blue sub-pixels; wherein the red sub-pixels are connected to a first drive terminal of the three drive terminals, the green sub-pixels are connected to a second drive terminal of the three drive terminals, and the blue sub-pixels are connected to a third drive terminal of the three drive terminals. (Li, [0050-0055], [0051], “Further, different data lines are connected to red pixels R, green pixels G, and blue pixels B in an alternating way. For example, a fourth data line D4 is connected to all red pixels disposed in the fourth column of pixels, the fifth column of pixels, and a sixth column of pixels, a fifth data line D5 is connected to all green pixels disposed in the fifth column of pixels, the sixth column of pixels, and a seventh column of pixels, a sixth data line D6 is connected to all blue pixels disposed in the sixth column of pixels, the seventh column of pixels, and an eighth column of pixels, and so on. That is, all (3s+1).sup.th data lines are connected to red pixels R, all (3s+2).sup.th data lines are connected to green pixels G, and all (3s+3).sup.th data lines are connected to blue pixels B, where s is a positive integer.”) It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide pixels of a same color connected to a same gate line was a known technique as taught in Li and would have been utilized for the purpose of the problem of color deviation caused by unnormal light mixing performed on the first column of pixels and the second column of pixels are prevented. (Li, [0055]) Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Prior art made of record and not relied upon which is still considered pertinent to applicant's disclosure is cited in a current or previous PTO-892. The prior art cited in a current or previous PTO-892 reads upon the applicants claims in part, in whole and/or gives a general reference to the knowledge and skill of persons having ordinary skill in the art before the effective filing date of the invention. Applicant, when responding to this Office action, should consider not only the cited references applied in the rejection but also any additional references made of record. In the response to this office action, the Examiner respectfully requests support be shown for any new or amended claims. More precisely, indicate support for any newly added language or amendments by specifying page, line numbers, and/or figure(s). This will assist The Office in compact prosecution of this application. The Office has cited particular columns, paragraphs, and/or line numbers in the applied rejection of the claims above for the convenience of the applicant. Citations are representative of the teachings in the art and are applied to the specific limitations within each claim, however other passages and figures may apply. Applicant, in preparing a response, should fully consider the cited reference(s) in its entirety and not only the cited portions as other sections of the reference may expand on the teachings of the cited portion(s). Applicant Representatives are reminded of CFR 1.4(d)(2)(ii) which states “A patent practitioner (§ 1.32(a)(1) ), signing pursuant to §§ 1.33(b)(1) or 1.33(b)(2), must supply his/her registration number either as part of the S-signature, or immediately below or adjacent to the S-signature. The number (#) character may be used only as part of the S-signature when appearing before a practitioner’s registration number; otherwise the number character may not be used in an S-signature.” When an unsigned or improperly signed amendment is received the amendment will be listed in the contents of the application file, but not entered. The examiner will notify applicant of the status of the application, advising him or her to furnish a duplicate amendment properly signed or to ratify the amendment already filed. In an application not under final rejection, applicant should be given a two month time period in which to ratify the previously filed amendment (37 CFR 1.135(c) ). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. Granting of After Final Interviews: “Interviews merely to restate arguments of record or to discuss new limitations which would require more than nominal reconsideration or new search should be denied.” See MPEP § 713.09. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL J JANSEN II whose telephone number is (571)272-5604. The examiner can normally be reached Normally Available Monday-Friday 9am-4pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Temesghen Ghebretinsae can be reached on 571-272-3017. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Michael J Jansen II/ Primary Examiner, Art Unit 2626
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Prosecution Timeline

Jan 17, 2025
Application Filed
Nov 07, 2025
Non-Final Rejection — §103, §112
Feb 10, 2026
Response Filed
Mar 09, 2026
Final Rejection — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
66%
Grant Probability
86%
With Interview (+20.4%)
2y 3m
Median Time to Grant
Moderate
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