Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This office action is in response to Preliminary amendment communication filed on 01/17/2025. Claims 1-10 have been amended. Claims 11-17 have been added. Claims 1 – 17 are pending on this application.
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. Pub. No. 2012/0081185 in view of OTA HIROYUKI JP H11173920 (English translation attached).
Fig. 2 of Wang et al. discloses a PLL for Time Digital-convert (TDC 220).
Fig. 3 of Wang discloses diagram to TDC comprising first (delay line 310a TDC), second (delay line 310b TDC) and third (delay lines 310c TDC)
Fig. 4 of Wang discloses each delay line comprising a plurality of delay elements 512 or 514) with locking detector 516s)
Regarding claim 1, Fig. 2 of Wang et al. discloses a time-to-digital converter (220) with a fine resolution (paragraph 0007) and based on a transmission line structure (transmission line structure Fig. 3), comprising three-stage time-to-digital converters (310a, 310b, 310c in Fig. 3)) configured to identify a decimal phase difference (phase difference) between a reference clock signal FREF (Master Clock) and a feedback signal CKV (Feedback Signal) after a phase-locked loop frequency division (250), wherein the three-stage TDCs (310a, 310b, 310c in Fig. 3) are connected in parallel (parallel of 310a, 310b, 310c); each stage of the three TDCs (each stage of 310a, 310b, 310c) disposed a plurality of delay units (plurality of delay elements 512 or 514 in Fig. 4); and the delay units (plurality of delay elements 512 or 514 in Fig. 4) are connected to a locking detector (516 in Fig. 4) by wherein in an output result of each stage (Dout1, Dout2, Dout3 in Fig. 3) of the tree-stage TDCs (310a, 310b, 310c) is determined by locking detector (516 in Fig. 4) for performing locking (locking of 516 in Fig. 4).
However, Wang et al. does not disclose the fine resolution time-to-digital converter with a sub-100fs resolution.
Fig. 3 of OTA HIROYUKI discloses a time-to-digital converter (time input 30 converted to digital out by analog-to-digital converter 52) with a sub-100fs resolution (paragraph 0026 in English translation discloses” output from the A/D converter 52 contains data including the timing jitter of the sampling pulse light, and although the optical sampling system 36′ is a device capable of obtaining time resolution of 100 fs or less.
Wang et al. and OTA HIROYUKI are common subject matter of TDC; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate OTA HIROYUKI into Wang et al. for the purpose of providing a TDC device capable of obtaining time resolution of 100 fs or less (as taught by paragraph 0026 of OTA HIROYUKI).
5. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. and OTA HIROYUKI applied to claim 1 above in further view of ZHANG, CONG et al. CN 109884873 (English translation).
Wang et al. and OTA HIROYUKI applied to claim 1 above do not disclose wherein each stage of the three-stage TDCs comprises 32 comparators.
Fig. 2 ZHANG, CONG et al. discloses a TDC comprising comprises 32 comparators (Under Contents of Invention of ZHANG, CONG et al. discloses “vernier delay line TDC circuit input end; said vernier delay line TDC circuit is composed of a delay line 1 circuit; delay line 2 circuit and comparator circuit; the delay line 1 circuit is composed of 32 delay time is delta t1 and adopts delay buffer of dynamic threshold value technology; delay line 2 circuit is composed of 32 delay time is delta t2 and adopts delay buffer of dynamic threshold technology; The comparator circuit is composed of 32 differential comparators using dynamic threshold technology based on SR latches”.
Wang et al./ OTA HIROYUKI and ZHANG, CONG et al. are common subject matter of TDC; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate TDC of ZHANG, CONG et al. into each TDC of Wang et al. for the purpose of providing TDC with obtaining faster working speed and less power consumption (Under Contents of Invention of ZHANG, CONG et al. discloses” time digital converter using dynamic threshold technology, capable of identifying the time difference of the rising edge signal of two input and converting binary digital form output, under the near threshold power supply voltage, using dynamic threshold value technology; obtaining faster working speed and less power consumption”).
Allowable Subject Matter
6. Claims 2 and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art does not teach: wherein a first-stage TDC employs a single-chain delay TDC structure and comprises a plurality of buffer delay units connected in series, each of the plurality of buffer delay units comprises two complementary metal-oxide-semiconductor (CMOS) inverters, and the two CMOS inverters are connected in series; the feedback signal CKV after the phase-locked loop frequency division is transmitted in a single-chain delay chain, an output end of each of the plurality of buffer delay units is connected to [[one]]a first input end of a comparator, and a second input end of the comparator is connected to the reference clock signal FREF, to compare a sequence of rising edges of two input signals, wherein -a comparison result comprising a temperature code is produced; and the temperature code is fed to the locking detector for a lock determination, and when outputs of the comparators are all the same or less than a set value, the locking detector turns off the first-stage TDC and enters a second-stage TDC.
7. Claim 3 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art does not teach: wherein a second-stage TDC employs a double-chain delay TDC structure and comprises a plurality of buffer delay units and a plurality of comparators, the buffer delay units are connected in series to form two transmission chains, a first transmission chain inputs the feedback signal CKV after the phase-locked loop frequency division, and a second transmission chain inputs the reference clock signal FREF; and an output end of each of the plurality of buffer delay units is connected to an input end of each of the plurality of comparators, wherein each of the plurality of comparators inputs different kinds of signals to compare a sequence of rising edges of two input signals, a comparison result comprising a temperature code is produced; and after a first-stage TDC is locked, the first-stage TDC continues to discern a residual phase difference between the different kinds of signals, and when outputs of the plurality of comparators are all the same or less than a set value, outputs of the second-stage TDC is frozen, the second-stage TDC is turned off, and determining of a third-stage TDC is initiated.
8. Claims 4-8 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art does not teach: wherein a third-stage TDC comprises two transmission lines, an input end of each of the two transmission lines is connected to a buffer, wherein a first transmission line is a linear microstrip line structure, wherein the linear microstrip line structure is spliced end-to-end by a plurality of metal cuboids; a second transmission line employs a S-type microstrip line structure, that is, each of the plurality of delay units is a bent semi-octagonal body, each bent semi-octagonal body is connected end- to-end to form a long transmission line chain, the feedback signal CKV enters the S-type microstrip line structure to be transmitted, and the reference clock signal FREF enters the linear microstrip line structure to be transmitted; and comparators are connected across outputs of each of the plurality of delay units of two signal transmission chains to compare a sequence of rising edges of two input signals, thus outputting a comparison result.
9. Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art does not teach: wherein the three- stage TDCs are executed in parallel, with two input signals first entering a first-stage TDC for quantization, and when a difference between a maximum value and a minimum value output by the first-stage TDC is less than 2, the first-stage TDC is locked; determining that a next-stage TDC is performed, with a locking criteria being the same as a locking criteria of the first-stage TDC, and a phase difference between two signals gradually decreases with a locking of a phase- locked loop (PLL}, which means a phase difference alignment is performed, and the PLL completes the locking.
Contact Information
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Linh Van Nguyen whose telephone number is (571) 272-1810. The examiner can normally be reached from 8:30 – 5:00 Monday-Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Dameon E. Levi can be reached at (571) 272-2105. The fax phone numbers for the organization where this application or proceeding is assigned are (571-273-8300) for regular communications and (571-273-8300) for After Final communications.
08/11/2026
/LINH V NGUYEN/Primary Examiner, Art Unit 2845
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