DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6 and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cho et al (US 2022/0020327 A1).
Regarding claim 1, Cho discloses a method to update a section of pixel arrays [e.g., Fig. 2: section of PX arrays], the method comprising:
having a pixel array [e.g., Fig. 2: PX array] divided into
sub-array sections [e.g., Fig. 2: 1st (upper, left) section = PX (SL0-2, EML1, DL1);
2nd (upper, right) section = PX (SL5-7, EML4, DLm-1);
3rd (lower, left) section = PX (SL10-12, EML7, DL2);
4th (lower, right) section = PX (SL17-19, EML10, DLm)] including
more than one row of sections [e.g., 1st top row = top horizontal area including 1st section, 2nd section; 2nd bottom row = bottom horizontal area including 3rd section, 4th section] and
more than one column of sections [e.g., Fig. 2: 1st left column = left vertical area including 1st section, 3rd section; 2nd right column = right vertical area including 2nd section, 4th section],
wherein each section of the sub-array sections is connected to a respective set of programming signals [e.g., see Figs. 1, 3, 4:
scan/emission signals (SC0-2, EM1 for SL0-2, EML1) for the 1st section;
scan/emission signals (SC5-7, EM4 for SL5-7, EML4) for the 2nd section;
scan/emission signals (SC10-12, EM7 for SL10-12, EML7) for the 3rd section;
scan/emission signals for (SC17-19, EM10 for SL17-19, EML10) for the 4th section;
each of which is unique/independent from the others], and
wherein the respective set of programming signals corresponding to a section is activated to select that section for programming [e.g., see Figs. 1, 3, 4:
scan/emission signals (SC0-2, EM1 for SL0-2, EML1) are activated to select the 1st section (by being logic low) for programming/updating with signals D1, D1−Vth, VINT, Id, Ibp, and ELVDD – wherein programming the 1st section doesn’t program/update the other three sections;
scan/emission signals (SC5-7, EM4 for SL5-7, EML4) are activated to select the 2nd section (by being logic low) for programming/updating with signals Dm-1, Dm-1−Vth, VINT, Id, Ibp, and ELVDD – wherein programming the 2nd section doesn’t program/update the other three sections;
scan/emission signals (SC10-12, EM7 for SL10-12, EML7) are activated to select the 3rd section (by being logic low) for programming/updating with signals D2, D2−Vth, VINT, Id, Ibp, and ELVDD – wherein programming the 3rd section doesn’t program/update the other three sections;
scan/emission signals (SC17-19, EM10 for SL17-19, EML10) are activated to select the 4th section (by being logic low) for programming/updating with signals Dm, Dm−Vth, VINT, Id, Ibp, and ELVDD – wherein programming the 4th section doesn’t program/update the other three sections]; and
updating a programming data [e.g., see Figs. 2, 3:
data signal D1 for DL1 for 1st section;
data signal Dm-1 for DLm-1 for 2nd section;
data signal D2 for DL2 for 3rd section;
data signal Dm for DLm for 4th section;
each of which is independent from the others] for each section independently,
wherein data [e.g., see Figs. 2, 3: scan/emission/data signals for SL0-2, EML1, DL1 for 1st section] for updating a display [e.g., Fig. 2: DP] is indicative of at least a section [e.g., 1st section] of the sub-array sections to be updated [e.g., Fig. 6: F1-F6] with respective programming data [e.g., see Figs. 2, 3: data signal for DL1 for 1st section], and
wherein the respective set of programming signals corresponding to the at least a section includes
select signals [e.g., Figs. 2, 3: scan signals for SL0-2 for 1st section] that activate a pixel [e.g., Fig. 2: PX (SL0-2, EML1, DL1), Fig. 3: PX11] for accepting the respective programming data,
emission signals [e.g., see Figs. 2, 3: emission signals for EML1 for 1st section] that control an emission time [e.g., Fig. 4: time EMj low] and
a frame rate [e.g., Fig. 7: 120Hz, 1Hz] of the pixel (e.g., see Paragraphs 48-178).
Regarding claim 2, Cho discloses the respective set of programming signals for each section are arranged in rows [e.g., Fig. 2: SL, EML] and data lines are arranged in columns [e.g., Fig. 2: DL] (e.g., see Paragraphs 54-69).
Regarding claim 3, Cho discloses sub-array sections [e.g., 2nd, 4th sections] on a right side [e.g., Fig. 2: right side of DP] are connected to right programming signals [e.g., see Figs. 1, 3, 4: scan/emission signals for SL5-7, EML4 for 2nd section; scan/emission signals for SL17-19, EML10 for 4th section] and
sub-array sections [e.g., 1st, 3rd sections] on a left side [e.g., Fig. 2: left side of DP] are connected to left programming signals [e.g., see Figs. 1, 3, 4: scan/emission signals for SL0-2, EML1 for 1st section; scan/emission signals for SL10-12, EML7 for 3rd section] for a 2 x 2 sectional arrangement (e.g., see Paragraphs 54-69).
Regarding claim 4, Cho discloses an orientation [e.g., see Figs. 1, 3, 4: orientation of scan/emission signals (SC0-2, EM1 for SL0-2, EML1) for 1st section; orientation of scan/emission signals for (SC5-7, EM4 for SL5-7, EML4) for 2nd section; orientation of scan/emission signals for (SC10-12, EM7 for SL10-12, EML7) for 3rd section; orientation of scan/emission signals for (SC17-19, EM10 for SL17-19, EML10) for 4th section] of the respective set of programming signals for each section is different (e.g., see Paragraphs 70-85).
Regarding claim 6, Cho discloses data signals [e.g., Fig. 3: SCj; Fig. 2: DATA; Fig. 5: ECS] include biasing conditions [e.g., Paragraph 88: when the second scan signal SCj of a low level is supplied, the third transistor T3 is turned on. The first transistor T1 is diode-connected by the turned-on third transistor T3, and is biased in a forward direction], data inputs [e.g., Paragraph 57: The data driving circuit 200 receives the data control signal DCS and the image data signal DATA from the driving controller 100] and frame rates [e.g., Paragraph 69: The light emission driving circuit EDC according to an embodiment may drive light emission lines corresponding to the first display region DA1 among the light emission lines EML1 to EMLn at a first driving frequency, and may drive light emission lines corresponding to the second display region DA2 at a second driving frequency different from the first driving frequency in response to the light emission control signal ECS].
Regarding claim 8, Cho discloses each section of the sub-array sections has a different emission duty cycle [e.g., Fig. 4: EMj high/low duty cycle; Paragraph 92: the light emission driving signal EMj supplied from the light emission line EMLj during a light emission period is changed from a high level to a low level. During the light emitting period, the fifth transistor T5 and the sixth transistor T6 are turned on by the light emission driving signal EMj of a low level. Then, the driving current Id corresponding to the voltage difference between the gate voltage of the gate electrode of the first transistor T1 and the first driving voltage ELVDD is generated, and through the sixth transistor T6, the driving current Id is supplied to the light emitting diode ED such that the current Ied flows in the light emitting diode ED] for modifying brightness, power or colour of a respective section [e.g., Paragraph 4: Light with a predetermined luminance may be generated in correspondence with the amount of the current flowing through the organic light emitting diode].
Response to Arguments
Applicant's arguments filed on 10 June 2026 have been fully considered but they are not persuasive.
The Applicant contends, “Cho does not show, teach, or suggest that the respective set of programming signals corresponding to a section is activated to select that section for programming and that the respective set of programming signals corresponding to the at least a section includes select signals that activate a pixel for accepting the respective programming data, as required by the claims” (see Page 7 of the Response filed on 10 June 2026). However, the Office respectfully disagrees.
Cho discloses the respective set of programming signals [e.g., see Figs. 1, 3, 4:
scan/emission signals (SC0-2, EM1 for SL0-2, EML1) for the 1st section;
scan/emission signals (SC5-7, EM4 for SL5-7, EML4) for the 2nd section;
scan/emission signals (SC10-12, EM7 for SL10-12, EML7) for the 3rd section;
scan/emission signals for (SC17-19, EM10 for SL17-19, EML10) for the 4th section;
each of which is unique/independent from the others] corresponding to a section [e.g., Fig. 2: 1st (upper, left) section = PX (SL0-2, EML1, DL1);
2nd (upper, right) section = PX (SL5-7, EML4, DLm-1);
3rd (lower, left) section = PX (SL10-12, EML7, DL2);
4th (lower, right) section = PX (SL17-19, EML10, DLm)] is activated to select that section for programming [e.g., see Figs. 1, 3, 4:
scan/emission signals (SC0-2, EM1 for SL0-2, EML1) are activated to select the 1st section (by being logic low) for programming/updating with signals D1, D1−Vth, VINT, Id, Ibp, and ELVDD – wherein programming the 1st section doesn’t program/update the other three sections;
scan/emission signals (SC5-7, EM4 for SL5-7, EML4) are activated to select the 2nd section (by being logic low) for programming/updating with signals Dm-1, Dm-1−Vth, VINT, Id, Ibp, and ELVDD – wherein programming the 2nd section doesn’t program/update the other three sections;
scan/emission signals (SC10-12, EM7 for SL10-12, EML7) are activated to select the 3rd section (by being logic low) for programming/updating with signals D2, D2−Vth, VINT, Id, Ibp, and ELVDD – wherein programming the 3rd section doesn’t program/update the other three sections;
scan/emission signals (SC17-19, EM10 for SL17-19, EML10) are activated to select the 4th section (by being logic low) for programming/updating with signals Dm, Dm−Vth, VINT, Id, Ibp, and ELVDD – wherein programming the 4th section doesn’t program/update the other three sections]; and
wherein the respective set of programming signals corresponding to the at least a section [e.g., 1st (upper, left) section = PX (SL0-2, EML1, DL1)] includes
select signals [e.g., Figs. 2, 3: scan signals for SL0-2 for 1st section] that activate a pixel [e.g., Fig. 2: PX (SL0-2, EML1, DL1), Fig. 3: PX11] for accepting the respective programming data [e.g., see Figs. 2, 3: data signal for DL1 for 1st section] (e.g., see Paragraphs 48-178).
The Applicant contends, “The signal lines in Cho extend across multiple pixels arranged in rows and columns, such that pixels in different regions share these signal lines. Sections in Cho are associated with combinations or intersections of shared signal lines, rather than by a set of programming signals that corresponds to a particular section. Because these signal lines are shared, activation of any given signal line is not limited to a particular section and does not correspond to selecting a section for programming” (see Pages 7-8 of the Response filed on 10 June 2026). However, the Office respectfully disagrees.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., signal line(s) ) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Cho discloses the respective set of programming signals [e.g., see Figs. 1, 3, 4:
scan/emission signals (SC0-2, EM1 for SL0-2, EML1) for the 1st section;
scan/emission signals (SC5-7, EM4 for SL5-7, EML4) for the 2nd section;
scan/emission signals (SC10-12, EM7 for SL10-12, EML7) for the 3rd section;
scan/emission signals for (SC17-19, EM10 for SL17-19, EML10) for the 4th section;
each of which is unique/independent from the others] corresponding to a section [e.g., Fig. 2: 1st (upper, left) section = PX (SL0-2, EML1, DL1);
2nd (upper, right) section = PX (SL5-7, EML4, DLm-1);
3rd (lower, left) section = PX (SL10-12, EML7, DL2);
4th (lower, right) section = PX (SL17-19, EML10, DLm);
each of which is unique/independent from the others] is activated to select that section for programming [e.g., see Figs. 1, 3, 4:
scan/emission signals (SC0-2, EM1 for SL0-2, EML1) are activated to select the 1st section (by being logic low) for programming/updating with signals D1, D1−Vth, VINT, Id, Ibp, and ELVDD – wherein programming the 1st section doesn’t program/update the other three sections;
scan/emission signals (SC5-7, EM4 for SL5-7, EML4) are activated to select the 2nd section (by being logic low) for programming/updating with signals Dm-1, Dm-1−Vth, VINT, Id, Ibp, and ELVDD – wherein programming the 2nd section doesn’t program/update the other three sections;
scan/emission signals (SC10-12, EM7 for SL10-12, EML7) are activated to select the 3rd section (by being logic low) for programming/updating with signals D2, D2−Vth, VINT, Id, Ibp, and ELVDD – wherein programming the 3rd section doesn’t program/update the other three sections;
scan/emission signals (SC17-19, EM10 for SL17-19, EML10) are activated to select the 4th section (by being logic low) for programming/updating with signals Dm, Dm−Vth, VINT, Id, Ibp, and ELVDD – wherein programming the 4th section doesn’t program/update the other three sections].
The Applicant contends, “Cho does not disclose that the respective set of programming signals corresponding to a section includes select signals that activate a pixel for accepting programming data, as required by the claims. The present specification explicitly defines that programming signals include select signals that perform this function. However, in Cho, the scan signals that control pixel operation are applied along shared scan lines that extend across multiple pixels and regions and are not disclosed as being included within a respective set of programming signals corresponding to a section” (see Page 8 of the Response filed on 10 June 2026). However, the Office respectfully disagrees.
Firstly, again, in response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., signal line(s) in any sort of arrangement) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Secondly, the instant specification uses the term “programming” interchangeably with term “updating.” Specification Paragraphs 12-13 state, “The power consumption associated with the optoelectronic array comes from the power associated with the pixel function and updating/programming the pixel value or reading the pixel sensing value. To reduce the power associated with the updating/programming, one can reduce the frequency of the updates when possible. However, in this case, the entire array is still updated during each update cycle.”
Thirdly, Cho discloses the respective set of programming signals [e.g., see Figs. 1, 3, 4: scan/emission signals (SC0-2, EM1 for SL0-2, EML1) are activated to select the 1st section (by being logic low) for programming/updating with signals D1, D1−Vth, VINT, Id, Ibp, and ELVDD – wherein programming the 1st section doesn’t program/update the other three sections] corresponding to the at least a section [e.g., 1st (upper, left) section = PX (SL0-2, EML1, DL1)] includes
select signals [e.g., Figs. 2, 3: scan signals for SL0-2 for 1st section] that activate a pixel [e.g., Fig. 2: PX (SL0-2, EML1, DL1), Fig. 3: PX11] for accepting the respective programming data [e.g., see Figs. 2, 3: data signal for DL1 for 1st section] (e.g., see Paragraphs 48-178).
The Applicant contends, “Even if Cho discloses scan signals that activate pixels, such signals are not organized or used as part of a respective set of programming signals corresponding to a section that is activated to select that section for programming. Cho therefore does not disclose that the respective set of programming signals corresponding to a section is activated to select that section for programming and that the respective set of programming signals corresponding to the at least a section includes select signals that activate a pixel for accepting the respective programming data, as required by the claims” (see Page 8 of the Response filed on 10 June 2026). However, the Office respectfully disagrees.
Cho discloses the respective set of programming signals [e.g., see Figs. 1, 3, 4:
scan/emission signals (SC0-2, EM1 for SL0-2, EML1) for the 1st section;
scan/emission signals (SC5-7, EM4 for SL5-7, EML4) for the 2nd section;
scan/emission signals (SC10-12, EM7 for SL10-12, EML7) for the 3rd section;
scan/emission signals for (SC17-19, EM10 for SL17-19, EML10) for the 4th section;
each of which is unique/independent from the others] corresponding to a section [e.g., Fig. 2: 1st (upper, left) section = PX (SL0-2, EML1, DL1);
2nd (upper, right) section = PX (SL5-7, EML4, DLm-1);
3rd (lower, left) section = PX (SL10-12, EML7, DL2);
4th (lower, right) section = PX (SL17-19, EML10, DLm)] is activated to select that section for programming [e.g., see Figs. 1, 3, 4:
scan/emission signals (SC0-2, EM1 for SL0-2, EML1) are activated to select the 1st section (by being logic low) for programming/updating with signals D1, D1−Vth, VINT, Id, Ibp, and ELVDD – wherein programming the 1st section doesn’t program/update the other three sections;
scan/emission signals (SC5-7, EM4 for SL5-7, EML4) are activated to select the 2nd section (by being logic low) for programming/updating with signals Dm-1, Dm-1−Vth, VINT, Id, Ibp, and ELVDD – wherein programming the 2nd section doesn’t program/update the other three sections;
scan/emission signals (SC10-12, EM7 for SL10-12, EML7) are activated to select the 3rd section (by being logic low) for programming/updating with signals D2, D2−Vth, VINT, Id, Ibp, and ELVDD – wherein programming the 3rd section doesn’t program/update the other three sections;
scan/emission signals (SC17-19, EM10 for SL17-19, EML10) are activated to select the 4th section (by being logic low) for programming/updating with signals Dm, Dm−Vth, VINT, Id, Ibp, and ELVDD – wherein programming the 4th section doesn’t program/update the other three sections]; and
wherein the respective set of programming signals corresponding to the at least a section [e.g., 1st (upper, left) section = PX (SL0-2, EML1, DL1)] includes
select signals [e.g., Figs. 2, 3: scan signals for SL0-2 for 1st section] that activate a pixel [e.g., Fig. 2: PX (SL0-2, EML1, DL1), Fig. 3: PX11] for accepting the respective programming data [e.g., see Figs. 2, 3: data signal for DL1 for 1st section] (e.g., see Paragraphs 48-178).
Applicant's arguments with respect to claims 1-4, 6 and 8 have been considered but are moot in view of any new ground(s) of rejection.
Conclusion
Applicant's amendment necessitated any new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeff Piziali whose telephone number is (571)272-7678. The examiner can normally be reached on Monday - Friday (7:30AM - 4PM). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Jeff Piziali/
Primary Examiner, Art Unit 2628
2 July 2026
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