DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 3, 5, 6, 8, 10-13 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species A-G, I and J and Subspecies I and III-V, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 1/23/2026.
Applicant’s election without traverse of Species H and Subspecies II drawn to claims 1, 2, 4, 7, 9 and 14-20 in the reply filed on 1/23/2026 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 20 is indefinite as it claims both an apparatus and a method within the same claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4, 7, 18 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Pub. No. 2022/0130311 A1 to Zhao et al.
As to claim 1, Zhao discloses a pixel circuit, comprising a driving circuit, a data-writing circuit, a data-writing control circuit and a light-emitting element; wherein
the driving circuit is configured to drive the light-emitting element to emit light (Fig. 2, paragraph 0030, where driving transistor (T1) is the driving circuit which drives light-emitting element (D1));
the data-writing circuit is coupled to a control end, a data line and a first end of the driving circuit, and is configured to control a connection or disconnection between the data line and the first end of the driving circuit under a control of a control signal provided by the control end (Fig. 2, paragraph 0030, where data-writing transistor (T2) is connected to data line (Vdata), driving transistor (T1) and scan line (Scan3));
the data-writing control circuit is coupled to the control end and is configured to control the control signal to control whether the data-writing circuit writes a data voltage provided by the data line into the first end of the driving circuit under the control of the control signal (Fig. 2, paragraph 0030, where scan line (Scan3) controls data-writing transistor (T2)).
As to claim 2, Zhao discloses the pixel circuit, wherein the data-writing control circuit is further coupled to the data line and a scanning end, and is configured to control the control signal according to a scanning signal provided by the scanning end under a control of the data voltage provided by the data line (Fig. 2, paragraph 0030, where data-writing transistor (T2) is connected to data line (Vdata) and scan line (Scan3)).
As to claim 4, Zhao discloses the pixel circuit, wherein the data-writing control circuit is further coupled to a first node, and is configured to control a connection or disconnection between the scanning end and the first node under the control of the data voltage, and control the control signal according to a potential of the first node (Fig. 2, paragraph 0030, where data-writing transistor (T2) is connected to a node as shown in the figure).
As to claim 7, Zhao discloses the pixel circuit, further comprising a compensation control circuit; wherein
the compensation control circuit is coupled to the control end, a control end of the driving circuit and a second end of the driving circuit, and is configured to control a connection or disconnection between the control end of the driving circuit and the second end of the driving circuit under a control of a control signal provided by the control end (Fig. 2, paragraph 0030, where compensation transistor (T3) is connected to scan line (Scan1) and the gate and one end of driving transistor (T1)).
As to claim 18, Zhao discloses a display substrate, comprising the pixel circuit (Fig. 9, paragraph 0068, display panel (10), pixel circuit (100)).
As to claim 19, Zhao discloses a display device, comprising the display substrate (Fig. 9, paragraph 0068, display panel (10)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Pub. No. 2022/0130311 A1 to Zhao et al. in view of U.S. Patent Pub. No. 2021/0358407 A1 to Xu et al.
As to claim 14, Zhao discloses the pixel circuit, further comprising a first light-emitting control circuit, a second light-emitting control circuit, an energy storage circuit;
the first light-emitting control circuit is coupled to a light-emitting control end, a first voltage line and the first end of the driving circuit, and is configured to control the connection or disconnection between the first voltage line and the first end of the driving circuit under a control of the light-emitting control signal provided by the light-emitting control end (Fig. 2, paragraphs 0030-0032, where the first light-emitting control circuit is transistor (T5) and it is connected to voltage (Vdd), driving transistor (T1) and signal input terminal (EM1));
the second light-emitting control circuit is coupled to the light-emitting control end, a second end of the driving circuit and the first electrode of the light-emitting element, and is configured to control the connection or disconnection between the second end of the driving circuit and the first electrode of the light-emitting element under the control of the light-emitting control signal (Fig. 2, paragraphs 0030-0032, where the second light-emitting control circuit is transistor (T6) and it is connected to light-emitting element (D1), driving transistor (T1) and signal input terminal (EM2));
the energy storage circuit is coupled to the control end of the driving circuit and is configured to maintain the potential of the control end of the driving circuit (Fig. 2, paragraph 0067, where storage capacitor (Cst) is connected to driving transistor (T1));
a second electrode of the light-emitting element is coupled to a second voltage line (Fig. 2, paragraph 0031, where light-emitting element (D1) is connected to voltage (Vss));
the driving circuit is configured to generate a driving current for driving the light-emitting element under the control of the potential of the control end (Fig. 2, paragraph 0030, where driving transistor (T1) generates a driving current to drive light-emitting element (D1)).
Zhao is deficient in disclosing the pixel circuit, further comprising a first initialization circuit;
the first initialization circuit is coupled to the first reset end, a first initialization voltage end and the control end of the driving circuit, and is configured to write a first initialization voltage provided by the first initialization voltage end into the control end of the driving circuit under a control of a first reset signal provided by the first reset end.
However, Xu discloses the pixel circuit, further comprising a first initialization circuit (Fig. 11, paragraph 0114, where transistor (T6) is the first initialization circuit);
the first initialization circuit is coupled to the first reset end, a first initialization voltage end and the control end of the driving circuit, and is configured to write a first initialization voltage provided by the first initialization voltage end into the control end of the driving circuit under a control of a first reset signal provided by the first reset end (Fig. 11, paragraphs 0102-0114, where transistor (T6) is coupled to reset control line (17), initialization voltage (Vint) and driving transistor (T1)).
At the time of filing, it would have been obvious to a person of ordinary skill in the art to have modified the pixel circuit as taught by Zhao by including an initialization circuit as taught by Xu. The suggestion/motivation would have been in order to reset the pixel circuit (Xu, paragraph 0093).
As to claim 15, Zhao is deficient in disclosing the pixel circuit, further comprising a second initialization circuit;
the second initialization circuit is coupled to the second reset end, a second initialization voltage end and the first electrode of the light-emitting element, and is configured to write a second initialization voltage provided by the second initialization voltage end into the first electrode of the light-emitting element under a control of a second reset signal provided by the second reset end.
However, Xu discloses the pixel circuit, further comprising a second initialization circuit (Fig. 11, paragraph 0102, where the second initialization circuit is transistor (T7));
the second initialization circuit is coupled to the second reset end, a second initialization voltage end and the first electrode of the light-emitting element, and is configured to write a second initialization voltage provided by the second initialization voltage end into the first electrode of the light-emitting element under a control of a second reset signal provided by the second reset end (Fig. 11, paragraphs 0102-0114, where transistor (T7) is connected to reset control line (17), initialization voltage (Vint) and light-emitting diode (20)). In addition, the same motivation is used as claim 14.
As to claim 16, Zhao discloses the pixel circuit, wherein the driving circuit comprises a third transistor, the data-writing circuit comprises a fourth transistor, the first light-emitting control circuit comprises a fifth transistor, the second light-emitting control circuit comprises a sixth transistor, the compensation control circuit comprises a seventh transistor, and the energy storage circuit comprises a storage capacitor;
a gate of the third transistor is coupled to the control end of the driving circuit, a first electrode of the third transistor is coupled to the first end of the driving circuit, and a second electrode of the third transistor is coupled to the second end of the driving circuit (Fig. 2, paragraph 0030, where transistor (T1) is the driving circuit);
a gate of the fourth transistor is coupled to the control end, a first electrode of the fourth transistor is coupled to the data line, and a second electrode of the fourth transistor is coupled to the first electrode of the third transistor (Fig. 2, paragraph 0030, where transistor (T2) is the data-writing circuit);
a gate of the fifth transistor is coupled to the light-emitting control end, a first electrode of the fifth transistor is coupled to the first voltage line, and a second electrode of the fifth transistor is coupled to the first electrode of the third transistor (Fig. 2, paragraphs 0030-0032, where the first light-emitting control circuit is transistor (T5));
a gate of the sixth transistor is coupled to the light-emitting control end, a first electrode of the sixth transistor is coupled to the second electrode of the third transistor, and a second electrode of the sixth transistor is coupled to the first electrode of the light-emitting element (Fig. 2, paragraphs 0030-0032, where the second light-emitting control circuit is transistor);
a gate of the seventh transistor is coupled to the control end, a first electrode of the seventh transistor is coupled to the gate of the third transistor, and a second electrode of the seventh transistor is coupled to the second electrode of the third transistor (Fig. 2, paragraph 0030, where compensation transistor (T3));
a first end of the storage capacitor is electrically connected to the gate of the third transistor, and a second end of the storage capacitor is electrically connected to the first voltage line (Fig. 2, paragraph 0067, where storage capacitor (Cst) is connected to driving transistor (T1)).
Zhao is deficient in disclosing the data-writing circuit comprising the first initialization circuit comprises an eight transistor;
a gate of the eighth transistor is coupled to the first reset end, a first electrode of the eighth transistor is coupled to the first initialization voltage end, and a second electrode of the eighth transistor is coupled to the gate of the third transistor.
However, Xu discloses the data-writing circuit comprising the first initialization circuit comprises an eight transistor (Fig. 11, paragraph 0114, where transistor (T6) is the first initialization circuit);
a gate of the eighth transistor is coupled to the first reset end, a first electrode of the eighth transistor is coupled to the first initialization voltage end, and a second electrode of the eighth transistor is coupled to the gate of the third transistor (Fig. 11, paragraphs 0102-0114, where transistor (T6) is coupled to reset control line (17), initialization voltage (Vint) and driving transistor (T1)). In addition, the same motivation is used as claim 14.
As to claim 17, Zhao is deficient in disclosing the pixel circuit, wherein the second initialization circuit comprises a ninth transistor;
a gate of the ninth transistor is coupled to the second reset end, a first electrode of the ninth transistor is coupled to the second initialization voltage end, and a second electrode of the ninth transistor is coupled to the first electrode of the light-emitting element.
However, Xu discloses the pixel circuit, wherein the second initialization circuit comprises a ninth transistor (Fig. 11, paragraph 0102, where transistor (T7) is the transistor);
a gate of the ninth transistor is coupled to the second reset end, a first electrode of the ninth transistor is coupled to the second initialization voltage end, and a second electrode of the ninth transistor is coupled to the first electrode of the light-emitting element (Fig. 11, paragraph 0102, where transistor (T7) is connected to reset control signal line (17), initialization voltage (Vint) and light-emitting diode (20)). In addition, the same motivation is used as claim 14.
Allowable Subject Matter
Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record alone, or in combination, fail to teach, disclose, or render obvious, “wherein the data-writing control circuit comprises a first transistor and a first capacitor; a gate of the first transistor is coupled to the data line, a first electrode of the first transistor is coupled to the scanning end, and a second electrode of the first transistor is coupled to the first node; a first end of the first capacitor is coupled to the first node, and a second end of the first capacitor is coupled to the control end”, in combination with the other limitations set forth in claim 9.
Claim 20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record alone, or in combination, fail to teach, disclose, or render obvious, “wherein the display area of the display device comprises a low refresh rate display area; the low refresh rate display area corresponds to at least one corresponding non-refresh display period; the at least one non-refresh display period is comprised in the display time; the display driving method comprises: in the low refresh rate display area, during the data-writing phase included in the non-refresh display period, the data-writing control circuit controlling the data-writing circuit to stop writing the data voltage into the first end of the driving circuit under the control of the control signal”, in combination with the other limitations set forth in claim 20.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANEETA YODICHKAS whose telephone number is (571)272-9773. The examiner can normally be reached Monday-Friday 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at 571-272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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ANEETA YODICHKAS
Primary Examiner
Art Unit 2627
/ANEETA YODICHKAS/ Primary Examiner, Art Unit 2627
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