DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
2. 35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 31 and 32 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claims does/do not fall within at least one of the four categories of patent eligible subject matter because the claims recite the limitation “computer-readable storage medium” however in paragraph 97, the specification recites “computer-readable storage media, which may be non-transitory”. The specification defines the medium in a manner which under BRI may also include transitory media, so Examiner suggests a correction reflect “non-transitory computer-readable storage medium”.
Claim Rejections - 35 USC § 103
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 13 – 32 are rejected under 35 U.S.C. 103 as being unpatentable over Bishara et al. (US Patent Number 9,898,431, hereinafter “Bishara”) in view of Magro et al. (US Publication Number 2018/0018105, hereinafter “Magro”).
5. As per claims 13, 18, 20, 25, 27, 29, and 31, Bishara teaches a data access device, system, system on a chip, method, apparatus, and medium for an SRAM array (memory 105, figure 1), the SRAM array comprising M SRAM groups (super banks 240/250, figure 2), the device comprising: M arbitration modules (bank arbiters 294/295, figure 2), each of which is coupled with one of the M SRAM groups; and a parsing module (distributor 231(A), figure 2), coupled with the M arbitration modules (memory includes super banks 140 and 150 as higher level banks and mini banks 141-148 and 151-158 as lower level banks, the array of memory cells being implemented in SRAM, column 5, line 19, the memory includes a first bank arbiter 294 coupled to mux’s 261-268 of first superbank 240 and a second arbiter 295 coupled to mux’s 271-278 of second super bank 250, figure 2), each access command being a read command or a write command (memory access circuit blocks 120a…d generate memory access requests, read/write, where figure 2 shows writes driving the distributors and figure 5 showing the reads driving the distributors) and directed to one SRAM group (read/writes data of first width from on fog the first level memory banks the access circuit provides it to the interface blocks 130a…d, figure 1), and send the respective access command to the arbitration module coupled with the SRAM group to which the respective access command is directed (interface circuit splits each data piece request into sub-requests of same width as a minibank, column 6, lines 7 – 10, the data to be written to super bank 240 to buffers 232a and 250 to 233a, figure 2, ), wherein each of the M arbitration modules is configured to: in response to a determination of receiving one access command directed to the respective SRAM group (each mini bank 2410248 and 251-258 coupled to mux to select an interface 230a/b where bank arbiter 294 provides select signal to mux 261 to select interface circuit coupling 230a to 241, where the select signal is the determination of which received sub-request is directed to that group), send the one access command directed to the respective SRAM group to the respective SRAM group (column 10, lines 17 – 24), so that the one access command is executed by the respective SRAM group (write to mini bank writes 16 bytes in a clock cycle and reads 16 bytes back, the client and bank arbiters providing TDM signals to store the buffered sub-units, step S340, figure 3, column 9, lines 50 – 55), wherein M is a positive integer greater than or equal to 2 (memory 205 includes 2 super banks 240/250, figure 2) and N is a positive integer (device 100,m figure 1 includes a plurality of memory access circuit blocks 120a…d thereby N=4 and is not limited to just that number).
Bishara does not appear to explicitly disclose configured to receive N data access requests in parallel, parse at least one access command from each of the N data access requests.
However, Magro discloses configured to receive N data access requests in parallel (address generator 522, figure 5), parse at least one access command from each of the N data access requests (CPU core complex 210 includes CPU cores 212 and 214 to provide memory access request to data fabric 250, paragraph 21, address generator 522 decodes address of memory access requests received from data fabric 250 over the bus into a format including column address, bank address, bank group and command queue 520 stores the address fields so decoded together with access type of QOS identifiers, paragraph 34, figure 5).
Bishara and Magro are analogous art because they are from the same field of endeavor of memory access arbitration.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Bishara and Magro before him or her, to modify the structure of Bishara to include the parallel function of Magro because it would enhance read/write request processing.
One of ordinary skill would be motivated to make such modification in order to enhance memory access efficiency, paragraph 3. Therefore, it would have been obvious to combine Magro with Bishara to obtain the invention as specified in the instant claims.
6. Bishara modified by the teachings of Magro as seen in claim 13 above, as per claims 14, 19, 21, 26, 28, 30, and 32, Bishara teaches a device, system, system on a chip, method, apparatus, and medium wherein: each of the arbitration modules is further configured to: in response to a determination of receiving at least two access commands directed to the respective SRAM group (super bank 240, figure 2), determine an execution order of the at least two access commands based on a predetermined arbitration strategy (TDM performed by arbitration circuitry 190, bank arbiters 294 and 295, figures 1 and 2), and send the at least two access commands to the respective SRAM group in sequence according to the execution order, so that the at least two access commands are executed by the respective SRAM group in sequence (arbitration circuitry 190 arbitrates the write and read operations according to TDM and allows one memory client to sequentially access eight mini banks in a super bank in subsequent eight memory access cycles to perform a full memory access to the super bank, column 7, lines 30 – 60, interface block 230a sequentially access mini banks 241 – 248 in eight different clock cycles, figure 4, column 10, lines 51 – 63).
7. Bishara modified by the teachings of Magro as seen in claim 13 above, as per claims 15 and 22, Bishara teaches a device and system on a chip, wherein the arbitration strategy comprises at least one of: a polling execution strategy; a read command priority strategy; a write command priority strategy (arbitration circuitry 190 for read/write operations, figures 2 and 5); and a time division strategy (TDM, column 6, line 18).
8. Bishara modified by the teachings of Magro as seen in claim 13 above, as per claims 16 and 23, Magro teaches a device and system on a chip, wherein: the parsing module (address generator 522, figure 5) is further configured to receive the N data access requests in parallel from a full-duplex data transmission bus (AXI4 bus, figure 5), wherein the full-duplex data transmission bus comprises at least one of: the Advanced Extensible Interface Protocol-simplified version; the Advanced Extensible Interface Protocol-Full Edition; and the Advanced Extensible Interface Protocol-Streaming Edition (paragraphs 33 and 39, interface 512 has connection to fabric 250 over AXI bus, figures 2 and 5).
9. Bishara modified by the teachings of Magro as seen in claim 13 above, as per claims 17 and 24, Magro teaches a device and system on a chip, wherein: the read command comprises a first group selection signal (sub-channel number SC, field 612, figure 6) and a read control instruction (access type command queue 520, figure 5), wherein the first group selection signal is used for selecting a corresponding SRAM group in a read operation, and the read control instruction is used for reading data in the corresponding SRAM group; the write command comprises a second group selection signal and a write control instruction, wherein the second group selection signal is used for selecting a corresponding SRAM group in a write operation, and the write control instruction is used for writing data in the corresponding SRAM group; the arbitration module (arbiter 538, figure 6) comprises: a read command group selection signal input end, configured to receive the first group selection signal; a read control instruction input end, configured to receive the read control instruction; an arbitration strategy input end (configuration registers 562, figure 5), configured to receive an arbitration strategy selection signal; a write command group selection signal input end, configured to receive the second group selection signal; a write control instruction input end, configured to receive the write control instruction; a command output end (dispatch queue 514, selector 620, figure 6), configured to send a read control command or a write control command to a corresponding SRAM group; a read state indication signal output end, configured to output a read state indication signal to a corresponding SRAM group; and a write state indication signal output end, configured to output a write state indication signal to a corresponding SRAM group (command queue 520 stores the decoded memory access request in and entry 610 having a first field 612 for the decoded sub-channel number and a second field 614 for the remainder of the decoded request, paragraph 42, command queue 520 stores address fields decoded by 522 via QOS, paragraph 34, registers 562 programmed over AXI bus and store configuration information for operation of block in memory 500, paragraph 39, queue 514 sends requests to sub-channel and selector 620 handles SC bit 612, paragraph 45, figures 5 and 6).
Conclusion
10. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ban/Coon/Doidge/Kim/Parsons/Lavelle has teaching of SRAM handling techniques utilizing AXI.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AURANGZEB HASSAN whose telephone number is (571)272-8625. The examiner can normally be reached 7 AM to 3 PM.
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AH
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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