DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . The preliminary amendment filed 01/17/2025 is entered. All the claims have been examined on the basis of the merit of the claims.
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. The present application is a 371 of PCT/CN2022116253 filed 08/31/2022.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/17/2025, 07/16/2025 & 12/19/2025 are considered and attached.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 22 is/are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by KIM et al. (US-20220223112-A1, hereinafter as, KIM).
Claim interpretations: The claims are given broadest reasonable interpretations, MPEP 2111. The terms “connected to,” and “coupled to” are interpreted throughout this office action as an indirect electrical connection unless otherwise expressly recited as direct electrical connection. Transitional terms such as “comprising” are interpreted to be open ended inclusion, MPEP 2111.03. Terms marked in [] need grammatical corrections, if any. No claim objections have been made for grammatical issues.
In regard to claim 1, KIM discloses a display panel (fig.1, display panel 100, para 0040), comprising: a substrate (inherently present in the display panel 100 on which); and a pixel driving circuit on a side of the substrate, the pixel driving circuit (the pixel driving circuit of fig. 7 is disposed. Referring fig. 7:) comprising: a driver transistor (T1, para 0015, para 0058, ); a ninth transistor, a first electrode of the ninth transistor being connected to a third initial signal line, and a second electrode of the ninth transistor being connected to a first electrode of the driver transistor (T9 and either of source/drain of T9 connected to VINTCOM, the other of source/drain connected to either of source/drain of T5); an eighth transistor, a first electrode of the eighth transistor being connected to a gate of the driver transistor (T8, either of source/drain of T8 of connected to the gate of T1); a first transistor, a first electrode of the first transistor being connected to a first initial signal line, and a second electrode of the first transistor being connected to a second electrode of the eighth transistor (T4 as the first transistor, either of source/drain connected to V1; the other of source/drain of T4 connected to other of source/drain of T8); and a second transistor, a first electrode of the second transistor being connected to the second electrode of the eighth transistor, and a second electrode of the second transistor being connected to a second electrode of the driver transistor (T3 as second electrode. Either of source/drain of T3 connected to the other of source/drain of T8; the other of source/drain of T3 connected other of source/drain of T1).
In regard to claim 22, KIM discloses a display device, comprising the display panel according to claim 1 (fig.1).
Allowable Subject Matter
Claims 2-14 and 16-20 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Kim does not disclose all the limitations of these claims “as a whole.”
2. (Original) The display panel according to claim 1, further comprising: a first active layer on a side of the substrate, the first active layer comprising: a second active portion configured to form a channel region of the second transistor, and a third active portion configured to form a channel region of the driver transistor; a first conductive layer on a side, away from the substrate, of the first active layer, the first conductive layer comprising: a first gate line, wherein an orthographic projection of the first gate line on the substrate extends in a first direction and covers an orthographic projection of the second active portion on the substrate, and a portion of a structure of the first gate line is configured to form a gate of the second transistor; and a first conductive portion, wherein an orthographic projection of the first conductive portion on the substrate covers an orthographic projection of the third active portion on the substrate, and the first conductive portion is configured to form the gate of the driver transistor; a second active layer on a side, away from the substrate, of the first conductive layer, the second active layer comprising an eighth active portion configured to form a channel region of the eighth transistor; and a third conductive layer on a side, away from the substrate, of the second active layer, the third conductive layer comprising a second gate line, wherein an orthographic projection of the second gate line on the substrate extends in the first direction and covers an orthographic projection of the eighth active portion on the substrate, and a portion of a structure of the second gate line is configured to form a top gate of the eighth transistor; wherein the orthographic projection of the first gate line on the substrate is between the orthographic projection of the second gate line on the substrate and the orthographic projection of the first conductive portion on the substrate.
Claims 3-5 depend on claim 2.
6. (Original) The display panel according to claim 1, wherein the pixel driving circuit further comprises a fourth transistor, a first electrode of the fourth transistor being connected to a data line, and a second electrode of the fourth transistor being connected to the first electrode of the driver transistor (T5 of Kim); wherein the display panel further comprises: a first active layer comprising a second active portion and a fourth active portion, wherein the second active portion is configured to form a channel region of the second transistor, and the fourth active portion is configured to form a channel region of the fourth transistor; and a second active layer on a side, away from the substrate, of the first active layer, the second active layer comprising an eighth active portion configured to form a channel region of the eighth transistor; wherein, in the first direction, an orthographic projection of the eighth active portion on the substrate is between an orthographic projection of the second active portion on the substrate and an orthographic projection of the fourth active portion on the substrate.
7. (Currently Amended) The display panel according to claim 1, further comprising a light-emitting unit, wherein the pixel driving circuit is connected to a first electrode of the light-emitting unit, and the pixel driving circuit further comprises a seventh transistor, a first electrode of the seventh transistor being connected to a second initial signal line, and a second electrode of the seventh transistor being connected to the a first electrode of the light-emitting unit (T7 of Kim); and wherein the display panel further comprises: a first active layer on a side of the substrate, the first active layer comprising a seventh active portion and a ninth active portion, wherein the seventh active portion is configured to form a channel region of the seventh transistor, and the ninth active portion is configured to form a channel region of the ninth transistor; and a first conductive layer on a side, away from the substrate, of the first active layer, the first conductive layer comprising a second reset signal line, wherein an orthographic projection of the second reset signal line on the substrate extends in a first direction and covers an orthographic projection of the seventh active portion on the substrate and an orthographic projection of the ninth active portion on the substrate, and a portion of a structure of the second reset signal line is configured to form a gate of the seventh transistor, and another portion of the structure of the second reset signal line is configured to form a gate of the ninth transistor.
Claim 8 depend on claim 7.
9. (Original) The display panel according to claim 1, further comprising: a first conductive layer on a side of the substrate, the first conductive layer comprising a first reset signal line and a first conductive portion, wherein a portion of a structure of the first reset signal line is configured to form a gate of the first transistor, and the first conductive portion is configured to form the gate of the driver transistor; a second conductive layer on a side, away from the substrate, of the first conductive layer, the second conductive layer comprising the third initial signal line; and a third conductive layer on a side, away from the substrate, of the second conductive layer, the third conductive layer comprising a second gate line, wherein a portion of a structure of the second gate line is configured to form a top gate of the eighth transistor; wherein, in a same said pixel driving circuit, an orthographic projection of the first reset signal line on the substrate is on a side, away from an orthographic projection of the first conductive portion on the substrate, of an orthographic projection of the second gate line on the substrate; and an orthographic projection, on the substrate, of the third initial signal line in the pixel driving circuit of an adjacent previous row is between the orthographic projection, on the substrate, of the first reset signal line in the pixel driving circuit of a current row and the orthographic projection, on the substrate, of the second gate line in the pixel driving circuit of the current row.
10. (Currently Amended) The display panel according to claim 1, further comprising a light-emitting unit, wherein the pixel driving circuit is connected to a first electrode of the light-emitting unit, and the pixel driving circuit further comprises a seventh transistor, a first electrode of the seventh transistor being connected to a second initial signal line, and a second electrode of the seventh transistor being connected to the a first electrode of the light-emitting unit; wherein the display panel further comprises: a first conductive layer on a side of the substrate, the first conductive layer comprising a first conductive portion, a second reset signal line, and a first gate line, wherein the first conductive portion is configured to form the gate of the driver transistor, a portion of a structure of the second reset signal line is configured to form a gate of the seventh transistor, and a portion of a structure of the first gate line is configured to form a gate of the second transistor; and a third conductive layer on a side, away from the substrate, of the first conductive layer, the third conductive layer comprising the first initial signal line; wherein, in a same pixel driving circuit, an orthographic projection of the second reset signal line on the substrate is on a side, away from an orthographic projection of the first gate line on the substrate, of an orthographic projection of the first conductive portion on the substrate; and an orthographic projection, on the substrate, of the first initial signal line in the pixel driving circuit of an adjacent next row is between the orthographic projection, on the substrate, of the second reset signal line in the pixel driving circuit of a current row and the orthographic projection, on the substrate, of the first conductive portion in the pixel driving circuit of the current row.
11. (Original) The display panel according to claim 1, wherein the pixel driving circuit further comprises a fifth transistor, a first electrode of the fifth transistor being connected to a power line, and a second electrode of the fifth transistor being connected to the first electrode of the driver transistor; wherein the display panel further comprises: a first active layer on a side of the substrate, the first active layer comprising a fifth active portion configured to form a channel region of the fifth transistor; a first conductive layer on a side, away from the substrate, of the first active layer, the first conductive layer comprising an enable signal line, wherein an orthographic projection of the enable signal line on the substrate extends in a first direction and covers an orthographic projection of the fifth active portion on the substrate, and a portion of a structure of the enable signal line is configured to form a gate of the fifth transistor; and a third conductive layer on a side, away from the substrate, of the first conductive layer, the third conductive layer comprising the first initial signal line; and wherein an orthographic projection, on the substrate, of the first initial signal line in the pixel driving circuit of an adjacent next row is at least partially overlapped with the orthographic projection, on the substrate, of the enable signal line in the pixel driving circuit of a current row.
12. (Original) The display panel according to claim 11, wherein, in a first unit pixel, an area of the orthographic projection, on the substrate, of the first initial signal line in the pixel driving circuit of the adjacent next row is S1; in the first unit pixel, an overlapping area, between the orthographic projection, on the substrate, of the first initial signal line in the pixel driving circuit of the adjacent next row and the orthographic projection, on the substrate, of the enable signal line in the pixel driving circuit of the current row, is S2; andS2/S 1 is greater than or equal to 60%.
13. (Currently Amended) The display panel according to claim 1, further comprising a light-emitting unit, wherein the pixel driving circuit is connected to a first electrode of the light-emitting unit, and the pixel driving circuit further comprises a seventh transistor, a first electrode of the seventh transistor being connected to a second initial signal line, and a second electrode of the seventh transistor being connected to the a first electrode of the light-emitting unit; wherein the display panel further comprises: a third conductive layer on a side of the substrate; a fourth conductive layer on a side, away from the substrate, of the third conductive layer, the fourth conductive layer comprising the second initial signal line, wherein the second initial signal line comprises a first initial signal sub-line and/or a second initial signal sub-line; and wherein an orthographic projection of the first initial signal sub-line on the substrate extends in a first direction, and an orthographic projection of the second initial signal sub-line on the substrate extends in a second direction, the first direction and the second direction intersecting.
14. (Currently Amended) The display panel according to claim 13, wherein, when the second initial signal line comprises the first initial signal sub-line, an orthographic projection of the first initial signal sub-line on the substrate is at least partially overlapped with an orthographic projection of the third initial signal line on the substrate; and wherein, in a second unit pixel, an area of the orthographic projection of the first initial signal sub-line on the substrate is S3; an overlapping area, between the orthographic projection of the first initial signal sub-line on the substrate and the orthographic projection of the third initial signal line on the substrate, is S4; and S4/S3 is greater than or equal to 50%.
15. (Cancelled)
Claims 16-17 depend on claim 13.
18. (Original) The display panel according to claim 1, comprising a plurality of repeatable units distributed in an array along a first direction and a second direction, wherein the repeatable unit comprises two pixel driving circuits distributed along the first direction, and the two pixel driving circuits in the same repeatable unit are disposed in mirror symmetry with respect to a mirror symmetry plane, the first direction and the second direction intersecting; wherein the pixel driving circuit further comprises a fifth transistor, a first electrode of the fifth transistor being connected to a power line, and a second electrode of the fifth transistor being connected to the first electrode of the driver transistor; wherein the display panel further comprises: a first active layer comprising a third active portion, a fifth active portion, and a thirteenth active portion, wherein the third active portion is configured to form a channel region of the driver transistor, the fifth active portion is configured to form a channel region of the fifth transistor, and the thirteenth active portion is connected to a side, away from the third active portion, of the fifth active portion; and wherein, in repeatable units adjacent in the first direction, the fifth active portions in two adjacent pixel driving circuits are connected through the same thirteenth active portion, and the thirteenth active portion is connected to the power line.
19. (Original) The display panel according to claim 1, comprising a plurality of repeatable units distributed in an array along a first direction and a second direction, wherein the repeatable unit comprises two pixel driving circuits distributed along the first direction, and the two pixel driving circuits in the same repeatable unit are disposed in mirror symmetry with respect to a mirror symmetry plane, the first direction and the second direction intersecting; wherein the display panel further comprises a light-emitting unit, the pixel driving circuit is connected to a first electrode of the light-emitting unit, and the pixel driving circuit further comprises a sixth transistor and a seventh transistor, and wherein a first electrode of the sixth transistor is connected to the second electrode of the driver transistor, a second electrode of the sixth transistor is connected to the first electrode of the light-emitting unit, a first electrode of the seventh transistor is connected to a second initial signal line, and a second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit; wherein the display panel further comprises: a first active layer comprising a sixth active portion, a seventh active portion, and a seventeenth active portion, wherein the sixth active portion is configured to form a channel region of the sixth transistor, the seventh active portion is configured to form a channel region of the seventh transistor, and the seventeenth active portion is connected to a side, away from the sixth active portion, of the seventh active portion; and wherein, in a same repeatable unit, the seventh active portions in two adjacent pixel driving circuits are connected through the same seventeenth active portion, and the seventeenth active portion is connected to the second initial signal line.
20. (Original) The display panel according to claim 1, further comprising: a fourth conductive layer on a side of the substrate; a fifth conductive layer on a side, away from the substrate, of the fourth conductive layer, wherein the fifth conductive layer comprises a power line, an orthographic projection of the power line on the substrate extending in a second direction; wherein the power line comprises a first power line segment, a second power line segment, and a third power line segment, and wherein the second power line segment is connected between the first power line segment and the third power line segment, two adjacent second power line segments are connected in a same repeatable unit, the connected second power line segments form a power supply portion, and a plurality of the power supply portions comprise a first power supply portion and a second power supply portion; an electrode layer on a side, away from the substrate, of the fifth conductive layer, the electrode layer comprising a plurality of electrode portions, wherein the plurality of electrode portions comprise a first electrode portion and a second electrode portion, and an orthographic projection of the first electrode portion on the substrate is smaller than an orthographic projection of the second electrode portion on the substrate; and a pixel definition layer on a side, away from the substrate, of the electrode layer, the pixel definition layer having a plurality of openings formed for forming light-emitting units, wherein the plurality of openings are provided in correspondence with the electrode portions, and an orthographic projection of the opening on the substrate coincides with an orthographic projection of the electrode portion provided in correspondence with the opening on the substrate; wherein the first electrode portion is provided in correspondence with the first power supply portion, the second electrode portion is provided in correspondence with the second power supply portion, an orthographic projection of the first electrode portion on the substrate is at least partially overlapped with an orthographic projection of the first power supply portion provided in correspondence with the first electrode portion on the substrate, and an orthographic projection of the second electrode portion on the substrate is at least partially overlapped with an orthographic projection of the second power supply portion provided in correspondence with the second electrode portion on the substrate; and wherein an area of the orthographic projection of the second power supply portion on the substrate is greater than an area of the orthographic projection of the first power supply portion on the substrate, and an overlapping area, between the orthographic projection of the second power supply portion on the substrate and the orthographic projection of the second electrode portion corresponding to the second power supply portion on the substrate, is greater than an overlapping area, between the orthographic projection of the first power supply portion on the substrate and the orthographic projection of the first electrode portion corresponding to the first power supply portion on the substrate.
21. (Cancelled).
Conclusion
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/DEEPROSE SUBEDI/Primary Examiner, Art Unit 2627