Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12-22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12, lines 3-4 disclose that during an execution iteration, performing a one-time analysis process. This is in conflict with line 6, where it is disclosed that the execution iteration is subsequently performed. It is unclear whether the one-time analysis is performed during the execution operation or prior to the execution operation, as both are disclosed. Moreover, in lines 13-16, the one-time analysis process checks which functions are processed simultaneously during the execution iteration, which indicates that the one-time analysis process is occurring simultaneously with the execution operation.
Claims 13-22 depend from claim 12 and do not resolve the deficiencies of the parent claim, and are also rejected.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 12, 21 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Burchardt et al., US PGPub 2021/0149570, in view of Adachi et al., US PGPub 2010/0077170.
With respect to claim 12, Burchardt teaches a method for static allocation and assignment of information to memory areas of a processor-external memory of an information technology system during an execution iteration, the method comprising:
performing a one-time analysis process to statically allocate and assign the information to memory areas of the processor-external memory (par. 51, the creation and configuration of the memory area 111); and
subsequently performing the execution iteration based on the static allocation and assignment of the information to the memory areas of the processor-external memory, wherein during the execution iteration, the information technology system processes a plurality of concatenated functions during an execution iteration by a processor to solve a problem, and wherein each function of the concatenated functions provides an item of output data as information, wherein the output data can be read in by a function downstream in an information flow direction (pars. 74-77, the data is written into the output memory area for the process that needs to access the memory area (a function downstream)),
wherein in the one-time analysis process, the information technology system
checks which of the output data of the functions of the concatenated functions are processed simultaneously by the processor during the subsequently performed execution iteration (pars. 45-49, the MMU manages the plurality of process that access the same memory areas simultaneously); and
assigns the output data to fixed memory areas, wherein each item of output data is assigned to precisely one of the fixed memory areas, and wherein at least one first and one second item of the output data, which are processed during the execution iteration by the processor at different time points, are assigned to a same fixed memory area (pars. 51-68, which describe the creation and configuration of the memory area, particularly par. 53, which teaches assigning “output type” to fixed memory areas. Par. 48 discloses that a plurality of processes can access the same memory areas simultaneously); and
wherein during the execution iteration, the information technology system
writes the at least one first item of output data into the fixed memory areas assigned to the at least one first item of output data and leaves the at least one first item of output data in the fixed memory area at least until a function requiring the at least one first item of output data has been processed by the processor (par. 77, the data is written into the output memory area for the process that needs to access the memory area); and
Burchardt fails to teach reusing the fixed memory area. Adachi teaches:
writes the at least one second item of output data into the same fixed memory area to replace the at least one first item of output data, before the function requiring the second item of output data is processed by the processor (par. 57, when one program is completed using a memory area, the memory area is released and reused by another program).
It would have been obvious to one of ordinary skill in the art, having the teachings of Burchardt and Adachi before him before the earliest effective filing date, to modify the memory system of Burchardt with the memory system of Adachi, in order to increase the use efficiency of the memory area and eliminate the need for increasing the capacity of the memory.
Claim 21 is an information technology system comprising a microcontroller and configured to perform the method of claim 12, and is rejected using similar logic.
Claim 22 is directed towards a vehicle, comprising the information technology system of claim 21, and is rejected using similar logic.
Claim(s) 13-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Burchardt and Adachi, as applied to claim 12, in view of Park et al., US PGPub 2021/0081138.
With respect to claim 13, Burchardt and Adachi teach all limitations of the parent claim, but fail to disclose wherein a third item of output data is provided before a fourth item of output data, and the third item of output data and the fourth item of output data are assigned to different fixed memory areas when a function requiring the third item of output data is processed by the processor after a function requiring the fourth item of output data. Park teaches the method of claim 12, wherein a third item of output data is provided before a fourth item of output data, and the third item of output data and the fourth item of output data are assigned to different fixed memory areas when a function requiring the third item of output data is processed by the processor after a function requiring the fourth item of output data (par. 93, data B is the third item of output data and data C is the fourth item of output data, and the function requiring the fourth item of output data is CAS TBM C’. The CAS TBM C’ command occurs before the system issues the CAS TBM B command for data B).
It would have been obvious to one of ordinary skill in the art, having the teachings of Burchardt, Adachi and Park before him before the earliest effective filing date, to modify the memory access method of Burchardt and Adachi with the memory access method of Park, in order to have both DRAM and non-volatile memory, in order to be able to restore content back into main memory after a power failure, as taught by Park in pars. 53-54.
With respect to claim 14, Burchardt and Adachi teach all limitations of the parent claim, but fail to disclose an auxiliary memory. Park teaches the method of claim 12, wherein the memory comprises a main memory, the information technology system is equipped with at least one auxiliary memory and, to replace the at least one first item of output data with the at least one second item of output data, the at least one first item of output data is discarded from the main memory or the at least one first item of output data is relocated to the at least one auxiliary memory (pars. 74 and 76, the DRAM is the main memory and the NVM is the auxiliary memory. New data is loaded in (replaced) in DRAM and data is swapped out (relocated) to NVM).
It would have been obvious to one of ordinary skill in the art, having the teachings of Burchardt, Adachi and Park before him before the earliest effective filing date, to modify the memory access method of Burchardt and Adachi with the memory access method of Park, in order to have both DRAM and non-volatile memory, in order to be able to restore content back into main memory after a power failure, as taught by Park in pars. 53-54.
With respect to claim 15, Burchardt, Adachi and Park teach all limitations of the parent claim. Park further teaches the method of claim 14, wherein the at least one auxiliary memory has a different access time to the main memory (par. 56, Flash I/O speed is slower than DRAM speed).
With respect to claim 16, Burchardt, Adachi and Park teach all limitations of the parent claim. Burchardt further teaches the method of claim 14, wherein the information technology system solves at least two different problems, at least sometimes simultaneously (par. 48, a plurality of processes access the memory areas simultaneously).
With respect to claim 17, Burchardt, Adachi and Park teach all limitations of the parent claim. Park further teaches the method of claim 16, wherein output data of functions of a first problem are written into the main memory and output data of functions of a second problem are written into one of the at least one auxiliary memories (par. 72, the storage areas of the NVM and the main memory are for different functions).
With respect to claim 18, Burchardt and Adachi teach the limitations of the parent claim, but fail to teach wherein the information technology system determines memory requirement of each item of output data and only those items of output data having a substantially identical memory requirement are assigned to the same fixed memory area. Park teaches the method of claim 12, wherein the information technology system determines memory requirement of each item of output data and only those items of output data having a substantially identical memory requirement are assigned to the same fixed memory area (par. 72, the storage areas of the NVM and the main memory are for different functions, so output data for performing the same functions are assigned to the same area).
It would have been obvious to one of ordinary skill in the art, having the teachings of Burchardt, Adachi and Park before him before the earliest effective filing date, to modify the memory access method of Burchardt and Adachi with the memory access method of Park, in order to have both DRAM and non-volatile memory, in order to be able to restore content back into main memory after a power failure, as taught by Park in pars. 53-54.
With respect to claim 19, Burchardt and Adachi teach the limitations of the parent claim, but fail to teach wherein the information technology system determines memory requirement of each item of output data and only those items of output data having a substantially identical memory requirement are assigned to the same fixed memory area. Park teaches the method of claim 12, wherein the information technology system applies a genetic algorithm in the one-time analysis process to determine which items of output data are to be assigned to the same fixed memory area in each case (par. 72, determining which function is being performed to assign an area of memory).
It would have been obvious to one of ordinary skill in the art, having the teachings of Burchardt, Adachi and Park before him before the earliest effective filing date, to modify the memory access method of Burchardt and Adachi with the memory access method of Park, in order to have both DRAM and non-volatile memory, in order to be able to restore content back into main memory after a power failure, as taught by Park in pars. 53-54.
With respect to claim 20, Burchardt, Adachi and Park teach all limitations of the parent claim. Burchardt further teaches the method of claim 19, wherein a first optimization target is to minimize an entire run time of the problems to be solved (par. 13, the simultaneous access minimizes runtime) and a second optimization target is to minimize a proportion of the processor-external memory used by the fixed memory areas (par. 33, the memory space required is minimized).
Response to Arguments
Applicant's arguments filed 2/3/2026 have been fully considered but they are not persuasive. The rejection under 35 USC 112(b) regarding the “standard operation” is withdrawn, due to the claim amendment. However, the claim amendments make it unclear whether the one-time analysis process occurs before or during the execution iteration, as discussed in the rejection above.
Applicant’s arguments on pages 5-6 are directed towards Burchardt and Adachi disclosing dynamic memory allocation during an execution information, and not a one-time analysis process to statically allocate and assign information to memory areas that is used during a subsequently performed execution iteration. Firstly, while Applicant amended to recite that the execution iteration is “subsequently performed,” claim 12 actually describes that all the steps of claim 12 are performed “during an execution iteration” (line 3). Further, the limitation “wherein in the one-time analysis process, the information technology system checks which of the output data of the functions of the concatenated functions are processed simultaneously during the subsequently performed execution iteration” indicates that the one-time analysis process and execution operation are being performed at the same time, as the one-time analysis process has knowledge of which functions are being processed during the execution iteration. Nevertheless, the examiner believes that Burchardt does in fact teach the one-time analysis process occurs prior to a subsequent execution operation, as the examiner has mapped the configuration of the memory area, as described in pars. 44-68, as the one-time analysis process, and the real-time operation described in pars. 74-77 as the subsequent execution operation. The arguments on page 7 regarding claims 13-22 are moot, as Burchardt does in fact tech independent claim 12, as discussed above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN DARE whose telephone number is (571)272-4069. The examiner can normally be reached M-F 9:00-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at 571-272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/RYAN DARE/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132